Lines Matching +full:cache +full:- +full:block

1 /* SPDX-License-Identifier: GPL-2.0+ */
3  * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. All rights reserved.
9 #include <asm/cache.h>
13  * ARC architecture has additional address space - auxiliary registers.
21  * describe version of the HW block in question. Moreover if decoded version
22  * is 0 this means given HW block is absent - this is especially useful because
23  * we may safely read BRC regardless HW block existence while an attempt to
24  * access any other AUX regs associated with this HW block lead to imediate
27  * I.e. before using any cofigurable HW block it's required to make sure it
39 /* Instruction cache related auxiliary registers */
65 /* Data cache related auxiliary registers */
98 /* XY-memory related */
101 /* DSP-extensions related auxiliary registers */
115 /* ARCNUM [15:8] - field to identify each core in a multi-core system */