Lines Matching +full:0 +full:xcf
47 ELFNOTE(Xen, XEN_ELFNOTE_VIRT_BASE, _ASM_PTR 0x100000)
50 ELFNOTE(Xen, XEN_ELFNOTE_PADDR_OFFSET, _ASM_PTR 0)
59 * - `cr0`: bit 0 (PE) must be set. All the other writable bits are cleared.
61 * - `cs `: must be a 32-bit read/execute code segment with a base of ‘0’
62 * and a limit of ‘0xFFFFFFFF’. The selector value is unspecified.
64 * ‘0’ and a limit of ‘0xFFFFFFFF’. The selector values are all
66 * - `tr`: must be a 32-bit TSS (active) with a base of '0' and a limit
67 * of '0x67'.
82 ljmp $0x8,$.Lloadcs
84 mov $0x10,%eax
96 #define MSR_EFER 0xc0000080 /* extended feature register */
114 ljmp $0x8,$.Lenter64
130 out %ax, $0xf4
133 mov $0x604,%edx
134 mov $0x2000,%eax
150 out %al,$0xE9
159 idt_00: .int 0, 0
160 idt_01: .int 0, 0
161 idt_02: .int 0, 0
162 idt_03: .int 0, 0
163 idt_04: .int 0, 0
164 idt_05: .int 0, 0
165 idt_06: .int 0, 0 /* intr_6_opcode, Invalid Opcode */
166 idt_07: .int 0, 0
167 idt_08: .int 0, 0
168 idt_09: .int 0, 0
169 idt_0A: .int 0, 0
170 idt_0B: .int 0, 0
171 idt_0C: .int 0, 0
172 idt_0D: .int 0, 0
173 idt_0E: .int 0, 0
174 idt_0F: .int 0, 0
175 idt_10: .int 0, 0
176 idt_11: .int 0, 0
177 idt_12: .int 0, 0
178 idt_13: .int 0, 0
179 idt_14: .int 0, 0
180 idt_15: .int 0, 0
181 idt_16: .int 0, 0
182 idt_17: .int 0, 0
183 idt_18: .int 0, 0
184 idt_19: .int 0, 0
185 idt_1A: .int 0, 0
186 idt_1B: .int 0, 0
187 idt_1C: .int 0, 0
188 idt_1D: .int 0, 0
189 idt_1E: .int 0, 0
190 idt_1F: .int 0, 0
204 .short 0
210 .short 0xFFFF
211 .short 0
212 .byte 0
213 .byte 0x9b
214 .byte 0xCF
215 .byte 0
218 .short 0xFFFF
219 .short 0
220 .byte 0
221 .byte 0x93
222 .byte 0xCF
223 .byte 0
227 .short 0
233 .short 0xFFFF
234 .short 0
235 .byte 0
236 .byte 0x9b
237 .byte 0xAF
238 .byte 0
241 .short 0xFFFF
242 .short 0
243 .byte 0
244 .byte 0x93
245 .byte 0xCF
246 .byte 0
259 i = 0
261 .quad 0x1e7 | (i << 21)
267 .quad .Lpd + 7 + 0 * 4096 /* 0-1 GB */
274 .quad .Lpdp + 7 /* 0-512 GB */