51 static void test_end(TestData *d)  in test_end()  argument
53     g_free(d->dev);  in test_end()
54     qpci_free_pc(d->bus);  in test_end()
55     qtest_quit(d->qts);  in test_end()
58 static void test_init(TestData *d)  in test_init()  argument
63                      d->noreboot ? "-global ICH9-LPC.noreboot=true" : "",  in test_init()
64                      !d->args ? "" : d->args);  in test_init()
67     d->bus = qpci_new_pc(qs, NULL);  in test_init()
68     d->dev = qpci_device_find(d->bus, QPCI_DEVFN(0x1f, 0x00));  in test_init()
69     g_assert(d->dev != NULL);  in test_init()
71     qpci_device_enable(d->dev);  in test_init()
74     qpci_config_writel(d->dev, ICH9_LPC_PMBASE, PM_IO_BASE_ADDR | 0x1);  in test_init()
76     qpci_config_writeb(d->dev, ICH9_LPC_ACPI_CTRL, 0x80);  in test_init()
78     qpci_config_writel(d->dev, ICH9_LPC_RCBA, RCBA_BASE_ADDR | 0x1);  in test_init()
80     d->tco_io_bar = qpci_legacy_iomap(d->dev, PM_IO_BASE_ADDR + 0x60);  in test_init()
81     d->qts = qs;  in test_init()
84 static void stop_tco(const TestData *d)  in stop_tco()  argument
88     val = qpci_io_readw(d->dev, d->tco_io_bar, TCO1_CNT);  in stop_tco()
90     qpci_io_writew(d->dev, d->tco_io_bar, TCO1_CNT, val);  in stop_tco()
93 static void start_tco(const TestData *d)  in start_tco()  argument
97     val = qpci_io_readw(d->dev, d->tco_io_bar, TCO1_CNT);  in start_tco()
99     qpci_io_writew(d->dev, d->tco_io_bar, TCO1_CNT, val);  in start_tco()
102 static void load_tco(const TestData *d)  in load_tco()  argument
104     qpci_io_writew(d->dev, d->tco_io_bar, TCO_RLD, 4);  in load_tco()
107 static void set_tco_timeout(const TestData *d, uint16_t ticks)  in set_tco_timeout()  argument
109     qpci_io_writew(d->dev, d->tco_io_bar, TCO_TMR, ticks);  in set_tco_timeout()
112 static void clear_tco_status(const TestData *d)  in clear_tco_status()  argument
114     qpci_io_writew(d->dev, d->tco_io_bar, TCO1_STS, 0x0008);  in clear_tco_status()
115     qpci_io_writew(d->dev, d->tco_io_bar, TCO2_STS, 0x0002);  in clear_tco_status()
116     qpci_io_writew(d->dev, d->tco_io_bar, TCO2_STS, 0x0004);  in clear_tco_status()
134     TestData d;  in test_tco_defaults()  local
136     d.args = NULL;  in test_tco_defaults()
137     d.noreboot = true;  in test_tco_defaults()
138     test_init(&d);  in test_tco_defaults()
139     g_assert_cmpint(qpci_io_readw(d.dev, d.tco_io_bar, TCO_RLD), ==,  in test_tco_defaults()
142     g_assert_cmpint(qpci_io_readw(d.dev, d.tco_io_bar, TCO_DAT_IN), ==,  in test_tco_defaults()
145     g_assert_cmpint(qpci_io_readl(d.dev, d.tco_io_bar, TCO1_STS), ==,  in test_tco_defaults()
148     g_assert_cmpint(qpci_io_readl(d.dev, d.tco_io_bar, TCO1_CNT), ==,  in test_tco_defaults()
151     g_assert_cmpint(qpci_io_readw(d.dev, d.tco_io_bar, TCO_MESSAGE1), ==,  in test_tco_defaults()
153     g_assert_cmpint(qpci_io_readb(d.dev, d.tco_io_bar, TCO_WDCNT), ==,  in test_tco_defaults()
155     g_assert_cmpint(qpci_io_readb(d.dev, d.tco_io_bar, SW_IRQ_GEN), ==,  in test_tco_defaults()
157     g_assert_cmpint(qpci_io_readw(d.dev, d.tco_io_bar, TCO_TMR), ==,  in test_tco_defaults()
159     test_end(&d);  in test_tco_defaults()
164     TestData d;  in test_tco_timeout()  local
169     d.args = NULL;  in test_tco_timeout()
170     d.noreboot = true;  in test_tco_timeout()
171     test_init(&d);  in test_tco_timeout()
173     stop_tco(&d);  in test_tco_timeout()
174     clear_tco_status(&d);  in test_tco_timeout()
175     reset_on_second_timeout(&d, false);  in test_tco_timeout()
176     set_tco_timeout(&d, ticks);  in test_tco_timeout()
177     load_tco(&d);  in test_tco_timeout()
178     start_tco(&d);  in test_tco_timeout()
179     qtest_clock_step(d.qts, ticks * TCO_TICK_NSEC);  in test_tco_timeout()
182     val = qpci_io_readw(d.dev, d.tco_io_bar, TCO1_STS);  in test_tco_timeout()
188     qpci_io_writew(d.dev, d.tco_io_bar, TCO1_STS, val);  in test_tco_timeout()
189     val = qpci_io_readw(d.dev, d.tco_io_bar, TCO1_STS);  in test_tco_timeout()
194     qtest_clock_step(d.qts, ticks * TCO_TICK_NSEC);  in test_tco_timeout()
195     val = qpci_io_readw(d.dev, d.tco_io_bar, TCO1_STS);  in test_tco_timeout()
198     val = qpci_io_readw(d.dev, d.tco_io_bar, TCO2_STS);  in test_tco_timeout()
202     stop_tco(&d);  in test_tco_timeout()
203     test_end(&d);  in test_tco_timeout()
208     TestData d;  in test_tco_max_timeout()  local
213     d.args = NULL;  in test_tco_max_timeout()
214     d.noreboot = true;  in test_tco_max_timeout()
215     test_init(&d);  in test_tco_max_timeout()
217     stop_tco(&d);  in test_tco_max_timeout()
218     clear_tco_status(&d);  in test_tco_max_timeout()
219     reset_on_second_timeout(&d, false);  in test_tco_max_timeout()
220     set_tco_timeout(&d, ticks);  in test_tco_max_timeout()
221     load_tco(&d);  in test_tco_max_timeout()
222     start_tco(&d);  in test_tco_max_timeout()
223     qtest_clock_step(d.qts, ((ticks & TCO_TMR_MASK) - 1) * TCO_TICK_NSEC);  in test_tco_max_timeout()
225     val = qpci_io_readw(d.dev, d.tco_io_bar, TCO_RLD);  in test_tco_max_timeout()
227     val = qpci_io_readw(d.dev, d.tco_io_bar, TCO1_STS);  in test_tco_max_timeout()
230     qtest_clock_step(d.qts, TCO_TICK_NSEC);  in test_tco_max_timeout()
231     val = qpci_io_readw(d.dev, d.tco_io_bar, TCO1_STS);  in test_tco_max_timeout()
235     stop_tco(&d);  in test_tco_max_timeout()
236     test_end(&d);  in test_tco_max_timeout()
352     TestData d;  in test_tco_ticks_counter()  local
356     d.args = NULL;  in test_tco_ticks_counter()
357     d.noreboot = true;  in test_tco_ticks_counter()
358     test_init(&d);  in test_tco_ticks_counter()
360     stop_tco(&d);  in test_tco_ticks_counter()
361     clear_tco_status(&d);  in test_tco_ticks_counter()
362     reset_on_second_timeout(&d, false);  in test_tco_ticks_counter()
363     set_tco_timeout(&d, ticks);  in test_tco_ticks_counter()
364     load_tco(&d);  in test_tco_ticks_counter()
365     start_tco(&d);  in test_tco_ticks_counter()
368         rld = qpci_io_readw(d.dev, d.tco_io_bar, TCO_RLD) & TCO_RLD_MASK;  in test_tco_ticks_counter()
370         qtest_clock_step(d.qts, TCO_TICK_NSEC);  in test_tco_ticks_counter()
372     } while (!(qpci_io_readw(d.dev, d.tco_io_bar, TCO1_STS) & TCO_TIMEOUT));  in test_tco_ticks_counter()
374     stop_tco(&d);  in test_tco_ticks_counter()
375     test_end(&d);  in test_tco_ticks_counter()
380     TestData d;  in test_tco1_control_bits()  local
383     d.args = NULL;  in test_tco1_control_bits()
384     d.noreboot = true;  in test_tco1_control_bits()
385     test_init(&d);  in test_tco1_control_bits()
388     qpci_io_writew(d.dev, d.tco_io_bar, TCO1_CNT, val);  in test_tco1_control_bits()
390     qpci_io_writew(d.dev, d.tco_io_bar, TCO1_CNT, val);  in test_tco1_control_bits()
391     g_assert_cmpint(qpci_io_readw(d.dev, d.tco_io_bar, TCO1_CNT), ==,  in test_tco1_control_bits()
393     test_end(&d);  in test_tco1_control_bits()
398     TestData d;  in test_tco1_status_bits()  local
403     d.args = NULL;  in test_tco1_status_bits()
404     d.noreboot = true;  in test_tco1_status_bits()
405     test_init(&d);  in test_tco1_status_bits()
407     stop_tco(&d);  in test_tco1_status_bits()
408     clear_tco_status(&d);  in test_tco1_status_bits()
409     reset_on_second_timeout(&d, false);  in test_tco1_status_bits()
410     set_tco_timeout(&d, ticks);  in test_tco1_status_bits()
411     load_tco(&d);  in test_tco1_status_bits()
412     start_tco(&d);  in test_tco1_status_bits()
413     qtest_clock_step(d.qts, ticks * TCO_TICK_NSEC);  in test_tco1_status_bits()
415     qpci_io_writeb(d.dev, d.tco_io_bar, TCO_DAT_IN, 0);  in test_tco1_status_bits()
416     qpci_io_writeb(d.dev, d.tco_io_bar, TCO_DAT_OUT, 0);  in test_tco1_status_bits()
417     val = qpci_io_readw(d.dev, d.tco_io_bar, TCO1_STS);  in test_tco1_status_bits()
420     qpci_io_writew(d.dev, d.tco_io_bar, TCO1_STS, val);  in test_tco1_status_bits()
421     g_assert_cmpint(qpci_io_readw(d.dev, d.tco_io_bar, TCO1_STS), ==, 0);  in test_tco1_status_bits()
422     test_end(&d);  in test_tco1_status_bits()
427     TestData d;  in test_tco2_status_bits()  local
432     d.args = NULL;  in test_tco2_status_bits()
433     d.noreboot = true;  in test_tco2_status_bits()
434     test_init(&d);  in test_tco2_status_bits()
436     stop_tco(&d);  in test_tco2_status_bits()
437     clear_tco_status(&d);  in test_tco2_status_bits()
438     reset_on_second_timeout(&d, true);  in test_tco2_status_bits()
439     set_tco_timeout(&d, ticks);  in test_tco2_status_bits()
440     load_tco(&d);  in test_tco2_status_bits()
441     start_tco(&d);  in test_tco2_status_bits()
442     qtest_clock_step(d.qts, ticks * TCO_TICK_NSEC * 2);  in test_tco2_status_bits()
444     val = qpci_io_readw(d.dev, d.tco_io_bar, TCO2_STS);  in test_tco2_status_bits()
447     qpci_io_writew(d.dev, d.tco_io_bar, TCO2_STS, val);  in test_tco2_status_bits()
448     g_assert_cmpint(qpci_io_readw(d.dev, d.tco_io_bar, TCO2_STS), ==, 0);  in test_tco2_status_bits()
449     test_end(&d);  in test_tco2_status_bits()