tests/qtest/npcm7xx_smbus-test.c

24 #define SMBUS_ADDR(x)       (0xf0080000 + 0x1000 * (x))
27 #define EVB_DEVICE_ADDR     0x48
28 #define INVALID_DEVICE_ADDR 0x01
30 const int evb_bus_list[] = {0, 1, 2, 6};
34     OFFSET_SDA     = 0x0,
35     OFFSET_ST      = 0x2,
36     OFFSET_CST     = 0x4,
37     OFFSET_CTL1    = 0x6,
38     OFFSET_ADDR1   = 0x8,
39     OFFSET_CTL2    = 0xa,
40     OFFSET_ADDR2   = 0xc,
41     OFFSET_CTL3    = 0xe,
42     OFFSET_CST2    = 0x18,
43     OFFSET_CST3    = 0x19,
47     OFFSET_ADDR3   = 0x10,
48     OFFSET_ADDR7   = 0x11,
49     OFFSET_ADDR4   = 0x12,
50     OFFSET_ADDR8   = 0x13,
51     OFFSET_ADDR5   = 0x14,
52     OFFSET_ADDR9   = 0x15,
53     OFFSET_ADDR6   = 0x16,
54     OFFSET_ADDR10  = 0x17,
55     OFFSET_CTL4    = 0x1a,
56     OFFSET_CTL5    = 0x1b,
57     OFFSET_SCLLT   = 0x1c,
58     OFFSET_FIF_CTL = 0x1d,
59     OFFSET_SCLHT   = 0x1e,
63     OFFSET_FIF_CTS  = 0x10,
64     OFFSET_FAIR_PER = 0x11,
65     OFFSET_TXF_CTL  = 0x12,
66     OFFSET_T_OUT    = 0x14,
67     OFFSET_TXF_STS  = 0x1a,
68     OFFSET_RXF_STS  = 0x1c,
69     OFFSET_RXF_CTL  = 0x1e,
80 #define ST_XMIT             BIT(0)
90 #define CST_BUSY            BIT(0)
100 #define CST2_MATCH1F        BIT(0)
106 #define CST3_MATCH8F        BIT(0)
116 #define CTL1_START          BIT(0)
120 #define CTL2_ENABLE         BIT(0)
129 #define CTL3_SCLFRQ(rv)     extract8((rv), 0, 2)
133 #define ADDR_A(rv)          extract8((rv), 0, 6)
145 #define TXF_CTL_TX_THR(rv)      extract8((rv), 0, 5)
149 #define TXF_STS_TX_BYTES(rv)    extract8((rv), 0, 5)
154 #define RXF_CTL_RX_THR(rv)      extract8((rv), 0, 5)
158 #define RXF_STS_RX_BYTES(rv)    extract8((rv), 0, 5)
184     g_assert_cmphex(qtest_readb(qts, base_addr + OFFSET_ST), ==, 0);  in check_stopped()
250     choose_bank(qts, base_addr, 0);  in check_recv()
277     uint8_t encoded_addr = (addr << 1) | (recv ? 1 : 0);  in send_address()
317     choose_bank(qts, base_addr, 0);  in start_fifo_mode()
326     g_assert_cmphex(qtest_readb(qts, base_addr + OFFSET_TXF_STS), ==, 0);  in start_fifo_mode()
327     g_assert_cmphex(qtest_readb(qts, base_addr + OFFSET_RXF_STS), ==, 0);  in start_fifo_mode()
333     qtest_writeb(qts, base_addr + OFFSET_TXF_CTL, 0);  in start_recv_fifo()
346     g_assert_cmphex(qtest_readb(qts, base_addr + OFFSET_CTL1), ==, 0);  in test_disable_bus()
347     g_assert_cmphex(qtest_readb(qts, base_addr + OFFSET_ST), ==, 0);  in test_disable_bus()
349     g_assert_cmphex(qtest_readb(qts, base_addr + OFFSET_CST), ==, 0);  in test_disable_bus()
381     uint8_t value = 0x60;  in test_single_mode()
417     uint8_t value = 0x60;  in test_fifo_mode()
439                         qtest_readb(qts, base_addr + OFFSET_TXF_STS)), ==, 0);  in test_fifo_mode()
464                         qtest_readb(qts, base_addr + OFFSET_RXF_STS)), ==, 0);  in test_fifo_mode()
484     for (i = 0; i < NR_SMBUS_DEVICES; ++i) {  in main()
489     for (i = 0; i < ARRAY_SIZE(evb_bus_list); ++i) {  in main()