Lines Matching +full:0 +full:xf0801000
28 #define CH_EN BIT(0)
33 #define PPR 0x00
34 #define CSR 0x04
35 #define PCR 0x08
36 #define PIER 0x3c
37 #define PIIR 0x40
40 #define CLK_BA 0xf0801000
41 #define CLKSEL 0x04
42 #define CLKDIV1 0x08
43 #define CLKDIV2 0x2c
44 #define PLLCON0 0x0c
45 #define PLLCON1 0x10
46 #define PLL_INDV(rv) extract32((rv), 0, 6)
52 #define CLK2CKDIV(rv) extract32((rv), 0, 1)
54 #define CPUCKSEL(rv) extract32((rv), 0, 2)
59 #define MFT_BA(n) (0xf0180000 + ((n) * 0x1000))
61 #define MFT_CNT1 0x00
62 #define MFT_CRA 0x02
63 #define MFT_CRB 0x04
64 #define MFT_CNT2 0x06
65 #define MFT_PRSC 0x08
66 #define MFT_CKC 0x0a
67 #define MFT_MCTRL 0x0c
68 #define MFT_ICTRL 0x0e
69 #define MFT_ICLR 0x10
70 #define MFT_IEN 0x12
71 #define MFT_CPA 0x14
72 #define MFT_CPB 0x16
73 #define MFT_CPCFG 0x18
74 #define MFT_INASEL 0x1a
75 #define MFT_INBSEL 0x1c
77 #define MFT_MCTRL_ALL 0x64
78 #define MFT_ICLR_ALL 0x3f
79 #define MFT_IEN_ALL 0x3f
80 #define MFT_CPCFG_EQ_MODE 0x44
83 #define MFT_CKC_C1CSEL BIT(0)
90 #define MFT_ICTRL_TAPND BIT(0)
92 #define MFT_MAX_CNT 0xffff
93 #define MFT_TIMEOUT 0x5000
121 .base_addr = 0xf0103000
125 .base_addr = 0xf0104000
131 .cnr_offset = 0x0c,
132 .cmr_offset = 0x10,
133 .pdr_offset = 0x14,
134 .pwdr_offset = 0x44,
137 .cnr_offset = 0x18,
138 .cmr_offset = 0x1c,
139 .pdr_offset = 0x20,
140 .pwdr_offset = 0x48,
143 .cnr_offset = 0x24,
144 .cmr_offset = 0x28,
145 .pdr_offset = 0x2c,
146 .pwdr_offset = 0x4c,
149 .cnr_offset = 0x30,
150 .cmr_offset = 0x34,
151 .pdr_offset = 0x38,
152 .pwdr_offset = 0x50,
156 static const int ppr_base[] = { 0, 0, 8, 8 };
157 static const int csr_base[] = { 0, 4, 8, 12 };
158 static const int pcr_base[] = { 0, 8, 12, 16 };
161 0,
169 0,
177 0,
189 0,
206 g_assert(diff >= 0 && diff < ARRAY_SIZE(pwm_module_list)); in pwm_module_index()
216 g_assert(diff >= 0 && diff < ARRAY_SIZE(pwm_list)); in pwm_index()
298 case 0: in read_pclk()
322 case 0: in pwm_selector()
347 if (cnr == 0) { in pwm_compute_duty()
349 duty = 0; in pwm_compute_duty()
472 mft_writeb(qts, index, MFT_CKC, 0); in mft_init()
476 mft_writeb(qts, index, MFT_INASEL, 0); in mft_init()
477 mft_writeb(qts, index, MFT_INBSEL, 0); in mft_init()
487 mft_qom_set(qts, index, "max_rpm[0]", DEFAULT_RPM); in mft_init()
495 if (rpm == 0) { in mft_compute_cnt()
524 mft_writeb(qts, index, MFT_CKC, 0); in mft_verify_rpm()
562 g_assert_cmpuint(pwm_get_freq(qts, module, pwm), ==, 0); in test_init()
563 g_assert_cmpuint(pwm_get_duty(qts, module, pwm), ==, 0); in test_init()
579 for (i = 0; i < ARRAY_SIZE(ppr_list); ++i) { in test_oneshot()
583 for (j = 0; j < ARRAY_SIZE(csr_list); ++j) { in test_oneshot()
591 g_assert_cmpuint(pwm_get_freq(qts, module, pwm), ==, 0); in test_oneshot()
592 g_assert_cmpuint(pwm_get_duty(qts, module, pwm), ==, 0); in test_oneshot()
614 for (i = 0; i < ARRAY_SIZE(ppr_list); ++i) { in test_toggle()
618 for (j = 0; j < ARRAY_SIZE(csr_list); ++j) { in test_toggle()
622 for (k = 0; k < ARRAY_SIZE(cnr_list); k += cnr_step) { in test_toggle()
626 for (l = 0; l < ARRAY_SIZE(cmr_list); ++l) { in test_toggle()
640 if (expected_duty != 0 && expected_duty != 100) { in test_toggle()
641 /* Duty cycle with 0 or 100 doesn't need frequency. */ in test_toggle()
655 if (expected_duty != 0 && expected_duty != 100) { in test_toggle()
656 /* Duty cycle with 0 or 100 doesn't need frequency. */ in test_toggle()
697 for (int i = 0; i < pwm_module_list_cnt; ++i) { in main()
698 for (int j = 0; j < pwm_list_cnt; ++j) { in main()