tests/qtest/npcm7xx_gpio-test.c

2  * QTest testcase for the Nuvoton NPCM7xx GPIO modules.
21 #define GPIO(x)         (0xf0010000 + (x) * 0x1000)  macro
24 /* GPIO registers */
58     if (readl(GPIO(n) + GP_N_TLOCK1) != 0) {  in gpio_unlock()
59         writel(GPIO(n) + GP_N_TLOCK2, 0xc0de1248);  in gpio_unlock()
60         writel(GPIO(n) + GP_N_TLOCK1, 0xc0defa73);  in gpio_unlock()
64 /* Restore the GPIO controller to a sensible default state. */
69     writel(GPIO(n) + GP_N_EVEN, 0x00000000);  in gpio_reset()
70     writel(GPIO(n) + GP_N_EVST, 0xffffffff);  in gpio_reset()
71     writel(GPIO(n) + GP_N_POL, 0x00000000);  in gpio_reset()
72     writel(GPIO(n) + GP_N_DOUT, 0x00000000);  in gpio_reset()
73     writel(GPIO(n) + GP_N_OE, 0x00000000);  in gpio_reset()
74     writel(GPIO(n) + GP_N_OTYP, 0x00000000);  in gpio_reset()
75     writel(GPIO(n) + GP_N_PU, 0xffffffff);  in gpio_reset()
76     writel(GPIO(n) + GP_N_PD, 0x00000000);  in gpio_reset()
77     writel(GPIO(n) + GP_N_IEM, 0xffffffff);  in gpio_reset()
85     writel(GPIO(0) + GP_N_OE, 0xffffffff);  in test_dout_to_din()
87     writel(GPIO(0) + GP_N_PU, 0xffff0000);  in test_dout_to_din()
88     writel(GPIO(0) + GP_N_PD, 0x0000ffff);  in test_dout_to_din()
89     writel(GPIO(0) + GP_N_DOUT, 0x12345678);  in test_dout_to_din()
90     g_assert_cmphex(readl(GPIO(0) + GP_N_DOUT), ==, 0x12345678);  in test_dout_to_din()
91     g_assert_cmphex(readl(GPIO(0) + GP_N_DIN), ==, 0x12345678);  in test_dout_to_din()
103     writel(GPIO(0) + GP_N_OE, 0x00000000);  in test_pullup_pulldown()
105     writel(GPIO(0) + GP_N_DOUT, 0xffff0000);  in test_pullup_pulldown()
106     writel(GPIO(0) + GP_N_PU, 0x23456789);  in test_pullup_pulldown()
107     writel(GPIO(0) + GP_N_PD, ~0x23456789U);  in test_pullup_pulldown()
108     g_assert_cmphex(readl(GPIO(0) + GP_N_PU), ==, 0x23456789);  in test_pullup_pulldown()
109     g_assert_cmphex(readl(GPIO(0) + GP_N_PD), ==, ~0x23456789U);  in test_pullup_pulldown()
110     g_assert_cmphex(readl(GPIO(0) + GP_N_DIN), ==, 0x23456789);  in test_pullup_pulldown()
121     writel(GPIO(0) + GP_N_DOUT, 0xffffffff);  in test_output_enable()
122     writel(GPIO(0) + GP_N_PU, 0x00000000);  in test_output_enable()
123     writel(GPIO(0) + GP_N_PD, 0xffffffff);  in test_output_enable()
124     writel(GPIO(0) + GP_N_OE, 0x3456789a);  in test_output_enable()
125     g_assert_cmphex(readl(GPIO(0) + GP_N_OE), ==, 0x3456789a);  in test_output_enable()
126     g_assert_cmphex(readl(GPIO(0) + GP_N_DIN), ==, 0x3456789a);  in test_output_enable()
128     writel(GPIO(0) + GP_N_OEC, 0x00030002);  in test_output_enable()
129     g_assert_cmphex(readl(GPIO(0) + GP_N_OE), ==, 0x34547898);  in test_output_enable()
130     g_assert_cmphex(readl(GPIO(0) + GP_N_DIN), ==, 0x34547898);  in test_output_enable()
132     writel(GPIO(0) + GP_N_OES, 0x0000f001);  in test_output_enable()
133     g_assert_cmphex(readl(GPIO(0) + GP_N_OE), ==, 0x3454f899);  in test_output_enable()
134     g_assert_cmphex(readl(GPIO(0) + GP_N_DIN), ==, 0x3454f899);  in test_output_enable()
147     writel(GPIO(0) + GP_N_OTYP, 0x456789ab);  in test_open_drain()
148     writel(GPIO(0) + GP_N_OE, 0xf0f0f0f0);  in test_open_drain()
149     writel(GPIO(0) + GP_N_DOUT, 0xffff0000);  in test_open_drain()
150     writel(GPIO(0) + GP_N_PU, 0xff00ff00);  in test_open_drain()
151     writel(GPIO(0) + GP_N_PD, 0x00ff00ff);  in test_open_drain()
152     g_assert_cmphex(readl(GPIO(0) + GP_N_OTYP), ==, 0x456789ab);  in test_open_drain()
153     g_assert_cmphex(readl(GPIO(0) + GP_N_DIN), ==, 0xff900f00);  in test_open_drain()
164     writel(GPIO(0) + GP_N_OTYP, 0x00000000);  in test_polarity()
165     writel(GPIO(0) + GP_N_OE, 0xffffffff);  in test_polarity()
166     writel(GPIO(0) + GP_N_DOUT, 0x56789abc);  in test_polarity()
167     writel(GPIO(0) + GP_N_POL, 0x6789abcd);  in test_polarity()
168     g_assert_cmphex(readl(GPIO(0) + GP_N_POL), ==, 0x6789abcd);  in test_polarity()
169     g_assert_cmphex(readl(GPIO(0) + GP_N_DIN), ==, 0x56789abc);  in test_polarity()
175     writel(GPIO(0) + GP_N_OE, 0x00000000);  in test_polarity()
176     writel(GPIO(0) + GP_N_POL, 0xffffffff);  in test_polarity()
177     writel(GPIO(0) + GP_N_PU, 0x789abcde);  in test_polarity()
178     writel(GPIO(0) + GP_N_PD, ~0x789abcdeU);  in test_polarity()
179     g_assert_cmphex(readl(GPIO(0) + GP_N_DIN), ==, ~0x789abcdeU);  in test_polarity()
185     writel(GPIO(0) + GP_N_OTYP, 0xffffffff);  in test_polarity()
186     writel(GPIO(0) + GP_N_OE, 0xffffffff);  in test_polarity()
187     writel(GPIO(0) + GP_N_PU, 0xffff0000);  in test_polarity()
188     writel(GPIO(0) + GP_N_PD, 0x0000ffff);  in test_polarity()
189     writel(GPIO(0) + GP_N_DOUT, 0xff00ff00);  in test_polarity()
190     g_assert_cmphex(readl(GPIO(0) + GP_N_DIN), ==, 0xff00ffff);  in test_polarity()
198     writel(GPIO(0) + GP_N_OE, 0xffffffff);  in test_input_mask()
199     writel(GPIO(0) + GP_N_DOUT, 0xff00ff00);  in test_input_mask()
200     writel(GPIO(0) + GP_N_POL, 0xffff0000);  in test_input_mask()
201     writel(GPIO(0) + GP_N_IEM, 0x87654321);  in test_input_mask()
202     g_assert_cmphex(readl(GPIO(0) + GP_N_DIN), ==, 0xff9a4300);  in test_input_mask()
209     writel(GPIO(0) + GP_N_DOUT, 0x98765432);  in test_temp_lock()
212     g_assert_cmphex(readl(GPIO(0) + GP_N_TLOCK1), ==, 0);  in test_temp_lock()
214     writel(GPIO(0) + GP_N_TLOCK1, 0);  in test_temp_lock()
215     g_assert_cmphex(readl(GPIO(0) + GP_N_TLOCK1), ==, 1);  in test_temp_lock()
216     writel(GPIO(0) + GP_N_DOUT, 0xa9876543);  in test_temp_lock()
217     g_assert_cmphex(readl(GPIO(0) + GP_N_DOUT), ==, 0x98765432);  in test_temp_lock()
220     g_assert_cmphex(readl(GPIO(0) + GP_N_TLOCK1), ==, 0);  in test_temp_lock()
221     writel(GPIO(0) + GP_N_DOUT, 0xa9876543);  in test_temp_lock()
222     g_assert_cmphex(readl(GPIO(0) + GP_N_DOUT), ==, 0xa9876543);  in test_temp_lock()
225     writel(GPIO(0) + GP_N_TLOCK2, 0);  in test_temp_lock()
226     g_assert_cmphex(readl(GPIO(0) + GP_N_TLOCK1), ==, 1);  in test_temp_lock()
227     writel(GPIO(0) + GP_N_DOUT, 0x98765432);  in test_temp_lock()
228     g_assert_cmphex(readl(GPIO(0) + GP_N_DOUT), ==, 0xa9876543);  in test_temp_lock()
231     g_assert_cmphex(readl(GPIO(0) + GP_N_TLOCK1), ==, 0);  in test_temp_lock()
232     writel(GPIO(0) + GP_N_DOUT, 0x98765432);  in test_temp_lock()
233     g_assert_cmphex(readl(GPIO(0) + GP_N_DOUT), ==, 0x98765432);  in test_temp_lock()
240     writel(GPIO(0) + GP_N_EVTYP, 0x00000000);  in test_events_level()
241     writel(GPIO(0) + GP_N_DOUT, 0xba987654);  in test_events_level()
242     writel(GPIO(0) + GP_N_OE, 0xffffffff);  in test_events_level()
243     writel(GPIO(0) + GP_N_EVST, 0xffffffff);  in test_events_level()
245     g_assert_cmphex(readl(GPIO(0) + GP_N_EVST), ==, 0xba987654);  in test_events_level()
247     writel(GPIO(0) + GP_N_DOUT, 0x00000000);  in test_events_level()
248     g_assert_cmphex(readl(GPIO(0) + GP_N_EVST), ==, 0xba987654);  in test_events_level()
250     writel(GPIO(0) + GP_N_EVST, 0x00007654);  in test_events_level()
251     g_assert_cmphex(readl(GPIO(0) + GP_N_EVST), ==, 0xba980000);  in test_events_level()
253     writel(GPIO(0) + GP_N_EVST, 0xba980000);  in test_events_level()
254     g_assert_cmphex(readl(GPIO(0) + GP_N_EVST), ==, 0x00000000);  in test_events_level()
262     writel(GPIO(0) + GP_N_EVTYP, 0xffffffff);  in test_events_rising_edge()
263     writel(GPIO(0) + GP_N_EVBE, 0x00000000);  in test_events_rising_edge()
264     writel(GPIO(0) + GP_N_DOUT, 0xffff0000);  in test_events_rising_edge()
265     writel(GPIO(0) + GP_N_OE, 0xffffffff);  in test_events_rising_edge()
266     writel(GPIO(0) + GP_N_EVST, 0xffffffff);  in test_events_rising_edge()
268     g_assert_cmphex(readl(GPIO(0) + GP_N_EVST), ==, 0x00000000);  in test_events_rising_edge()
270     writel(GPIO(0) + GP_N_DOUT, 0xff00ff00);  in test_events_rising_edge()
271     g_assert_cmphex(readl(GPIO(0) + GP_N_EVST), ==, 0x0000ff00);  in test_events_rising_edge()
273     writel(GPIO(0) + GP_N_DOUT, 0x00ff0000);  in test_events_rising_edge()
274     g_assert_cmphex(readl(GPIO(0) + GP_N_EVST), ==, 0x00ffff00);  in test_events_rising_edge()
276     writel(GPIO(0) + GP_N_EVST, 0x0000f000);  in test_events_rising_edge()
277     g_assert_cmphex(readl(GPIO(0) + GP_N_EVST), ==, 0x00ff0f00);  in test_events_rising_edge()
279     writel(GPIO(0) + GP_N_EVST, 0x00ff0f00);  in test_events_rising_edge()
280     g_assert_cmphex(readl(GPIO(0) + GP_N_EVST), ==, 0x00000000);  in test_events_rising_edge()
288     writel(GPIO(0) + GP_N_EVTYP, 0xffffffff);  in test_events_both_edges()
289     writel(GPIO(0) + GP_N_EVBE, 0xffffffff);  in test_events_both_edges()
290     writel(GPIO(0) + GP_N_DOUT, 0xffff0000);  in test_events_both_edges()
291     writel(GPIO(0) + GP_N_OE, 0xffffffff);  in test_events_both_edges()
292     writel(GPIO(0) + GP_N_EVST, 0xffffffff);  in test_events_both_edges()
294     g_assert_cmphex(readl(GPIO(0) + GP_N_EVST), ==, 0x00000000);  in test_events_both_edges()
296     writel(GPIO(0) + GP_N_DOUT, 0xff00ff00);  in test_events_both_edges()
297     g_assert_cmphex(readl(GPIO(0) + GP_N_EVST), ==, 0x00ffff00);  in test_events_both_edges()
299     writel(GPIO(0) + GP_N_DOUT, 0xef00ff08);  in test_events_both_edges()
300     g_assert_cmphex(readl(GPIO(0) + GP_N_EVST), ==, 0x10ffff08);  in test_events_both_edges()
302     writel(GPIO(0) + GP_N_EVST, 0x0000f000);  in test_events_both_edges()
303     g_assert_cmphex(readl(GPIO(0) + GP_N_EVST), ==, 0x10ff0f08);  in test_events_both_edges()
305     writel(GPIO(0) + GP_N_EVST, 0x10ff0f08);  in test_events_both_edges()
306     g_assert_cmphex(readl(GPIO(0) + GP_N_EVST), ==, 0x00000000);  in test_events_both_edges()
316     writel(GPIO(n) + GP_N_EVTYP, 0x00000000);  in test_gpion_irq()
317     writel(GPIO(n) + GP_N_DOUT, 0x00000000);  in test_gpion_irq()
318     writel(GPIO(n) + GP_N_OE, 0xffffffff);  in test_gpion_irq()
319     writel(GPIO(n) + GP_N_EVST, 0xffffffff);  in test_gpion_irq()
320     writel(GPIO(n) + GP_N_EVEN, 0x00000000);  in test_gpion_irq()
323     g_assert_cmphex(readl(GPIO(n) + GP_N_EVST), ==, 0x00000000);  in test_gpion_irq()
325     writel(GPIO(n) + GP_N_DOS, 0x00008000);  in test_gpion_irq()
326     g_assert_cmphex(readl(GPIO(n) + GP_N_EVST), ==, 0x00008000);  in test_gpion_irq()
330     writel(GPIO(n) + GP_N_EVEN, 0xffffffff);  in test_gpion_irq()
334     writel(GPIO(n) + GP_N_DOC, 0x00008000);  in test_gpion_irq()
336     writel(GPIO(n) + GP_N_DOS, 0x00000200);  in test_gpion_irq()
338     writel(GPIO(n) + GP_N_EVST, 0x00008000);  in test_gpion_irq()
342     writel(GPIO(n) + GP_N_EVENC, 0x00000200);  in test_gpion_irq()
344     writel(GPIO(n) + GP_N_EVENS, 0x00000200);  in test_gpion_irq()
348     writel(GPIO(n) + GP_N_DOC, 0x00000200);  in test_gpion_irq()
350     writel(GPIO(n) + GP_N_EVST, 0x00000200);  in test_gpion_irq()
375             g_strdup_printf("/npcm7xx_gpio/gpio[%d]/irq", i);  in main()