Lines Matching +full:bus +full:- +full:addr
4 * Copyright IBM, Corp. 2012-2013
10 * See the COPYING file in the top-level directory.
19 #include "qemu/host-utils.h"
22 void qpci_device_foreach(QPCIBus *bus, int vendor_id, int device_id, in qpci_device_foreach() argument
34 dev = qpci_device_find(bus, QPCI_DEVFN(slot, fn)); in qpci_device_foreach()
39 if (vendor_id != -1 && in qpci_device_foreach()
45 if (device_id != -1 && in qpci_device_foreach()
58 return dev->bus->has_buggy_msi; in qpci_has_buggy_msi()
70 static void qpci_device_set(QPCIDevice *dev, QPCIBus *bus, int devfn) in qpci_device_set() argument
74 dev->bus = bus; in qpci_device_set()
75 dev->devfn = devfn; in qpci_device_set()
78 QPCIDevice *qpci_device_find(QPCIBus *bus, int devfn) in qpci_device_find() argument
83 qpci_device_set(dev, bus, devfn); in qpci_device_find()
93 void qpci_device_init(QPCIDevice *dev, QPCIBus *bus, QPCIAddress *addr) in qpci_device_init() argument
97 qpci_device_set(dev, bus, addr->devfn); in qpci_device_init()
100 g_assert(!addr->vendor_id || vendor_id == addr->vendor_id); in qpci_device_init()
101 g_assert(!addr->device_id || device_id == addr->device_id); in qpci_device_init()
134 static void qpci_secondary_buses_rec(QPCIBus *qbus, int bus, int *pci_bus) in qpci_secondary_buses_rec() argument
142 dev = qpci_device_find(qbus, QPCI_DEVFN(bus + index, 0)); in qpci_secondary_buses_rec()
155 dev = qpci_device_find(qbus, QPCI_DEVFN(bus + index, 0)); in qpci_secondary_buses_rec()
166 if (pribus != bus) { in qpci_secondary_buses_rec()
167 qpci_config_writeb(dev, PCI_PRIMARY_BUS, bus); in qpci_secondary_buses_rec()
191 if (tmp_res_bus != (uint32_t)-1) { in qpci_secondary_buses_rec()
211 int qpci_secondary_buses_init(QPCIBus *bus) in qpci_secondary_buses_init() argument
215 qpci_secondary_buses_rec(bus, 0, &last_bus); in qpci_secondary_buses_init()
225 /* FIXME -- does this need to be a bus callout? */ in qpci_device_enable()
252 uint8_t addr; in qpci_find_capability() local
255 addr = qpci_config_readb(dev, start_addr + PCI_CAP_LIST_NEXT); in qpci_find_capability()
257 addr = qpci_config_readb(dev, PCI_CAPABILITY_LIST); in qpci_find_capability()
261 cap = qpci_config_readb(dev, addr); in qpci_find_capability()
263 addr = qpci_config_readb(dev, addr + PCI_CAP_LIST_NEXT); in qpci_find_capability()
265 } while (cap != id && addr != 0); in qpci_find_capability()
267 return addr; in qpci_find_capability()
272 uint8_t addr; in qpci_msix_enable() local
278 addr = qpci_find_capability(dev, PCI_CAP_ID_MSIX, 0); in qpci_msix_enable()
279 g_assert_cmphex(addr, !=, 0); in qpci_msix_enable()
281 val = qpci_config_readw(dev, addr + PCI_MSIX_FLAGS); in qpci_msix_enable()
282 qpci_config_writew(dev, addr + PCI_MSIX_FLAGS, val | PCI_MSIX_FLAGS_ENABLE); in qpci_msix_enable()
284 table = qpci_config_readl(dev, addr + PCI_MSIX_TABLE); in qpci_msix_enable()
286 dev->msix_table_bar = qpci_iomap(dev, bir_table, NULL); in qpci_msix_enable()
287 dev->msix_table_off = table & ~PCI_MSIX_FLAGS_BIRMASK; in qpci_msix_enable()
289 table = qpci_config_readl(dev, addr + PCI_MSIX_PBA); in qpci_msix_enable()
292 dev->msix_pba_bar = qpci_iomap(dev, bir_pba, NULL); in qpci_msix_enable()
294 dev->msix_pba_bar = dev->msix_table_bar; in qpci_msix_enable()
296 dev->msix_pba_off = table & ~PCI_MSIX_FLAGS_BIRMASK; in qpci_msix_enable()
298 dev->msix_enabled = true; in qpci_msix_enable()
303 uint8_t addr; in qpci_msix_disable() local
306 g_assert(dev->msix_enabled); in qpci_msix_disable()
307 addr = qpci_find_capability(dev, PCI_CAP_ID_MSIX, 0); in qpci_msix_disable()
308 g_assert_cmphex(addr, !=, 0); in qpci_msix_disable()
309 val = qpci_config_readw(dev, addr + PCI_MSIX_FLAGS); in qpci_msix_disable()
310 qpci_config_writew(dev, addr + PCI_MSIX_FLAGS, in qpci_msix_disable()
313 if (dev->msix_pba_bar.addr != dev->msix_table_bar.addr) { in qpci_msix_disable()
314 qpci_iounmap(dev, dev->msix_pba_bar); in qpci_msix_disable()
316 qpci_iounmap(dev, dev->msix_table_bar); in qpci_msix_disable()
318 dev->msix_enabled = 0; in qpci_msix_disable()
319 dev->msix_table_off = 0; in qpci_msix_disable()
320 dev->msix_pba_off = 0; in qpci_msix_disable()
329 g_assert(dev->msix_enabled); in qpci_msix_pending()
330 pba_entry = qpci_io_readl(dev, dev->msix_pba_bar, dev->msix_pba_off + off); in qpci_msix_pending()
331 qpci_io_writel(dev, dev->msix_pba_bar, dev->msix_pba_off + off, in qpci_msix_pending()
338 uint8_t addr; in qpci_msix_masked() local
340 uint64_t vector_off = dev->msix_table_off + entry * PCI_MSIX_ENTRY_SIZE; in qpci_msix_masked()
342 g_assert(dev->msix_enabled); in qpci_msix_masked()
343 addr = qpci_find_capability(dev, PCI_CAP_ID_MSIX, 0); in qpci_msix_masked()
344 g_assert_cmphex(addr, !=, 0); in qpci_msix_masked()
345 val = qpci_config_readw(dev, addr + PCI_MSIX_FLAGS); in qpci_msix_masked()
350 return (qpci_io_readl(dev, dev->msix_table_bar, in qpci_msix_masked()
358 uint8_t addr; in qpci_msix_table_size() local
361 addr = qpci_find_capability(dev, PCI_CAP_ID_MSIX, 0); in qpci_msix_table_size()
362 g_assert_cmphex(addr, !=, 0); in qpci_msix_table_size()
364 control = qpci_config_readw(dev, addr + PCI_MSIX_FLAGS); in qpci_msix_table_size()
370 return dev->bus->config_readb(dev->bus, dev->devfn, offset); in qpci_config_readb()
375 return dev->bus->config_readw(dev->bus, dev->devfn, offset); in qpci_config_readw()
380 return dev->bus->config_readl(dev->bus, dev->devfn, offset); in qpci_config_readl()
386 dev->bus->config_writeb(dev->bus, dev->devfn, offset, value); in qpci_config_writeb()
391 dev->bus->config_writew(dev->bus, dev->devfn, offset, value); in qpci_config_writew()
396 dev->bus->config_writel(dev->bus, dev->devfn, offset, value); in qpci_config_writel()
401 QPCIBus *bus = dev->bus; in qpci_io_readb() local
404 return bus->pio_readb(bus, token.addr + off); in qpci_io_readb()
408 bus->memread(dev->bus, token.addr + off, &val, sizeof(val)); in qpci_io_readb()
415 QPCIBus *bus = dev->bus; in qpci_io_readw() local
418 return bus->pio_readw(bus, token.addr + off); in qpci_io_readw()
422 bus->memread(bus, token.addr + off, &val, sizeof(val)); in qpci_io_readw()
429 QPCIBus *bus = dev->bus; in qpci_io_readl() local
432 return bus->pio_readl(bus, token.addr + off); in qpci_io_readl()
436 bus->memread(dev->bus, token.addr + off, &val, sizeof(val)); in qpci_io_readl()
443 QPCIBus *bus = dev->bus; in qpci_io_readq() local
446 return bus->pio_readq(bus, token.addr + off); in qpci_io_readq()
450 bus->memread(bus, token.addr + off, &val, sizeof(val)); in qpci_io_readq()
458 QPCIBus *bus = dev->bus; in qpci_io_writeb() local
461 bus->pio_writeb(bus, token.addr + off, value); in qpci_io_writeb()
463 bus->memwrite(bus, token.addr + off, &value, sizeof(value)); in qpci_io_writeb()
470 QPCIBus *bus = dev->bus; in qpci_io_writew() local
473 bus->pio_writew(bus, token.addr + off, value); in qpci_io_writew()
476 bus->memwrite(bus, token.addr + off, &value, sizeof(value)); in qpci_io_writew()
483 QPCIBus *bus = dev->bus; in qpci_io_writel() local
486 bus->pio_writel(bus, token.addr + off, value); in qpci_io_writel()
489 bus->memwrite(bus, token.addr + off, &value, sizeof(value)); in qpci_io_writel()
496 QPCIBus *bus = dev->bus; in qpci_io_writeq() local
499 bus->pio_writeq(bus, token.addr + off, value); in qpci_io_writeq()
502 bus->memwrite(bus, token.addr + off, &value, sizeof(value)); in qpci_io_writeq()
510 dev->bus->memread(dev->bus, token.addr + off, buf, len); in qpci_memread()
517 dev->bus->memwrite(dev->bus, token.addr + off, buf, len); in qpci_memwrite()
522 QPCIBus *bus = dev->bus; in qpci_iomap() local
529 uint32_t addr, size; in qpci_iomap() local
537 addr = qpci_config_readl(dev, bar_reg); in qpci_iomap()
539 io_type = addr & PCI_BASE_ADDRESS_SPACE; in qpci_iomap()
541 addr &= PCI_BASE_ADDRESS_IO_MASK; in qpci_iomap()
543 addr &= PCI_BASE_ADDRESS_MEM_MASK; in qpci_iomap()
546 g_assert(addr); /* Must have *some* size bits */ in qpci_iomap()
548 size = 1U << ctz32(addr); in qpci_iomap()
554 loc = QEMU_ALIGN_UP(bus->pio_alloc_ptr, size); in qpci_iomap()
556 g_assert(loc >= bus->pio_alloc_ptr); in qpci_iomap()
557 g_assert(loc + size <= bus->pio_limit); in qpci_iomap()
559 bus->pio_alloc_ptr = loc + size; in qpci_iomap()
564 loc = QEMU_ALIGN_UP(bus->mmio_alloc_ptr, size); in qpci_iomap()
567 g_assert(loc >= bus->mmio_alloc_ptr); in qpci_iomap()
568 g_assert(loc + size <= bus->mmio_limit); in qpci_iomap()
570 bus->mmio_alloc_ptr = loc + size; in qpci_iomap()
576 bar.addr = loc; in qpci_iomap()
585 QPCIBar qpci_legacy_iomap(QPCIDevice *dev, uint16_t addr) in qpci_legacy_iomap() argument
587 QPCIBar bar = { .addr = addr, .is_io = true }; in qpci_legacy_iomap()
591 void add_qpci_address(QOSGraphEdgeOptions *opts, QPCIAddress *addr) in add_qpci_address() argument
593 g_assert(addr); in add_qpci_address()
596 opts->arg = addr; in add_qpci_address()
597 opts->size_arg = sizeof(QPCIAddress); in add_qpci_address()