tests/functional/test_mem_addr_space.py

28         access up to a maximum of 64GiB of memory. Memory hotplug region begins
29         at 4 GiB boundary when "above_4g_mem_size" is 0 (this would be true when
30         we have 0.5 GiB of VM memory, see pc_q35_init()). This means total
31         hotpluggable memory size is 60 GiB. Per slot, we reserve 1 GiB of memory
33         actual memory size of 59 GiB. If the VM is started with 0.5 GiB of
34         memory, maxmem should be set to a maximum value of 59.5 GiB to ensure
55         access up to a maximum of 64GiB of memory. Rest is the same as the case
121         so it can access physical address up to 4 GiB. Setting maxmem to
122         4 GiB should make QEMU fail to start with "phys-bits too low"
124         above 4 GiB due to the PCI hole and simplicity.
141         1024 GiB and ends at 1 TiB - 1. If the max GPA falls in this range,
145         pci64_hole size is 32 GiB. Since TCG_PHYS_ADDR_BITS is defined to
146         be 40, TCG emulated CPUs have maximum of 1 TiB (1024 GiB) of
149         1024 GiB - 4 GiB - 1 GiB per slot for alignment - 32 GiB + 0.5 GiB
150         which is equal to 987.5 GiB. Setting the value to 988 GiB should
166         AMD_HT_START is defined to be at 1012 GiB. So for q35 machines
167         version > 7.0 and AMD cpus, instead of 1024 GiB limit for 40 bit
168         processor address space, it has to be 1012 GiB , that is 12 GiB
170         Make sure QEMU fails when maxmem size is 976 GiB (12 GiB less
171         than 988 GiB).
237         By setting maxram above 1012 GiB  - 32 GiB - 4 GiB = 976 GiB, we can
239         (max GPA will be above AMD_HT_START which is defined as 1012 GiB).
241         With pci_64_hole size at 32 GiB, in this case, maxmem should be 991.5
242         GiB with 1 GiB per slot for alignment and 0.5 GiB as non-hotplug
243         memory for the VM (1024 - 32 - 1 + 0.5). With 992 GiB, QEMU should
261         Same as above but by setting maxram between 976 GiB and 992 Gib,
278         cxl memory window starts after memory device range. Here, we use 1 GiB
279         of cxl window memory. 4G_mem end aligns at 4G. pci64_hole is 32 GiB and
281         So maxmem here should be at most 986 GiB considering all memory boundary