Lines Matching refs:a

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337 /* Since R6 is a potential argument register, choose it last of the
415 /* Condition codes that result from a COMPARE and COMPARE LOGICAL.  */
431 /* Condition codes that result from a LOAD AND TEST.  Here, we have no
543     /* Invert to look for a second transition.  */
553 /* Test if a constant matches the constraint. */
648 /* RRF-a without the m4 field */
655 /* RRF-a with the m4 field */
906 /* load a register with an immediate value */
969 /* Emit a load/store type instruction.  Inputs are:
1412          * The result of a compare has CC=2 for GT and CC=3 unused.
1703      * but do allow a pair of 64-bit operations.
1851 /* We're expecting to use a 20-bit negative offset on the tlb memory ops.  */
1857  * In both cases, return a TCGLabelQemuLdst structure if the slow path
2315             /* Using tcg_out_sh64 here for the format; it is a 32-bit shift.  */
2333         /* ??? Using tcg_out_sh64 here for the format; it is a 32-bit rol.  */
2707             /* Since we can't support "0Z" as a constraint, we allow a1 in
2708                any register.  Fix things up as if a matching constraint.  */
2781      * Recall that the "standard" integer, within a vector, is the
2782      * rightmost element of the leftmost doubleword, a-la VLLEZ.
3156     /* Arithmetic on a wider element size. */
3480      * Facility 45 is a big bin that contains: distinct-operands,
3513     /* The r6 register is technically call-saved, but it's also a parameter
3579      * Return path for goto_ptr. Set return value to 0, a-la exit_tb,
3612 /* We're expecting a 2 byte uleb128 encoded value.  */