Lines Matching +full:0 +full:x70010000
12 OPC_MOVGR2SCR = 0x00000800,
13 OPC_MOVSCR2GR = 0x00000c00,
14 OPC_CLZ_W = 0x00001400,
15 OPC_CTZ_W = 0x00001c00,
16 OPC_CLZ_D = 0x00002400,
17 OPC_CTZ_D = 0x00002c00,
18 OPC_REVB_2H = 0x00003000,
19 OPC_REVB_2W = 0x00003800,
20 OPC_REVB_D = 0x00003c00,
21 OPC_SEXT_H = 0x00005800,
22 OPC_SEXT_B = 0x00005c00,
23 OPC_ADD_W = 0x00100000,
24 OPC_ADD_D = 0x00108000,
25 OPC_SUB_W = 0x00110000,
26 OPC_SUB_D = 0x00118000,
27 OPC_SLT = 0x00120000,
28 OPC_SLTU = 0x00128000,
29 OPC_MASKEQZ = 0x00130000,
30 OPC_MASKNEZ = 0x00138000,
31 OPC_NOR = 0x00140000,
32 OPC_AND = 0x00148000,
33 OPC_OR = 0x00150000,
34 OPC_XOR = 0x00158000,
35 OPC_ORN = 0x00160000,
36 OPC_ANDN = 0x00168000,
37 OPC_SLL_W = 0x00170000,
38 OPC_SRL_W = 0x00178000,
39 OPC_SRA_W = 0x00180000,
40 OPC_SLL_D = 0x00188000,
41 OPC_SRL_D = 0x00190000,
42 OPC_SRA_D = 0x00198000,
43 OPC_ROTR_B = 0x001a0000,
44 OPC_ROTR_H = 0x001a8000,
45 OPC_ROTR_W = 0x001b0000,
46 OPC_ROTR_D = 0x001b8000,
47 OPC_MUL_W = 0x001c0000,
48 OPC_MULH_W = 0x001c8000,
49 OPC_MULH_WU = 0x001d0000,
50 OPC_MUL_D = 0x001d8000,
51 OPC_MULH_D = 0x001e0000,
52 OPC_MULH_DU = 0x001e8000,
53 OPC_DIV_W = 0x00200000,
54 OPC_MOD_W = 0x00208000,
55 OPC_DIV_WU = 0x00210000,
56 OPC_MOD_WU = 0x00218000,
57 OPC_DIV_D = 0x00220000,
58 OPC_MOD_D = 0x00228000,
59 OPC_DIV_DU = 0x00230000,
60 OPC_MOD_DU = 0x00238000,
61 OPC_SLLI_W = 0x00408000,
62 OPC_SLLI_D = 0x00410000,
63 OPC_SRLI_W = 0x00448000,
64 OPC_SRLI_D = 0x00450000,
65 OPC_SRAI_W = 0x00488000,
66 OPC_SRAI_D = 0x00490000,
67 OPC_ROTRI_B = 0x004c2000,
68 OPC_ROTRI_H = 0x004c4000,
69 OPC_ROTRI_W = 0x004c8000,
70 OPC_ROTRI_D = 0x004d0000,
71 OPC_BSTRINS_W = 0x00600000,
72 OPC_BSTRPICK_W = 0x00608000,
73 OPC_BSTRINS_D = 0x00800000,
74 OPC_BSTRPICK_D = 0x00c00000,
75 OPC_FMOV_D = 0x01149800,
76 OPC_MOVGR2FR_D = 0x0114a800,
77 OPC_MOVFR2GR_D = 0x0114b800,
78 OPC_SLTI = 0x02000000,
79 OPC_SLTUI = 0x02400000,
80 OPC_ADDI_W = 0x02800000,
81 OPC_ADDI_D = 0x02c00000,
82 OPC_CU52I_D = 0x03000000,
83 OPC_ANDI = 0x03400000,
84 OPC_ORI = 0x03800000,
85 OPC_XORI = 0x03c00000,
86 OPC_VBITSEL_V = 0x0d100000,
87 OPC_XVBITSEL_V = 0x0d200000,
88 OPC_VSHUF_B = 0x0d500000,
89 OPC_XVSHUF_B = 0x0d600000,
90 OPC_ADDU16I_D = 0x10000000,
91 OPC_LU12I_W = 0x14000000,
92 OPC_CU32I_D = 0x16000000,
93 OPC_PCADDU2I = 0x18000000,
94 OPC_PCALAU12I = 0x1a000000,
95 OPC_PCADDU12I = 0x1c000000,
96 OPC_PCADDU18I = 0x1e000000,
97 OPC_LD_B = 0x28000000,
98 OPC_LD_H = 0x28400000,
99 OPC_LD_W = 0x28800000,
100 OPC_LD_D = 0x28c00000,
101 OPC_ST_B = 0x29000000,
102 OPC_ST_H = 0x29400000,
103 OPC_ST_W = 0x29800000,
104 OPC_ST_D = 0x29c00000,
105 OPC_LD_BU = 0x2a000000,
106 OPC_LD_HU = 0x2a400000,
107 OPC_LD_WU = 0x2a800000,
108 OPC_FLD_S = 0x2b000000,
109 OPC_FST_S = 0x2b400000,
110 OPC_FLD_D = 0x2b800000,
111 OPC_FST_D = 0x2bc00000,
112 OPC_VLD = 0x2c000000,
113 OPC_VST = 0x2c400000,
114 OPC_XVLD = 0x2c800000,
115 OPC_XVST = 0x2cc00000,
116 OPC_VLDREPL_D = 0x30100000,
117 OPC_VLDREPL_W = 0x30200000,
118 OPC_VLDREPL_H = 0x30400000,
119 OPC_VLDREPL_B = 0x30800000,
120 OPC_VSTELM_D = 0x31100000,
121 OPC_VSTELM_W = 0x31200000,
122 OPC_VSTELM_H = 0x31400000,
123 OPC_VSTELM_B = 0x31800000,
124 OPC_XVLDREPL_D = 0x32100000,
125 OPC_XVLDREPL_W = 0x32200000,
126 OPC_XVLDREPL_H = 0x32400000,
127 OPC_XVLDREPL_B = 0x32800000,
128 OPC_XVSTELM_D = 0x33100000,
129 OPC_XVSTELM_W = 0x33200000,
130 OPC_XVSTELM_H = 0x33400000,
131 OPC_XVSTELM_B = 0x33800000,
132 OPC_LDX_B = 0x38000000,
133 OPC_LDX_H = 0x38040000,
134 OPC_LDX_W = 0x38080000,
135 OPC_LDX_D = 0x380c0000,
136 OPC_STX_B = 0x38100000,
137 OPC_STX_H = 0x38140000,
138 OPC_STX_W = 0x38180000,
139 OPC_STX_D = 0x381c0000,
140 OPC_LDX_BU = 0x38200000,
141 OPC_LDX_HU = 0x38240000,
142 OPC_LDX_WU = 0x38280000,
143 OPC_FLDX_S = 0x38300000,
144 OPC_FLDX_D = 0x38340000,
145 OPC_FSTX_S = 0x38380000,
146 OPC_FSTX_D = 0x383c0000,
147 OPC_VLDX = 0x38400000,
148 OPC_VSTX = 0x38440000,
149 OPC_XVLDX = 0x38480000,
150 OPC_XVSTX = 0x384c0000,
151 OPC_DBAR = 0x38720000,
152 OPC_JISCR0 = 0x48000200,
153 OPC_JISCR1 = 0x48000300,
154 OPC_JIRL = 0x4c000000,
155 OPC_B = 0x50000000,
156 OPC_BL = 0x54000000,
157 OPC_BEQ = 0x58000000,
158 OPC_BNE = 0x5c000000,
159 OPC_BGT = 0x60000000,
160 OPC_BLE = 0x64000000,
161 OPC_BGTU = 0x68000000,
162 OPC_BLEU = 0x6c000000,
163 OPC_VSEQ_B = 0x70000000,
164 OPC_VSEQ_H = 0x70008000,
165 OPC_VSEQ_W = 0x70010000,
166 OPC_VSEQ_D = 0x70018000,
167 OPC_VSLE_B = 0x70020000,
168 OPC_VSLE_H = 0x70028000,
169 OPC_VSLE_W = 0x70030000,
170 OPC_VSLE_D = 0x70038000,
171 OPC_VSLE_BU = 0x70040000,
172 OPC_VSLE_HU = 0x70048000,
173 OPC_VSLE_WU = 0x70050000,
174 OPC_VSLE_DU = 0x70058000,
175 OPC_VSLT_B = 0x70060000,
176 OPC_VSLT_H = 0x70068000,
177 OPC_VSLT_W = 0x70070000,
178 OPC_VSLT_D = 0x70078000,
179 OPC_VSLT_BU = 0x70080000,
180 OPC_VSLT_HU = 0x70088000,
181 OPC_VSLT_WU = 0x70090000,
182 OPC_VSLT_DU = 0x70098000,
183 OPC_VADD_B = 0x700a0000,
184 OPC_VADD_H = 0x700a8000,
185 OPC_VADD_W = 0x700b0000,
186 OPC_VADD_D = 0x700b8000,
187 OPC_VSUB_B = 0x700c0000,
188 OPC_VSUB_H = 0x700c8000,
189 OPC_VSUB_W = 0x700d0000,
190 OPC_VSUB_D = 0x700d8000,
191 OPC_VSADD_B = 0x70460000,
192 OPC_VSADD_H = 0x70468000,
193 OPC_VSADD_W = 0x70470000,
194 OPC_VSADD_D = 0x70478000,
195 OPC_VSSUB_B = 0x70480000,
196 OPC_VSSUB_H = 0x70488000,
197 OPC_VSSUB_W = 0x70490000,
198 OPC_VSSUB_D = 0x70498000,
199 OPC_VSADD_BU = 0x704a0000,
200 OPC_VSADD_HU = 0x704a8000,
201 OPC_VSADD_WU = 0x704b0000,
202 OPC_VSADD_DU = 0x704b8000,
203 OPC_VSSUB_BU = 0x704c0000,
204 OPC_VSSUB_HU = 0x704c8000,
205 OPC_VSSUB_WU = 0x704d0000,
206 OPC_VSSUB_DU = 0x704d8000,
207 OPC_VMAX_B = 0x70700000,
208 OPC_VMAX_H = 0x70708000,
209 OPC_VMAX_W = 0x70710000,
210 OPC_VMAX_D = 0x70718000,
211 OPC_VMIN_B = 0x70720000,
212 OPC_VMIN_H = 0x70728000,
213 OPC_VMIN_W = 0x70730000,
214 OPC_VMIN_D = 0x70738000,
215 OPC_VMAX_BU = 0x70740000,
216 OPC_VMAX_HU = 0x70748000,
217 OPC_VMAX_WU = 0x70750000,
218 OPC_VMAX_DU = 0x70758000,
219 OPC_VMIN_BU = 0x70760000,
220 OPC_VMIN_HU = 0x70768000,
221 OPC_VMIN_WU = 0x70770000,
222 OPC_VMIN_DU = 0x70778000,
223 OPC_VMUL_B = 0x70840000,
224 OPC_VMUL_H = 0x70848000,
225 OPC_VMUL_W = 0x70850000,
226 OPC_VMUL_D = 0x70858000,
227 OPC_VSLL_B = 0x70e80000,
228 OPC_VSLL_H = 0x70e88000,
229 OPC_VSLL_W = 0x70e90000,
230 OPC_VSLL_D = 0x70e98000,
231 OPC_VSRL_B = 0x70ea0000,
232 OPC_VSRL_H = 0x70ea8000,
233 OPC_VSRL_W = 0x70eb0000,
234 OPC_VSRL_D = 0x70eb8000,
235 OPC_VSRA_B = 0x70ec0000,
236 OPC_VSRA_H = 0x70ec8000,
237 OPC_VSRA_W = 0x70ed0000,
238 OPC_VSRA_D = 0x70ed8000,
239 OPC_VROTR_B = 0x70ee0000,
240 OPC_VROTR_H = 0x70ee8000,
241 OPC_VROTR_W = 0x70ef0000,
242 OPC_VROTR_D = 0x70ef8000,
243 OPC_VREPLVE_B = 0x71220000,
244 OPC_VREPLVE_H = 0x71228000,
245 OPC_VREPLVE_W = 0x71230000,
246 OPC_VREPLVE_D = 0x71238000,
247 OPC_VAND_V = 0x71260000,
248 OPC_VOR_V = 0x71268000,
249 OPC_VXOR_V = 0x71270000,
250 OPC_VNOR_V = 0x71278000,
251 OPC_VANDN_V = 0x71280000,
252 OPC_VORN_V = 0x71288000,
253 OPC_VSEQI_B = 0x72800000,
254 OPC_VSEQI_H = 0x72808000,
255 OPC_VSEQI_W = 0x72810000,
256 OPC_VSEQI_D = 0x72818000,
257 OPC_VSLEI_B = 0x72820000,
258 OPC_VSLEI_H = 0x72828000,
259 OPC_VSLEI_W = 0x72830000,
260 OPC_VSLEI_D = 0x72838000,
261 OPC_VSLEI_BU = 0x72840000,
262 OPC_VSLEI_HU = 0x72848000,
263 OPC_VSLEI_WU = 0x72850000,
264 OPC_VSLEI_DU = 0x72858000,
265 OPC_VSLTI_B = 0x72860000,
266 OPC_VSLTI_H = 0x72868000,
267 OPC_VSLTI_W = 0x72870000,
268 OPC_VSLTI_D = 0x72878000,
269 OPC_VSLTI_BU = 0x72880000,
270 OPC_VSLTI_HU = 0x72888000,
271 OPC_VSLTI_WU = 0x72890000,
272 OPC_VSLTI_DU = 0x72898000,
273 OPC_VADDI_BU = 0x728a0000,
274 OPC_VADDI_HU = 0x728a8000,
275 OPC_VADDI_WU = 0x728b0000,
276 OPC_VADDI_DU = 0x728b8000,
277 OPC_VSUBI_BU = 0x728c0000,
278 OPC_VSUBI_HU = 0x728c8000,
279 OPC_VSUBI_WU = 0x728d0000,
280 OPC_VSUBI_DU = 0x728d8000,
281 OPC_VMAXI_B = 0x72900000,
282 OPC_VMAXI_H = 0x72908000,
283 OPC_VMAXI_W = 0x72910000,
284 OPC_VMAXI_D = 0x72918000,
285 OPC_VMINI_B = 0x72920000,
286 OPC_VMINI_H = 0x72928000,
287 OPC_VMINI_W = 0x72930000,
288 OPC_VMINI_D = 0x72938000,
289 OPC_VMAXI_BU = 0x72940000,
290 OPC_VMAXI_HU = 0x72948000,
291 OPC_VMAXI_WU = 0x72950000,
292 OPC_VMAXI_DU = 0x72958000,
293 OPC_VMINI_BU = 0x72960000,
294 OPC_VMINI_HU = 0x72968000,
295 OPC_VMINI_WU = 0x72970000,
296 OPC_VMINI_DU = 0x72978000,
297 OPC_VNEG_B = 0x729c3000,
298 OPC_VNEG_H = 0x729c3400,
299 OPC_VNEG_W = 0x729c3800,
300 OPC_VNEG_D = 0x729c3c00,
301 OPC_VREPLGR2VR_B = 0x729f0000,
302 OPC_VREPLGR2VR_H = 0x729f0400,
303 OPC_VREPLGR2VR_W = 0x729f0800,
304 OPC_VREPLGR2VR_D = 0x729f0c00,
305 OPC_VROTRI_B = 0x72a02000,
306 OPC_VROTRI_H = 0x72a04000,
307 OPC_VROTRI_W = 0x72a08000,
308 OPC_VROTRI_D = 0x72a10000,
309 OPC_VINSGR2VR_B = 0x72eb8000,
310 OPC_VINSGR2VR_H = 0x72ebc000,
311 OPC_VINSGR2VR_W = 0x72ebe000,
312 OPC_VINSGR2VR_D = 0x72ebf000,
313 OPC_VPICKVE2GR_B = 0x72ef8000,
314 OPC_VPICKVE2GR_H = 0x72efc000,
315 OPC_VPICKVE2GR_W = 0x72efe000,
316 OPC_VPICKVE2GR_D = 0x72eff000,
317 OPC_VPICKVE2GR_BU = 0x72f38000,
318 OPC_VPICKVE2GR_HU = 0x72f3c000,
319 OPC_VPICKVE2GR_WU = 0x72f3e000,
320 OPC_VPICKVE2GR_DU = 0x72f3f000,
321 OPC_VREPLVEI_B = 0x72f78000,
322 OPC_VREPLVEI_H = 0x72f7c000,
323 OPC_VREPLVEI_W = 0x72f7e000,
324 OPC_VREPLVEI_D = 0x72f7f000,
325 OPC_VBITCLRI_B = 0x73102000,
326 OPC_VBITCLRI_H = 0x73104000,
327 OPC_VBITCLRI_W = 0x73108000,
328 OPC_VBITCLRI_D = 0x73110000,
329 OPC_VBITSETI_B = 0x73142000,
330 OPC_VBITSETI_H = 0x73144000,
331 OPC_VBITSETI_W = 0x73148000,
332 OPC_VBITSETI_D = 0x73150000,
333 OPC_VBITREVI_B = 0x73182000,
334 OPC_VBITREVI_H = 0x73184000,
335 OPC_VBITREVI_W = 0x73188000,
336 OPC_VBITREVI_D = 0x73190000,
337 OPC_VSLLI_B = 0x732c2000,
338 OPC_VSLLI_H = 0x732c4000,
339 OPC_VSLLI_W = 0x732c8000,
340 OPC_VSLLI_D = 0x732d0000,
341 OPC_VSRLI_B = 0x73302000,
342 OPC_VSRLI_H = 0x73304000,
343 OPC_VSRLI_W = 0x73308000,
344 OPC_VSRLI_D = 0x73310000,
345 OPC_VSRAI_B = 0x73342000,
346 OPC_VSRAI_H = 0x73344000,
347 OPC_VSRAI_W = 0x73348000,
348 OPC_VSRAI_D = 0x73350000,
349 OPC_VBITSELI_B = 0x73c40000,
350 OPC_VANDI_B = 0x73d00000,
351 OPC_VORI_B = 0x73d40000,
352 OPC_VXORI_B = 0x73d80000,
353 OPC_VNORI_B = 0x73dc0000,
354 OPC_VLDI = 0x73e00000,
355 OPC_XVSEQ_B = 0x74000000,
356 OPC_XVSEQ_H = 0x74008000,
357 OPC_XVSEQ_W = 0x74010000,
358 OPC_XVSEQ_D = 0x74018000,
359 OPC_XVSLE_B = 0x74020000,
360 OPC_XVSLE_H = 0x74028000,
361 OPC_XVSLE_W = 0x74030000,
362 OPC_XVSLE_D = 0x74038000,
363 OPC_XVSLE_BU = 0x74040000,
364 OPC_XVSLE_HU = 0x74048000,
365 OPC_XVSLE_WU = 0x74050000,
366 OPC_XVSLE_DU = 0x74058000,
367 OPC_XVSLT_B = 0x74060000,
368 OPC_XVSLT_H = 0x74068000,
369 OPC_XVSLT_W = 0x74070000,
370 OPC_XVSLT_D = 0x74078000,
371 OPC_XVSLT_BU = 0x74080000,
372 OPC_XVSLT_HU = 0x74088000,
373 OPC_XVSLT_WU = 0x74090000,
374 OPC_XVSLT_DU = 0x74098000,
375 OPC_XVADD_B = 0x740a0000,
376 OPC_XVADD_H = 0x740a8000,
377 OPC_XVADD_W = 0x740b0000,
378 OPC_XVADD_D = 0x740b8000,
379 OPC_XVSUB_B = 0x740c0000,
380 OPC_XVSUB_H = 0x740c8000,
381 OPC_XVSUB_W = 0x740d0000,
382 OPC_XVSUB_D = 0x740d8000,
383 OPC_XVSADD_B = 0x74460000,
384 OPC_XVSADD_H = 0x74468000,
385 OPC_XVSADD_W = 0x74470000,
386 OPC_XVSADD_D = 0x74478000,
387 OPC_XVSSUB_B = 0x74480000,
388 OPC_XVSSUB_H = 0x74488000,
389 OPC_XVSSUB_W = 0x74490000,
390 OPC_XVSSUB_D = 0x74498000,
391 OPC_XVSADD_BU = 0x744a0000,
392 OPC_XVSADD_HU = 0x744a8000,
393 OPC_XVSADD_WU = 0x744b0000,
394 OPC_XVSADD_DU = 0x744b8000,
395 OPC_XVSSUB_BU = 0x744c0000,
396 OPC_XVSSUB_HU = 0x744c8000,
397 OPC_XVSSUB_WU = 0x744d0000,
398 OPC_XVSSUB_DU = 0x744d8000,
399 OPC_XVMAX_B = 0x74700000,
400 OPC_XVMAX_H = 0x74708000,
401 OPC_XVMAX_W = 0x74710000,
402 OPC_XVMAX_D = 0x74718000,
403 OPC_XVMIN_B = 0x74720000,
404 OPC_XVMIN_H = 0x74728000,
405 OPC_XVMIN_W = 0x74730000,
406 OPC_XVMIN_D = 0x74738000,
407 OPC_XVMAX_BU = 0x74740000,
408 OPC_XVMAX_HU = 0x74748000,
409 OPC_XVMAX_WU = 0x74750000,
410 OPC_XVMAX_DU = 0x74758000,
411 OPC_XVMIN_BU = 0x74760000,
412 OPC_XVMIN_HU = 0x74768000,
413 OPC_XVMIN_WU = 0x74770000,
414 OPC_XVMIN_DU = 0x74778000,
415 OPC_XVMUL_B = 0x74840000,
416 OPC_XVMUL_H = 0x74848000,
417 OPC_XVMUL_W = 0x74850000,
418 OPC_XVMUL_D = 0x74858000,
419 OPC_XVSLL_B = 0x74e80000,
420 OPC_XVSLL_H = 0x74e88000,
421 OPC_XVSLL_W = 0x74e90000,
422 OPC_XVSLL_D = 0x74e98000,
423 OPC_XVSRL_B = 0x74ea0000,
424 OPC_XVSRL_H = 0x74ea8000,
425 OPC_XVSRL_W = 0x74eb0000,
426 OPC_XVSRL_D = 0x74eb8000,
427 OPC_XVSRA_B = 0x74ec0000,
428 OPC_XVSRA_H = 0x74ec8000,
429 OPC_XVSRA_W = 0x74ed0000,
430 OPC_XVSRA_D = 0x74ed8000,
431 OPC_XVROTR_B = 0x74ee0000,
432 OPC_XVROTR_H = 0x74ee8000,
433 OPC_XVROTR_W = 0x74ef0000,
434 OPC_XVROTR_D = 0x74ef8000,
435 OPC_XVREPLVE_B = 0x75220000,
436 OPC_XVREPLVE_H = 0x75228000,
437 OPC_XVREPLVE_W = 0x75230000,
438 OPC_XVREPLVE_D = 0x75238000,
439 OPC_XVAND_V = 0x75260000,
440 OPC_XVOR_V = 0x75268000,
441 OPC_XVXOR_V = 0x75270000,
442 OPC_XVNOR_V = 0x75278000,
443 OPC_XVANDN_V = 0x75280000,
444 OPC_XVORN_V = 0x75288000,
445 OPC_XVSEQI_B = 0x76800000,
446 OPC_XVSEQI_H = 0x76808000,
447 OPC_XVSEQI_W = 0x76810000,
448 OPC_XVSEQI_D = 0x76818000,
449 OPC_XVSLEI_B = 0x76820000,
450 OPC_XVSLEI_H = 0x76828000,
451 OPC_XVSLEI_W = 0x76830000,
452 OPC_XVSLEI_D = 0x76838000,
453 OPC_XVSLEI_BU = 0x76840000,
454 OPC_XVSLEI_HU = 0x76848000,
455 OPC_XVSLEI_WU = 0x76850000,
456 OPC_XVSLEI_DU = 0x76858000,
457 OPC_XVSLTI_B = 0x76860000,
458 OPC_XVSLTI_H = 0x76868000,
459 OPC_XVSLTI_W = 0x76870000,
460 OPC_XVSLTI_D = 0x76878000,
461 OPC_XVSLTI_BU = 0x76880000,
462 OPC_XVSLTI_HU = 0x76888000,
463 OPC_XVSLTI_WU = 0x76890000,
464 OPC_XVSLTI_DU = 0x76898000,
465 OPC_XVADDI_BU = 0x768a0000,
466 OPC_XVADDI_HU = 0x768a8000,
467 OPC_XVADDI_WU = 0x768b0000,
468 OPC_XVADDI_DU = 0x768b8000,
469 OPC_XVSUBI_BU = 0x768c0000,
470 OPC_XVSUBI_HU = 0x768c8000,
471 OPC_XVSUBI_WU = 0x768d0000,
472 OPC_XVSUBI_DU = 0x768d8000,
473 OPC_XVMAXI_B = 0x76900000,
474 OPC_XVMAXI_H = 0x76908000,
475 OPC_XVMAXI_W = 0x76910000,
476 OPC_XVMAXI_D = 0x76918000,
477 OPC_XVMINI_B = 0x76920000,
478 OPC_XVMINI_H = 0x76928000,
479 OPC_XVMINI_W = 0x76930000,
480 OPC_XVMINI_D = 0x76938000,
481 OPC_XVMAXI_BU = 0x76940000,
482 OPC_XVMAXI_HU = 0x76948000,
483 OPC_XVMAXI_WU = 0x76950000,
484 OPC_XVMAXI_DU = 0x76958000,
485 OPC_XVMINI_BU = 0x76960000,
486 OPC_XVMINI_HU = 0x76968000,
487 OPC_XVMINI_WU = 0x76970000,
488 OPC_XVMINI_DU = 0x76978000,
489 OPC_XVNEG_B = 0x769c3000,
490 OPC_XVNEG_H = 0x769c3400,
491 OPC_XVNEG_W = 0x769c3800,
492 OPC_XVNEG_D = 0x769c3c00,
493 OPC_XVREPLGR2VR_B = 0x769f0000,
494 OPC_XVREPLGR2VR_H = 0x769f0400,
495 OPC_XVREPLGR2VR_W = 0x769f0800,
496 OPC_XVREPLGR2VR_D = 0x769f0c00,
497 OPC_XVROTRI_B = 0x76a02000,
498 OPC_XVROTRI_H = 0x76a04000,
499 OPC_XVROTRI_W = 0x76a08000,
500 OPC_XVROTRI_D = 0x76a10000,
501 OPC_XVINSGR2VR_W = 0x76ebc000,
502 OPC_XVINSGR2VR_D = 0x76ebe000,
503 OPC_XVPICKVE2GR_W = 0x76efc000,
504 OPC_XVPICKVE2GR_D = 0x76efe000,
505 OPC_XVPICKVE2GR_WU = 0x76f3c000,
506 OPC_XVPICKVE2GR_DU = 0x76f3e000,
507 OPC_XVREPL128VEI_B = 0x76f78000,
508 OPC_XVREPL128VEI_H = 0x76f7c000,
509 OPC_XVREPL128VEI_W = 0x76f7e000,
510 OPC_XVREPL128VEI_D = 0x76f7f000,
511 OPC_XVREPLVE0_B = 0x77070000,
512 OPC_XVREPLVE0_H = 0x77078000,
513 OPC_XVREPLVE0_W = 0x7707c000,
514 OPC_XVREPLVE0_D = 0x7707e000,
515 OPC_XVREPLVE0_Q = 0x7707f000,
516 OPC_XVBITCLRI_B = 0x77102000,
517 OPC_XVBITCLRI_H = 0x77104000,
518 OPC_XVBITCLRI_W = 0x77108000,
519 OPC_XVBITCLRI_D = 0x77110000,
520 OPC_XVBITSETI_B = 0x77142000,
521 OPC_XVBITSETI_H = 0x77144000,
522 OPC_XVBITSETI_W = 0x77148000,
523 OPC_XVBITSETI_D = 0x77150000,
524 OPC_XVBITREVI_B = 0x77182000,
525 OPC_XVBITREVI_H = 0x77184000,
526 OPC_XVBITREVI_W = 0x77188000,
527 OPC_XVBITREVI_D = 0x77190000,
528 OPC_XVSLLI_B = 0x772c2000,
529 OPC_XVSLLI_H = 0x772c4000,
530 OPC_XVSLLI_W = 0x772c8000,
531 OPC_XVSLLI_D = 0x772d0000,
532 OPC_XVSRLI_B = 0x77302000,
533 OPC_XVSRLI_H = 0x77304000,
534 OPC_XVSRLI_W = 0x77308000,
535 OPC_XVSRLI_D = 0x77310000,
536 OPC_XVSRAI_B = 0x77342000,
537 OPC_XVSRAI_H = 0x77344000,
538 OPC_XVSRAI_W = 0x77348000,
539 OPC_XVSRAI_D = 0x77350000,
540 OPC_XVBITSELI_B = 0x77c40000,
541 OPC_XVANDI_B = 0x77d00000,
542 OPC_XVORI_B = 0x77d40000,
543 OPC_XVXORI_B = 0x77d80000,
544 OPC_XVNORI_B = 0x77dc0000,
545 OPC_XVLDI = 0x77e00000,
596 tcg_debug_assert(d >= 0 && d <= 0x1f);
597 tcg_debug_assert(fj >= 0x20 && fj <= 0x3f);
598 return encode_dj_slots(opc, d, fj & 0x1f);
604 tcg_debug_assert(d >= 0 && d <= 0x1f);
605 tcg_debug_assert(j >= 0 && j <= 0x1f);
612 tcg_debug_assert(d >= 0 && d <= 0x1f);
613 tcg_debug_assert(j >= 0 && j <= 0x1f);
614 tcg_debug_assert(k >= 0 && k <= 0x1f);
621 tcg_debug_assert(d >= 0 && d <= 0x1f);
622 tcg_debug_assert(j >= 0 && j <= 0x1f);
623 tcg_debug_assert(sk12 >= -0x800 && sk12 <= 0x7ff);
624 return encode_djk_slots(opc, d, j, sk12 & 0xfff);
630 tcg_debug_assert(d >= 0 && d <= 0x1f);
631 tcg_debug_assert(j >= 0 && j <= 0x1f);
632 tcg_debug_assert(sk16 >= -0x8000 && sk16 <= 0x7fff);
633 return encode_djk_slots(opc, d, j, sk16 & 0xffff);
639 tcg_debug_assert(d >= 0 && d <= 0x1f);
640 tcg_debug_assert(j >= 0 && j <= 0x1f);
641 tcg_debug_assert(uk12 <= 0xfff);
648 tcg_debug_assert(d >= 0 && d <= 0x1f);
649 tcg_debug_assert(j >= 0 && j <= 0x1f);
650 tcg_debug_assert(uk3 <= 0x7);
657 tcg_debug_assert(d >= 0 && d <= 0x1f);
658 tcg_debug_assert(j >= 0 && j <= 0x1f);
659 tcg_debug_assert(uk4 <= 0xf);
666 tcg_debug_assert(d >= 0 && d <= 0x1f);
667 tcg_debug_assert(j >= 0 && j <= 0x1f);
668 tcg_debug_assert(uk5 <= 0x1f);
676 tcg_debug_assert(d >= 0 && d <= 0x1f);
677 tcg_debug_assert(j >= 0 && j <= 0x1f);
678 tcg_debug_assert(uk5 <= 0x1f);
679 tcg_debug_assert(um5 <= 0x1f);
686 tcg_debug_assert(d >= 0 && d <= 0x1f);
687 tcg_debug_assert(j >= 0 && j <= 0x1f);
688 tcg_debug_assert(uk6 <= 0x3f);
696 tcg_debug_assert(d >= 0 && d <= 0x1f);
697 tcg_debug_assert(j >= 0 && j <= 0x1f);
698 tcg_debug_assert(uk6 <= 0x3f);
699 tcg_debug_assert(um6 <= 0x3f);
706 tcg_debug_assert(d >= 0 && d <= 0x1f);
707 tcg_debug_assert(sj20 >= -0x80000 && sj20 <= 0x7ffff);
708 return encode_dj_slots(opc, d, sj20 & 0xfffff);
714 tcg_debug_assert(d >= 0 && d <= 0x1f);
715 tcg_debug_assert(tj >= 0 && tj <= 0x3);
722 tcg_debug_assert(d >= 0 && d <= 0x1f);
723 tcg_debug_assert(vj >= 0x20 && vj <= 0x3f);
724 tcg_debug_assert(uk1 <= 0x1);
725 return encode_djk_slots(opc, d, vj & 0x1f, uk1);
731 tcg_debug_assert(d >= 0 && d <= 0x1f);
732 tcg_debug_assert(vj >= 0x20 && vj <= 0x3f);
733 tcg_debug_assert(uk2 <= 0x3);
734 return encode_djk_slots(opc, d, vj & 0x1f, uk2);
740 tcg_debug_assert(d >= 0 && d <= 0x1f);
741 tcg_debug_assert(vj >= 0x20 && vj <= 0x3f);
742 tcg_debug_assert(uk3 <= 0x7);
743 return encode_djk_slots(opc, d, vj & 0x1f, uk3);
749 tcg_debug_assert(d >= 0 && d <= 0x1f);
750 tcg_debug_assert(vj >= 0x20 && vj <= 0x3f);
751 tcg_debug_assert(uk4 <= 0xf);
752 return encode_djk_slots(opc, d, vj & 0x1f, uk4);
758 tcg_debug_assert(d >= 0 && d <= 0x1f);
759 tcg_debug_assert(xj >= 0x20 && xj <= 0x3f);
760 tcg_debug_assert(uk2 <= 0x3);
761 return encode_djk_slots(opc, d, xj & 0x1f, uk2);
767 tcg_debug_assert(d >= 0 && d <= 0x1f);
768 tcg_debug_assert(xj >= 0x20 && xj <= 0x3f);
769 tcg_debug_assert(uk3 <= 0x7);
770 return encode_djk_slots(opc, d, xj & 0x1f, uk3);
776 tcg_debug_assert(fd >= 0x20 && fd <= 0x3f);
777 tcg_debug_assert(fj >= 0x20 && fj <= 0x3f);
778 return encode_dj_slots(opc, fd & 0x1f, fj & 0x1f);
784 tcg_debug_assert(fd >= 0x20 && fd <= 0x3f);
785 tcg_debug_assert(j >= 0 && j <= 0x1f);
786 return encode_dj_slots(opc, fd & 0x1f, j);
792 tcg_debug_assert(fd >= 0x20 && fd <= 0x3f);
793 tcg_debug_assert(j >= 0 && j <= 0x1f);
794 tcg_debug_assert(k >= 0 && k <= 0x1f);
795 return encode_djk_slots(opc, fd & 0x1f, j, k);
801 tcg_debug_assert(fd >= 0x20 && fd <= 0x3f);
802 tcg_debug_assert(j >= 0 && j <= 0x1f);
803 tcg_debug_assert(sk12 >= -0x800 && sk12 <= 0x7ff);
804 return encode_djk_slots(opc, fd & 0x1f, j, sk12 & 0xfff);
810 tcg_debug_assert(sd10k16 >= -0x2000000 && sd10k16 <= 0x1ffffff);
811 return encode_dk_slots(opc, (sd10k16 >> 16) & 0x3ff, sd10k16 & 0xffff);
817 tcg_debug_assert(sd5k16 >= -0x100000 && sd5k16 <= 0xfffff);
818 return encode_dk_slots(opc, (sd5k16 >> 16) & 0x1f, sd5k16 & 0xffff);
824 tcg_debug_assert(td >= 0 && td <= 0x3);
825 tcg_debug_assert(j >= 0 && j <= 0x1f);
832 tcg_debug_assert(ud15 <= 0x7fff);
839 tcg_debug_assert(vd >= 0x20 && vd <= 0x3f);
840 tcg_debug_assert(j >= 0 && j <= 0x1f);
841 return encode_dj_slots(opc, vd & 0x1f, j);
847 tcg_debug_assert(vd >= 0x20 && vd <= 0x3f);
848 tcg_debug_assert(j >= 0 && j <= 0x1f);
849 tcg_debug_assert(k >= 0 && k <= 0x1f);
850 return encode_djk_slots(opc, vd & 0x1f, j, k);
856 tcg_debug_assert(vd >= 0x20 && vd <= 0x3f);
857 tcg_debug_assert(j >= 0 && j <= 0x1f);
858 tcg_debug_assert(sk10 >= -0x200 && sk10 <= 0x1ff);
859 return encode_djk_slots(opc, vd & 0x1f, j, sk10 & 0x3ff);
865 tcg_debug_assert(vd >= 0x20 && vd <= 0x3f);
866 tcg_debug_assert(j >= 0 && j <= 0x1f);
867 tcg_debug_assert(sk11 >= -0x400 && sk11 <= 0x3ff);
868 return encode_djk_slots(opc, vd & 0x1f, j, sk11 & 0x7ff);
874 tcg_debug_assert(vd >= 0x20 && vd <= 0x3f);
875 tcg_debug_assert(j >= 0 && j <= 0x1f);
876 tcg_debug_assert(sk12 >= -0x800 && sk12 <= 0x7ff);
877 return encode_djk_slots(opc, vd & 0x1f, j, sk12 & 0xfff);
884 tcg_debug_assert(vd >= 0x20 && vd <= 0x3f);
885 tcg_debug_assert(j >= 0 && j <= 0x1f);
886 tcg_debug_assert(sk8 >= -0x80 && sk8 <= 0x7f);
887 tcg_debug_assert(un1 <= 0x1);
888 return encode_djkn_slots(opc, vd & 0x1f, j, sk8 & 0xff, un1);
895 tcg_debug_assert(vd >= 0x20 && vd <= 0x3f);
896 tcg_debug_assert(j >= 0 && j <= 0x1f);
897 tcg_debug_assert(sk8 >= -0x80 && sk8 <= 0x7f);
898 tcg_debug_assert(un2 <= 0x3);
899 return encode_djkn_slots(opc, vd & 0x1f, j, sk8 & 0xff, un2);
906 tcg_debug_assert(vd >= 0x20 && vd <= 0x3f);
907 tcg_debug_assert(j >= 0 && j <= 0x1f);
908 tcg_debug_assert(sk8 >= -0x80 && sk8 <= 0x7f);
909 tcg_debug_assert(un3 <= 0x7);
910 return encode_djkn_slots(opc, vd & 0x1f, j, sk8 & 0xff, un3);
917 tcg_debug_assert(vd >= 0x20 && vd <= 0x3f);
918 tcg_debug_assert(j >= 0 && j <= 0x1f);
919 tcg_debug_assert(sk8 >= -0x80 && sk8 <= 0x7f);
920 tcg_debug_assert(un4 <= 0xf);
921 return encode_djkn_slots(opc, vd & 0x1f, j, sk8 & 0xff, un4);
927 tcg_debug_assert(vd >= 0x20 && vd <= 0x3f);
928 tcg_debug_assert(j >= 0 && j <= 0x1f);
929 tcg_debug_assert(sk9 >= -0x100 && sk9 <= 0xff);
930 return encode_djk_slots(opc, vd & 0x1f, j, sk9 & 0x1ff);
936 tcg_debug_assert(vd >= 0x20 && vd <= 0x3f);
937 tcg_debug_assert(j >= 0 && j <= 0x1f);
938 tcg_debug_assert(uk1 <= 0x1);
939 return encode_djk_slots(opc, vd & 0x1f, j, uk1);
945 tcg_debug_assert(vd >= 0x20 && vd <= 0x3f);
946 tcg_debug_assert(j >= 0 && j <= 0x1f);
947 tcg_debug_assert(uk2 <= 0x3);
948 return encode_djk_slots(opc, vd & 0x1f, j, uk2);
954 tcg_debug_assert(vd >= 0x20 && vd <= 0x3f);
955 tcg_debug_assert(j >= 0 && j <= 0x1f);
956 tcg_debug_assert(uk3 <= 0x7);
957 return encode_djk_slots(opc, vd & 0x1f, j, uk3);
963 tcg_debug_assert(vd >= 0x20 && vd <= 0x3f);
964 tcg_debug_assert(j >= 0 && j <= 0x1f);
965 tcg_debug_assert(uk4 <= 0xf);
966 return encode_djk_slots(opc, vd & 0x1f, j, uk4);
972 tcg_debug_assert(vd >= 0x20 && vd <= 0x3f);
973 tcg_debug_assert(sj13 >= -0x1000 && sj13 <= 0xfff);
974 return encode_dj_slots(opc, vd & 0x1f, sj13 & 0x1fff);
980 tcg_debug_assert(vd >= 0x20 && vd <= 0x3f);
981 tcg_debug_assert(vj >= 0x20 && vj <= 0x3f);
982 return encode_dj_slots(opc, vd & 0x1f, vj & 0x1f);
988 tcg_debug_assert(vd >= 0x20 && vd <= 0x3f);
989 tcg_debug_assert(vj >= 0x20 && vj <= 0x3f);
990 tcg_debug_assert(k >= 0 && k <= 0x1f);
991 return encode_djk_slots(opc, vd & 0x1f, vj & 0x1f, k);
997 tcg_debug_assert(vd >= 0x20 && vd <= 0x3f);
998 tcg_debug_assert(vj >= 0x20 && vj <= 0x3f);
999 tcg_debug_assert(sk5 >= -0x10 && sk5 <= 0xf);
1000 return encode_djk_slots(opc, vd & 0x1f, vj & 0x1f, sk5 & 0x1f);
1006 tcg_debug_assert(vd >= 0x20 && vd <= 0x3f);
1007 tcg_debug_assert(vj >= 0x20 && vj <= 0x3f);
1008 tcg_debug_assert(uk1 <= 0x1);
1009 return encode_djk_slots(opc, vd & 0x1f, vj & 0x1f, uk1);
1015 tcg_debug_assert(vd >= 0x20 && vd <= 0x3f);
1016 tcg_debug_assert(vj >= 0x20 && vj <= 0x3f);
1017 tcg_debug_assert(uk2 <= 0x3);
1018 return encode_djk_slots(opc, vd & 0x1f, vj & 0x1f, uk2);
1024 tcg_debug_assert(vd >= 0x20 && vd <= 0x3f);
1025 tcg_debug_assert(vj >= 0x20 && vj <= 0x3f);
1026 tcg_debug_assert(uk3 <= 0x7);
1027 return encode_djk_slots(opc, vd & 0x1f, vj & 0x1f, uk3);
1033 tcg_debug_assert(vd >= 0x20 && vd <= 0x3f);
1034 tcg_debug_assert(vj >= 0x20 && vj <= 0x3f);
1035 tcg_debug_assert(uk4 <= 0xf);
1036 return encode_djk_slots(opc, vd & 0x1f, vj & 0x1f, uk4);
1042 tcg_debug_assert(vd >= 0x20 && vd <= 0x3f);
1043 tcg_debug_assert(vj >= 0x20 && vj <= 0x3f);
1044 tcg_debug_assert(uk5 <= 0x1f);
1045 return encode_djk_slots(opc, vd & 0x1f, vj & 0x1f, uk5);
1051 tcg_debug_assert(vd >= 0x20 && vd <= 0x3f);
1052 tcg_debug_assert(vj >= 0x20 && vj <= 0x3f);
1053 tcg_debug_assert(uk6 <= 0x3f);
1054 return encode_djk_slots(opc, vd & 0x1f, vj & 0x1f, uk6);
1060 tcg_debug_assert(vd >= 0x20 && vd <= 0x3f);
1061 tcg_debug_assert(vj >= 0x20 && vj <= 0x3f);
1062 tcg_debug_assert(uk8 <= 0xff);
1063 return encode_djk_slots(opc, vd & 0x1f, vj & 0x1f, uk8);
1069 tcg_debug_assert(vd >= 0x20 && vd <= 0x3f);
1070 tcg_debug_assert(vj >= 0x20 && vj <= 0x3f);
1071 tcg_debug_assert(vk >= 0x20 && vk <= 0x3f);
1072 return encode_djk_slots(opc, vd & 0x1f, vj & 0x1f, vk & 0x1f);
1079 tcg_debug_assert(vd >= 0x20 && vd <= 0x3f);
1080 tcg_debug_assert(vj >= 0x20 && vj <= 0x3f);
1081 tcg_debug_assert(vk >= 0x20 && vk <= 0x3f);
1082 tcg_debug_assert(va >= 0x20 && va <= 0x3f);
1083 return encode_djka_slots(opc, vd & 0x1f, vj & 0x1f, vk & 0x1f, va & 0x1f);
1089 tcg_debug_assert(xd >= 0x20 && xd <= 0x3f);
1090 tcg_debug_assert(j >= 0 && j <= 0x1f);
1091 return encode_dj_slots(opc, xd & 0x1f, j);
1097 tcg_debug_assert(xd >= 0x20 && xd <= 0x3f);
1098 tcg_debug_assert(j >= 0 && j <= 0x1f);
1099 tcg_debug_assert(k >= 0 && k <= 0x1f);
1100 return encode_djk_slots(opc, xd & 0x1f, j, k);
1106 tcg_debug_assert(xd >= 0x20 && xd <= 0x3f);
1107 tcg_debug_assert(j >= 0 && j <= 0x1f);
1108 tcg_debug_assert(sk10 >= -0x200 && sk10 <= 0x1ff);
1109 return encode_djk_slots(opc, xd & 0x1f, j, sk10 & 0x3ff);
1115 tcg_debug_assert(xd >= 0x20 && xd <= 0x3f);
1116 tcg_debug_assert(j >= 0 && j <= 0x1f);
1117 tcg_debug_assert(sk11 >= -0x400 && sk11 <= 0x3ff);
1118 return encode_djk_slots(opc, xd & 0x1f, j, sk11 & 0x7ff);
1124 tcg_debug_assert(xd >= 0x20 && xd <= 0x3f);
1125 tcg_debug_assert(j >= 0 && j <= 0x1f);
1126 tcg_debug_assert(sk12 >= -0x800 && sk12 <= 0x7ff);
1127 return encode_djk_slots(opc, xd & 0x1f, j, sk12 & 0xfff);
1134 tcg_debug_assert(xd >= 0x20 && xd <= 0x3f);
1135 tcg_debug_assert(j >= 0 && j <= 0x1f);
1136 tcg_debug_assert(sk8 >= -0x80 && sk8 <= 0x7f);
1137 tcg_debug_assert(un2 <= 0x3);
1138 return encode_djkn_slots(opc, xd & 0x1f, j, sk8 & 0xff, un2);
1145 tcg_debug_assert(xd >= 0x20 && xd <= 0x3f);
1146 tcg_debug_assert(j >= 0 && j <= 0x1f);
1147 tcg_debug_assert(sk8 >= -0x80 && sk8 <= 0x7f);
1148 tcg_debug_assert(un3 <= 0x7);
1149 return encode_djkn_slots(opc, xd & 0x1f, j, sk8 & 0xff, un3);
1156 tcg_debug_assert(xd >= 0x20 && xd <= 0x3f);
1157 tcg_debug_assert(j >= 0 && j <= 0x1f);
1158 tcg_debug_assert(sk8 >= -0x80 && sk8 <= 0x7f);
1159 tcg_debug_assert(un4 <= 0xf);
1160 return encode_djkn_slots(opc, xd & 0x1f, j, sk8 & 0xff, un4);
1167 tcg_debug_assert(xd >= 0x20 && xd <= 0x3f);
1168 tcg_debug_assert(j >= 0 && j <= 0x1f);
1169 tcg_debug_assert(sk8 >= -0x80 && sk8 <= 0x7f);
1170 tcg_debug_assert(un5 <= 0x1f);
1171 return encode_djkn_slots(opc, xd & 0x1f, j, sk8 & 0xff, un5);
1177 tcg_debug_assert(xd >= 0x20 && xd <= 0x3f);
1178 tcg_debug_assert(j >= 0 && j <= 0x1f);
1179 tcg_debug_assert(sk9 >= -0x100 && sk9 <= 0xff);
1180 return encode_djk_slots(opc, xd & 0x1f, j, sk9 & 0x1ff);
1186 tcg_debug_assert(xd >= 0x20 && xd <= 0x3f);
1187 tcg_debug_assert(j >= 0 && j <= 0x1f);
1188 tcg_debug_assert(uk2 <= 0x3);
1189 return encode_djk_slots(opc, xd & 0x1f, j, uk2);
1195 tcg_debug_assert(xd >= 0x20 && xd <= 0x3f);
1196 tcg_debug_assert(j >= 0 && j <= 0x1f);
1197 tcg_debug_assert(uk3 <= 0x7);
1198 return encode_djk_slots(opc, xd & 0x1f, j, uk3);
1204 tcg_debug_assert(xd >= 0x20 && xd <= 0x3f);
1205 tcg_debug_assert(sj13 >= -0x1000 && sj13 <= 0xfff);
1206 return encode_dj_slots(opc, xd & 0x1f, sj13 & 0x1fff);
1212 tcg_debug_assert(xd >= 0x20 && xd <= 0x3f);
1213 tcg_debug_assert(xj >= 0x20 && xj <= 0x3f);
1214 return encode_dj_slots(opc, xd & 0x1f, xj & 0x1f);
1220 tcg_debug_assert(xd >= 0x20 && xd <= 0x3f);
1221 tcg_debug_assert(xj >= 0x20 && xj <= 0x3f);
1222 tcg_debug_assert(k >= 0 && k <= 0x1f);
1223 return encode_djk_slots(opc, xd & 0x1f, xj & 0x1f, k);
1229 tcg_debug_assert(xd >= 0x20 && xd <= 0x3f);
1230 tcg_debug_assert(xj >= 0x20 && xj <= 0x3f);
1231 tcg_debug_assert(sk5 >= -0x10 && sk5 <= 0xf);
1232 return encode_djk_slots(opc, xd & 0x1f, xj & 0x1f, sk5 & 0x1f);
1238 tcg_debug_assert(xd >= 0x20 && xd <= 0x3f);
1239 tcg_debug_assert(xj >= 0x20 && xj <= 0x3f);
1240 tcg_debug_assert(uk1 <= 0x1);
1241 return encode_djk_slots(opc, xd & 0x1f, xj & 0x1f, uk1);
1247 tcg_debug_assert(xd >= 0x20 && xd <= 0x3f);
1248 tcg_debug_assert(xj >= 0x20 && xj <= 0x3f);
1249 tcg_debug_assert(uk2 <= 0x3);
1250 return encode_djk_slots(opc, xd & 0x1f, xj & 0x1f, uk2);
1256 tcg_debug_assert(xd >= 0x20 && xd <= 0x3f);
1257 tcg_debug_assert(xj >= 0x20 && xj <= 0x3f);
1258 tcg_debug_assert(uk3 <= 0x7);
1259 return encode_djk_slots(opc, xd & 0x1f, xj & 0x1f, uk3);
1265 tcg_debug_assert(xd >= 0x20 && xd <= 0x3f);
1266 tcg_debug_assert(xj >= 0x20 && xj <= 0x3f);
1267 tcg_debug_assert(uk4 <= 0xf);
1268 return encode_djk_slots(opc, xd & 0x1f, xj & 0x1f, uk4);
1274 tcg_debug_assert(xd >= 0x20 && xd <= 0x3f);
1275 tcg_debug_assert(xj >= 0x20 && xj <= 0x3f);
1276 tcg_debug_assert(uk5 <= 0x1f);
1277 return encode_djk_slots(opc, xd & 0x1f, xj & 0x1f, uk5);
1283 tcg_debug_assert(xd >= 0x20 && xd <= 0x3f);
1284 tcg_debug_assert(xj >= 0x20 && xj <= 0x3f);
1285 tcg_debug_assert(uk6 <= 0x3f);
1286 return encode_djk_slots(opc, xd & 0x1f, xj & 0x1f, uk6);
1292 tcg_debug_assert(xd >= 0x20 && xd <= 0x3f);
1293 tcg_debug_assert(xj >= 0x20 && xj <= 0x3f);
1294 tcg_debug_assert(uk8 <= 0xff);
1295 return encode_djk_slots(opc, xd & 0x1f, xj & 0x1f, uk8);
1301 tcg_debug_assert(xd >= 0x20 && xd <= 0x3f);
1302 tcg_debug_assert(xj >= 0x20 && xj <= 0x3f);
1303 tcg_debug_assert(xk >= 0x20 && xk <= 0x3f);
1304 return encode_djk_slots(opc, xd & 0x1f, xj & 0x1f, xk & 0x1f);
1311 tcg_debug_assert(xd >= 0x20 && xd <= 0x3f);
1312 tcg_debug_assert(xj >= 0x20 && xj <= 0x3f);
1313 tcg_debug_assert(xk >= 0x20 && xk <= 0x3f);
1314 tcg_debug_assert(xa >= 0x20 && xa <= 0x3f);
1315 return encode_djka_slots(opc, xd & 0x1f, xj & 0x1f, xk & 0x1f, xa & 0x1f);