Lines Matching +full:0 +full:x28400000
20 QEMU_BUILD_BUG_ON(TCG_TYPE_I32 != 0 || TCG_TYPE_I64 != 1);
71 tcg_debug_assert(slot >= 0 && slot <= 1);
87 if (offset == sextract64(offset, 0, 26)) {
90 *src_rw = deposit32(*src_rw, 0, 26, offset);
101 if (offset == sextract64(offset, 0, 19)) {
113 if (offset == sextract64(offset, 0, 14)) {
123 tcg_debug_assert(addend == 0);
137 #define TCG_CT_CONST_AIMM 0x100
138 #define TCG_CT_CONST_LIMM 0x200
139 #define TCG_CT_CONST_ZERO 0x400
140 #define TCG_CT_CONST_MONE 0x800
141 #define TCG_CT_CONST_ORRI 0x1000
142 #define TCG_CT_CONST_ANDI 0x2000
143 #define TCG_CT_CONST_CMP 0x4000
145 #define ALL_GENERAL_REGS 0xffffffffu
146 #define ALL_VECTOR_REGS 0xffffffff00000000ull
151 return (val & ~0xfff) == 0 || (val & ~0xfff000) == 0;
160 0....01....1
161 0..01..10..0
165 if ((int64_t)val < 0) {
168 if (val == 0) {
172 return (val & (val - 1)) == 0;
178 if (v16 == (v16 & 0xff)) {
179 *cmode = 0x8;
180 *imm8 = v16 & 0xff;
182 } else if (v16 == (v16 & 0xff00)) {
183 *cmode = 0xa;
193 if (v32 == (v32 & 0xff)) {
194 *cmode = 0x0;
195 *imm8 = v32 & 0xff;
197 } else if (v32 == (v32 & 0xff00)) {
198 *cmode = 0x2;
199 *imm8 = (v32 >> 8) & 0xff;
201 } else if (v32 == (v32 & 0xff0000)) {
202 *cmode = 0x4;
203 *imm8 = (v32 >> 16) & 0xff;
205 } else if (v32 == (v32 & 0xff000000)) {
206 *cmode = 0x6;
216 if ((v32 & 0xffff00ff) == 0xff) {
217 *cmode = 0xc;
218 *imm8 = (v32 >> 8) & 0xff;
220 } else if ((v32 & 0xff00ffff) == 0xffff) {
221 *cmode = 0xd;
222 *imm8 = (v32 >> 16) & 0xff;
231 if (extract32(v32, 0, 19) == 0
232 && (extract32(v32, 25, 6) == 0x20
233 || extract32(v32, 25, 6) == 0x1f)) {
234 *cmode = 0xf;
246 if (extract64(v64, 0, 48) == 0
247 && (extract64(v64, 54, 9) == 0x100
248 || extract64(v64, 54, 9) == 0x0ff)) {
249 *cmode = 0xf;
267 for (i = 6; i > 0; i -= 2) {
269 uint32_t tmp = v32 & ~(0xffu << (i * 4));
312 if ((ct & TCG_CT_CONST_ZERO) && val == 0) {
320 case 0:
336 return 0;
340 COND_EQ = 0x0,
341 COND_NE = 0x1,
342 COND_CS = 0x2, /* Unsigned greater or equal */
344 COND_CC = 0x3, /* Unsigned less than */
346 COND_MI = 0x4, /* Negative */
347 COND_PL = 0x5, /* Zero or greater */
348 COND_VS = 0x6, /* Overflow */
349 COND_VC = 0x7, /* No overflow */
350 COND_HI = 0x8, /* Unsigned greater than */
351 COND_LS = 0x9, /* Unsigned less or equal */
352 COND_GE = 0xa,
353 COND_LT = 0xb,
354 COND_GT = 0xc,
355 COND_LE = 0xd,
356 COND_AL = 0xe,
357 COND_NV = 0xf, /* behaves like COND_AL here */
378 LDST_ST = 0, /* store */
391 I3201_CBZ = 0x34000000,
392 I3201_CBNZ = 0x35000000,
395 I3202_B_C = 0x54000000,
398 I3205_TBZ = 0x36000000,
399 I3205_TBNZ = 0x37000000,
402 I3206_B = 0x14000000,
403 I3206_BL = 0x94000000,
406 I3207_BR = 0xd61f0000,
407 I3207_BLR = 0xd63f0000,
408 I3207_RET = 0xd65f0000,
411 I3303_LD1R = 0x0d40c000,
414 I3305_LDR = 0x58000000,
415 I3305_LDR_v64 = 0x5c000000,
416 I3305_LDR_v128 = 0x9c000000,
419 I3306_LDXP = 0xc8600000,
420 I3306_STXP = 0xc8200000,
424 I3312_STRB = 0x38000000 | LDST_ST << 22 | MO_8 << 30,
425 I3312_STRH = 0x38000000 | LDST_ST << 22 | MO_16 << 30,
426 I3312_STRW = 0x38000000 | LDST_ST << 22 | MO_32 << 30,
427 I3312_STRX = 0x38000000 | LDST_ST << 22 | MO_64 << 30,
429 I3312_LDRB = 0x38000000 | LDST_LD << 22 | MO_8 << 30,
430 I3312_LDRH = 0x38000000 | LDST_LD << 22 | MO_16 << 30,
431 I3312_LDRW = 0x38000000 | LDST_LD << 22 | MO_32 << 30,
432 I3312_LDRX = 0x38000000 | LDST_LD << 22 | MO_64 << 30,
434 I3312_LDRSBW = 0x38000000 | LDST_LD_S_W << 22 | MO_8 << 30,
435 I3312_LDRSHW = 0x38000000 | LDST_LD_S_W << 22 | MO_16 << 30,
437 I3312_LDRSBX = 0x38000000 | LDST_LD_S_X << 22 | MO_8 << 30,
438 I3312_LDRSHX = 0x38000000 | LDST_LD_S_X << 22 | MO_16 << 30,
439 I3312_LDRSWX = 0x38000000 | LDST_LD_S_X << 22 | MO_32 << 30,
441 I3312_LDRVS = 0x3c000000 | LDST_LD << 22 | MO_32 << 30,
442 I3312_STRVS = 0x3c000000 | LDST_ST << 22 | MO_32 << 30,
444 I3312_LDRVD = 0x3c000000 | LDST_LD << 22 | MO_64 << 30,
445 I3312_STRVD = 0x3c000000 | LDST_ST << 22 | MO_64 << 30,
447 I3312_LDRVQ = 0x3c000000 | 3 << 22 | 0 << 30,
448 I3312_STRVQ = 0x3c000000 | 2 << 22 | 0 << 30,
450 I3312_TO_I3310 = 0x00200800,
451 I3312_TO_I3313 = 0x01000000,
454 I3314_LDP = 0x28400000,
455 I3314_STP = 0x28000000,
458 I3401_ADDI = 0x11000000,
459 I3401_ADDSI = 0x31000000,
460 I3401_SUBI = 0x51000000,
461 I3401_SUBSI = 0x71000000,
464 I3402_BFM = 0x33000000,
465 I3402_SBFM = 0x13000000,
466 I3402_UBFM = 0x53000000,
469 I3403_EXTR = 0x13800000,
472 I3404_ANDI = 0x12000000,
473 I3404_ORRI = 0x32000000,
474 I3404_EORI = 0x52000000,
475 I3404_ANDSI = 0x72000000,
478 I3405_MOVN = 0x12800000,
479 I3405_MOVZ = 0x52800000,
480 I3405_MOVK = 0x72800000,
483 I3406_ADR = 0x10000000,
484 I3406_ADRP = 0x90000000,
487 I3501_ADD = 0x0b200000,
490 I3502_ADD = 0x0b000000,
491 I3502_ADDS = 0x2b000000,
492 I3502_SUB = 0x4b000000,
493 I3502_SUBS = 0x6b000000,
499 I3503_ADC = 0x1a000000,
500 I3503_SBC = 0x5a000000,
503 I3506_CSEL = 0x1a800000,
504 I3506_CSINC = 0x1a800400,
505 I3506_CSINV = 0x5a800000,
506 I3506_CSNEG = 0x5a800400,
509 I3507_CLZ = 0x5ac01000,
510 I3507_RBIT = 0x5ac00000,
511 I3507_REV = 0x5ac00000, /* + size << 10 */
514 I3508_LSLV = 0x1ac02000,
515 I3508_LSRV = 0x1ac02400,
516 I3508_ASRV = 0x1ac02800,
517 I3508_RORV = 0x1ac02c00,
518 I3508_SMULH = 0x9b407c00,
519 I3508_UMULH = 0x9bc07c00,
520 I3508_UDIV = 0x1ac00800,
521 I3508_SDIV = 0x1ac00c00,
524 I3509_MADD = 0x1b000000,
525 I3509_MSUB = 0x1b008000,
528 I3510_AND = 0x0a000000,
529 I3510_BIC = 0x0a200000,
530 I3510_ORR = 0x2a000000,
531 I3510_ORN = 0x2a200000,
532 I3510_EOR = 0x4a000000,
533 I3510_EON = 0x4a200000,
534 I3510_ANDS = 0x6a000000,
540 I3605_DUP = 0x0e000400,
541 I3605_INS = 0x4e001c00,
542 I3605_UMOV = 0x0e003c00,
545 I3606_MOVI = 0x0f000400,
546 I3606_MVNI = 0x2f000400,
547 I3606_BIC = 0x2f001400,
548 I3606_ORR = 0x0f001400,
551 I3609_SSHR = 0x5f000400,
552 I3609_SSRA = 0x5f001400,
553 I3609_SHL = 0x5f005400,
554 I3609_USHR = 0x7f000400,
555 I3609_USRA = 0x7f001400,
556 I3609_SLI = 0x7f005400,
559 I3611_SQADD = 0x5e200c00,
560 I3611_SQSUB = 0x5e202c00,
561 I3611_CMGT = 0x5e203400,
562 I3611_CMGE = 0x5e203c00,
563 I3611_SSHL = 0x5e204400,
564 I3611_ADD = 0x5e208400,
565 I3611_CMTST = 0x5e208c00,
566 I3611_UQADD = 0x7e200c00,
567 I3611_UQSUB = 0x7e202c00,
568 I3611_CMHI = 0x7e203400,
569 I3611_CMHS = 0x7e203c00,
570 I3611_USHL = 0x7e204400,
571 I3611_SUB = 0x7e208400,
572 I3611_CMEQ = 0x7e208c00,
575 I3612_CMGT0 = 0x5e208800,
576 I3612_CMEQ0 = 0x5e209800,
577 I3612_CMLT0 = 0x5e20a800,
578 I3612_ABS = 0x5e20b800,
579 I3612_CMGE0 = 0x7e208800,
580 I3612_CMLE0 = 0x7e209800,
581 I3612_NEG = 0x7e20b800,
584 I3614_SSHR = 0x0f000400,
585 I3614_SSRA = 0x0f001400,
586 I3614_SHL = 0x0f005400,
587 I3614_SLI = 0x2f005400,
588 I3614_USHR = 0x2f000400,
589 I3614_USRA = 0x2f001400,
592 I3616_ADD = 0x0e208400,
593 I3616_AND = 0x0e201c00,
594 I3616_BIC = 0x0e601c00,
595 I3616_BIF = 0x2ee01c00,
596 I3616_BIT = 0x2ea01c00,
597 I3616_BSL = 0x2e601c00,
598 I3616_EOR = 0x2e201c00,
599 I3616_MUL = 0x0e209c00,
600 I3616_ORR = 0x0ea01c00,
601 I3616_ORN = 0x0ee01c00,
602 I3616_SUB = 0x2e208400,
603 I3616_CMGT = 0x0e203400,
604 I3616_CMGE = 0x0e203c00,
605 I3616_CMTST = 0x0e208c00,
606 I3616_CMHI = 0x2e203400,
607 I3616_CMHS = 0x2e203c00,
608 I3616_CMEQ = 0x2e208c00,
609 I3616_SMAX = 0x0e206400,
610 I3616_SMIN = 0x0e206c00,
611 I3616_SSHL = 0x0e204400,
612 I3616_SQADD = 0x0e200c00,
613 I3616_SQSUB = 0x0e202c00,
614 I3616_UMAX = 0x2e206400,
615 I3616_UMIN = 0x2e206c00,
616 I3616_UQADD = 0x2e200c00,
617 I3616_UQSUB = 0x2e202c00,
618 I3616_USHL = 0x2e204400,
621 I3617_CMGT0 = 0x0e208800,
622 I3617_CMEQ0 = 0x0e209800,
623 I3617_CMLT0 = 0x0e20a800,
624 I3617_CMGE0 = 0x2e208800,
625 I3617_CMLE0 = 0x2e209800,
626 I3617_NOT = 0x2e205800,
627 I3617_ABS = 0x0e20b800,
628 I3617_NEG = 0x2e20b800,
631 NOP = 0xd503201f,
632 DMB_ISH = 0xd50338bf,
633 DMB_LD = 0x00000100,
634 DMB_ST = 0x00000200,
636 BTI_C = 0xd503245f,
637 BTI_J = 0xd503249f,
638 BTI_JC = 0xd50324df,
654 tcg_out32(s, insn | (rt & 0x1f) | (rn << 5) | (size << 10) | (q << 30));
660 tcg_out32(s, insn | (imm19 & 0x7ffff) << 5 | rt);
672 tcg_out32(s, insn | ext << 31 | (imm19 & 0x7ffff) << 5 | rt);
678 tcg_out32(s, insn | tcg_cond_to_aarch64[c] | (imm19 & 0x7ffff) << 5);
684 insn |= (imm6 & 0x20) << (31 - 5);
685 insn |= (imm6 & 0x1f) << 19;
686 tcg_out32(s, insn | (imm14 & 0x3fff) << 5 | rt);
691 tcg_out32(s, insn | (imm26 & 0x03ffffff));
707 tcg_debug_assert(ofs >= -0x200 && ofs < 0x200 && (ofs & 7) == 0);
708 insn |= (ofs & (0x7f << 3)) << (15 - 3);
716 if (aimm > 0xfff) {
717 tcg_debug_assert((aimm & 0xfff) == 0);
719 tcg_debug_assert(aimm <= 0xfff);
749 tcg_debug_assert((shift & ~0x30) == 0);
756 tcg_out32(s, insn | (disp & 3) << 29 | (disp & 0x1ffffc) << (5 - 2) | rd);
815 | (rd & 0x1f) | (~rn & 0x20) << 6 | (rn & 0x1f) << 5);
821 tcg_out32(s, insn | q << 30 | op << 29 | cmode << 12 | (rd & 0x1f)
822 | (imm8 & 0xe0) << (16 - 5) | (imm8 & 0x1f) << 5);
828 tcg_out32(s, insn | immhb << 16 | (rn & 0x1f) << 5 | (rd & 0x1f));
834 tcg_out32(s, insn | (size << 22) | (rm & 0x1f) << 16
835 | (rn & 0x1f) << 5 | (rd & 0x1f));
841 tcg_out32(s, insn | (size << 22) | (rn & 0x1f) << 5 | (rd & 0x1f));
848 | (rn & 0x1f) << 5 | (rd & 0x1f));
854 tcg_out32(s, insn | q << 30 | (size << 22) | (rm & 0x1f) << 16
855 | (rn & 0x1f) << 5 | (rd & 0x1f));
862 | (rn & 0x1f) << 5 | (rd & 0x1f));
871 0x4000 | ext << 13 | base << 5 | (rd & 0x1f));
877 tcg_out32(s, insn | (offset & 0x1ff) << 12 | rn << 5 | (rd & 0x1f));
885 | rn << 5 | (rd & 0x1f));
908 tcg_out_insn(s, 3401, ADDI, ext, rd, rn, 0);
923 if (l == 0) {
924 r = 0; /* form 0....01....1 */
926 if (h == 0) {
931 r = 64 - l; /* form 1....10....0 or 0..01..10..0 */
951 tcg_out_insn(s, 3606, MOVI, q, rd, 0, 0xe, imm8);
956 * Test all bytes 0x00 or 0xff second. This can match cases that
959 for (i = imm8 = 0; i < 8; i++) {
961 if (byte == 0xff) {
963 } else if (byte != 0) {
967 tcg_out_insn(s, 3606, MOVI, q, rd, 1, 0xe, imm8);
980 tcg_out_insn(s, 3606, MOVI, q, rd, 0, cmode, imm8);
984 tcg_out_insn(s, 3606, MVNI, q, rd, 0, cmode, imm8);
990 * rd = v16 & 0xff, rd |= v16 & 0xff00.
992 tcg_out_insn(s, 3606, MOVI, q, rd, 0, 0x8, v16 & 0xff);
993 tcg_out_insn(s, 3606, ORR, q, rd, 0, 0xa, v16 >> 8);
1002 tcg_out_insn(s, 3606, MOVI, q, rd, 0, cmode, imm8);
1007 tcg_out_insn(s, 3606, MVNI, q, rd, 0, cmode, imm8);
1017 tcg_out_insn(s, 3606, MOVI, q, rd, 0, cmode, imm8);
1018 tcg_out_insn(s, 3606, ORR, q, rd, 0, i, extract32(v32, i * 4, 8));
1023 tcg_out_insn(s, 3606, MVNI, q, rd, 0, cmode, imm8);
1024 tcg_out_insn(s, 3606, BIC, q, rd, 0, i, extract32(n32, i * 4, 8));
1037 new_pool_l2(s, R_AARCH64_CONDBR19, s->code_ptr, 0, v64, v64);
1038 tcg_out_insn(s, 3305, LDR_v128, 0, rd);
1040 new_pool_label(s, v64, R_AARCH64_CONDBR19, s->code_ptr, 0);
1041 tcg_out_insn(s, 3305, LDR_v64, 0, rd);
1049 tcg_out_insn(s, 3605, DUP, is_q, rd, rs, 1 << vece, 0);
1058 if (offset < -0xffffff || offset > 0xffffff) {
1065 if (offset < 0) {
1069 if (offset & 0xfff000) {
1070 tcg_out_insn_3401(s, add_insn, 1, temp, base, offset & 0xfff000);
1073 if (offset & 0xfff) {
1074 tcg_out_insn_3401(s, add_insn, 1, temp, base, offset & 0xfff);
1103 the high 32 bits are cleared by setting SF=0. */
1104 if (type == TCG_TYPE_I32 || (value & ~0xffffffffull) == 0) {
1113 if ((value & ~0xffffull) == 0) {
1114 tcg_out_insn(s, 3405, MOVZ, type, rd, value, 0);
1116 } else if ((ivalue & ~0xffffull) == 0) {
1117 tcg_out_insn(s, 3405, MOVN, type, rd, ivalue, 0);
1123 as 0xff0000ff with the same 64-bit logic matching 0xffffffffff0000ff. */
1134 if (disp == sextract64(disp, 0, 21)) {
1139 if (disp == sextract64(disp, 0, 21)) {
1141 if (value & 0xfff) {
1142 tcg_out_insn(s, 3401, ADDI, type, rd, rd, value & 0xfff);
1157 t1 = t0 & ~(0xffffull << s0);
1159 t2 = t1 & ~(0xffffull << s1);
1160 if (t2 == 0) {
1162 if (t1 != 0) {
1169 new_pool_label(s, value, R_AARCH64_CONDBR19, s->code_ptr, 0);
1170 tcg_out_insn(s, 3305, LDR, 0, rd);
1193 if (offset >= 0 && !(offset & ((1 << lgsize) - 1))) {
1195 if (scaled_uimm <= 0xfff) {
1224 tcg_out_insn(s, 3605, UMOV, type, ret, arg, 0, 0);
1227 tcg_out_insn(s, 3605, INS, 0, ret, arg, 4 << type, 0);
1234 tcg_out_insn(s, 3616, ORR, 0, 0, ret, arg, arg);
1238 tcg_out_insn(s, 3616, ORR, 1, 0, ret, arg, arg);
1308 if (type <= TCG_TYPE_I64 && val == 0) {
1396 } else if (b >= 0) {
1409 tcg_debug_assert(offset == sextract64(offset, 0, 26));
1416 if (offset == sextract64(offset, 0, 26)) {
1433 tcg_out_reloc(s, s->code_ptr, R_AARCH64_JUMP26, l, 0);
1434 tcg_out_insn(s, 3206, B, 0);
1449 /* cmp xN,0; b.ne L -> cbnz xN,L */
1450 if (b_const && b == 0) {
1456 /* cmp xN,0; b.mi L -> tbnz xN,63,L */
1457 if (b_const && b == 0) {
1465 /* tst xN,0xffffffff; b.ne L -> cbnz wN,L */
1484 tcg_out_reloc(s, s->code_ptr, R_AARCH64_CONDBR19, l, 0);
1485 tcg_out_insn(s, 3202, B_C, c, 0);
1489 if (tbit >= 0) {
1490 tcg_out_reloc(s, s->code_ptr, R_AARCH64_TSTBR14, l, 0);
1493 tcg_out_insn(s, 3205, TBZ, a, tbit, 0);
1496 tcg_out_insn(s, 3205, TBNZ, a, tbit, 0);
1502 tcg_out_reloc(s, s->code_ptr, R_AARCH64_CONDBR19, l, 0);
1505 tcg_out_insn(s, 3201, CBZ, ext, a, 0);
1508 tcg_out_insn(s, 3201, CBNZ, ext, a, 0);
1526 /* Using ALIASes SXTB, SXTH, SXTW, of SBFM Xd, Xn, #0, #7|15|31 */
1528 tcg_out_sbfm(s, ext, rd, rn, 0, bits);
1554 /* Using ALIASes UXTB, UXTH of UBFM Wd, Wn, #0, #7|15 */
1556 tcg_out_ubfm(s, 0, rd, rn, 0, bits);
1587 if (aimm >= 0) {
1607 if (bl < 0) {
1617 possibility of adding 0+const in the low part, and the
1621 tcg_out_movi(s, ext, al, 0);
1630 /* Note that the only two constants we support are 0 and -1, and
1631 that SBC = rn + ~rm + c, so adc -1 is sbc 0, and vice-versa. */
1632 if ((bh != 0) ^ sub) {
1647 [0 ... TCG_MO_ALL] = DMB_ISH | DMB_LD | DMB_ST,
1669 tcg_out_cmp(s, ext, TCG_COND_NE, a0, 0, 1);
1676 } else if (b == 0) {
1707 if (!reloc_pc19(lb->label_ptr[0], tcg_splitwx_to_rx(s->code_ptr))) {
1722 if (!reloc_pc19(lb->label_ptr[0], tcg_splitwx_to_rx(s->code_ptr))) {
1773 QEMU_BUILD_BUG_ON(offsetof(CPUTLBDescFast, mask) != 0);
1776 tlb_mask_table_ofs(s, mem_index), 1, 0);
1814 tcg_out_cmp(s, addr_type, TCG_COND_NE, TCG_REG_TMP0, TCG_REG_TMP2, 0);
1817 ldst->label_ptr[0] = s->code_ptr;
1818 tcg_out_insn(s, 3202, B_C, TCG_COND_NE, 0);
1832 tcg_out_logicali(s, I3404_ANDSI, 0, TCG_REG_XZR, addr_reg, a_mask);
1835 ldst->label_ptr[0] = s->code_ptr;
1836 tcg_out_insn(s, 3202, B_C, TCG_COND_NE, 0);
1956 h.base, h.index, MO_32, 0);
1979 tcg_out_logicali(s, I3404_ANDSI, 0, TCG_REG_XZR, addr_reg, 15);
1981 tcg_out_insn(s, 3202, B_C, TCG_COND_NE, 0);
2015 tcg_out_insn(s, 3201, CBNZ, 0, TCG_REG_TMP0, -2);
2026 tcg_out_insn(s, 3314, LDP, datalo, datahi, base, 0, 1, 0);
2028 tcg_out_insn(s, 3314, STP, datalo, datahi, base, 0, 1, 0);
2048 if (a0 == 0) {
2056 if (offset == sextract64(offset, 0, 26)) {
2077 tcg_debug_assert(i_off == sextract64(i_off, 0, 21));
2094 if (d_offset == sextract64(d_offset, 0, 28)) {
2095 insn = deposit32(I3206_B, 0, 26, d_offset >> 2);
2113 TCGType ext = (tcg_op_defs[opc].flags & TCG_OPF_64BIT) != 0;
2116 TCGArg a0 = args[0];
2122 the zero register. These need not actually test args[I] == 0. */
2136 tcg_out_ldst(s, I3312_LDRB, a0, a1, a2, 0);
2139 tcg_out_ldst(s, I3312_LDRSBW, a0, a1, a2, 0);
2142 tcg_out_ldst(s, I3312_LDRSBX, a0, a1, a2, 0);
2167 tcg_out_ldst(s, I3312_STRB, REG0(0), a1, a2, 0);
2171 tcg_out_ldst(s, I3312_STRH, REG0(0), a1, a2, 1);
2175 tcg_out_ldst(s, I3312_STRW, REG0(0), a1, a2, 2);
2178 tcg_out_ldst(s, I3312_STRX, REG0(0), a1, a2, 3);
2345 tcg_out_insn(s, 3502, SUB, 0, TCG_REG_TMP0, TCG_REG_XZR, a2);
2404 tcg_out_qemu_st(s, REG0(0), a1, a2, ext);
2412 tcg_out_qemu_ldst_i128(s, REG0(0), REG0(1), a2, args[3], false);
2554 a0 = args[0];
2603 tcg_out_insn(s, 3606, BIC, is_q, a0, 0, cmode, imm8);
2606 tcg_out_insn(s, 3606, MVNI, is_q, a0, 0, cmode, imm8);
2609 tcg_out_insn(s, 3616, AND, is_q, 0, a0, a1, a2);
2615 tcg_out_insn(s, 3606, ORR, is_q, a0, 0, cmode, imm8);
2618 tcg_out_insn(s, 3606, MOVI, is_q, a0, 0, cmode, imm8);
2621 tcg_out_insn(s, 3616, ORR, is_q, 0, a0, a1, a2);
2627 tcg_out_insn(s, 3606, BIC, is_q, a0, 0, cmode, imm8);
2630 tcg_out_insn(s, 3606, MOVI, is_q, a0, 0, cmode, imm8);
2633 tcg_out_insn(s, 3616, BIC, is_q, 0, a0, a1, a2);
2639 tcg_out_insn(s, 3606, ORR, is_q, a0, 0, cmode, imm8);
2642 tcg_out_insn(s, 3606, MVNI, is_q, a0, 0, cmode, imm8);
2645 tcg_out_insn(s, 3616, ORN, is_q, 0, a0, a1, a2);
2648 tcg_out_insn(s, 3616, EOR, is_q, 0, a0, a1, a2);
2691 tcg_out_insn(s, 3617, NOT, is_q, 0, a0, a1);
2754 tcg_out_insn(s, 3617, NOT, is_q, 0, a0, a0);
2761 /* (x & 0) == 0 */
2772 tcg_out_insn(s, 3617, NOT, is_q, 0, a0, a0);
2791 tcg_out_dupi_vec(s, type, MO_8, TCG_VEC_TMP0, 0);
2796 if (insn == 0) {
2801 tcg_debug_assert(insn != 0);
2806 if (insn == 0) {
2811 tcg_debug_assert(insn != 0);
2823 tcg_out_insn(s, 3616, BIT, is_q, 0, a0, a2, a1);
2825 tcg_out_insn(s, 3616, BIF, is_q, 0, a0, a3, a1);
2830 tcg_out_insn(s, 3616, BSL, is_q, 0, a0, a2, a3);
2879 return 0;
3093 return C_O1_I2(r, 0, rZ);
3147 return C_O1_I2(w, 0, w);
3156 tcg_target_available_regs[TCG_TYPE_I32] = 0xffffffffu;
3157 tcg_target_available_regs[TCG_TYPE_I64] = 0xffffffffu;
3158 tcg_target_available_regs[TCG_TYPE_V64] = 0xffffffff00000000ull;
3159 tcg_target_available_regs[TCG_TYPE_V128] = 0xffffffff00000000ull;
3182 s->reserved_regs = 0;
3206 QEMU_BUILD_BUG_ON(FRAME_SIZE - PUSH_SIZE > 0xfff);
3224 tcg_out_insn(s, 3314, STP, r, r + 1, TCG_REG_SP, ofs, 1, 0);
3246 tcg_out_mov(s, TCG_TYPE_PTR, TCG_AREG0, tcg_target_call_iarg_regs[0]);
3250 * Return path for goto_ptr. Set return value to 0, a-la exit_tb,
3255 tcg_out_movi(s, TCG_TYPE_REG, TCG_REG_X0, 0);
3268 tcg_out_insn(s, 3314, LDP, r, r + 1, TCG_REG_SP, ofs, 1, 0);
3273 TCG_REG_SP, PUSH_SIZE, 0, 1);
3285 for (i = 0; i < count; ++i) {
3303 .h.cie.data_align = 0x78, /* sleb128 -8 */
3311 (FRAME_SIZE & 0x7f) | 0x80, /* ... uleb128 FRAME_SIZE */
3315 0x80 + 28, 1, /* DW_CFA_offset, x28, -8 */
3316 0x80 + 27, 2, /* DW_CFA_offset, x27, -16 */
3317 0x80 + 26, 3, /* DW_CFA_offset, x26, -24 */
3318 0x80 + 25, 4, /* DW_CFA_offset, x25, -32 */
3319 0x80 + 24, 5, /* DW_CFA_offset, x24, -40 */
3320 0x80 + 23, 6, /* DW_CFA_offset, x23, -48 */
3321 0x80 + 22, 7, /* DW_CFA_offset, x22, -56 */
3322 0x80 + 21, 8, /* DW_CFA_offset, x21, -64 */
3323 0x80 + 20, 9, /* DW_CFA_offset, x20, -72 */
3324 0x80 + 19, 10, /* DW_CFA_offset, x1p, -80 */
3325 0x80 + 30, 11, /* DW_CFA_offset, lr, -88 */
3326 0x80 + 29, 12, /* DW_CFA_offset, fp, -96 */