Lines Matching full:dc
278 static inline bool option_enabled(DisasContext *dc, int opt) in option_enabled() argument
280 return xtensa_option_enabled(dc->config, opt); in option_enabled()
283 static void init_sar_tracker(DisasContext *dc) in init_sar_tracker() argument
285 dc->sar_5bit = false; in init_sar_tracker()
286 dc->sar_m32_5bit = false; in init_sar_tracker()
287 dc->sar_m32 = NULL; in init_sar_tracker()
290 static void gen_right_shift_sar(DisasContext *dc, TCGv_i32 sa) in gen_right_shift_sar() argument
293 if (dc->sar_m32_5bit) { in gen_right_shift_sar()
294 tcg_gen_discard_i32(dc->sar_m32); in gen_right_shift_sar()
296 dc->sar_5bit = true; in gen_right_shift_sar()
297 dc->sar_m32_5bit = false; in gen_right_shift_sar()
300 static void gen_left_shift_sar(DisasContext *dc, TCGv_i32 sa) in gen_left_shift_sar() argument
302 if (!dc->sar_m32) { in gen_left_shift_sar()
303 dc->sar_m32 = tcg_temp_new_i32(); in gen_left_shift_sar()
305 tcg_gen_andi_i32(dc->sar_m32, sa, 0x1f); in gen_left_shift_sar()
306 tcg_gen_sub_i32(cpu_SR[SAR], tcg_constant_i32(32), dc->sar_m32); in gen_left_shift_sar()
307 dc->sar_5bit = false; in gen_left_shift_sar()
308 dc->sar_m32_5bit = true; in gen_left_shift_sar()
311 static void gen_exception(DisasContext *dc, int excp) in gen_exception() argument
316 static void gen_exception_cause(DisasContext *dc, uint32_t cause) in gen_exception_cause() argument
318 TCGv_i32 pc = tcg_constant_i32(dc->pc); in gen_exception_cause()
322 dc->base.is_jmp = DISAS_NORETURN; in gen_exception_cause()
326 static void gen_debug_exception(DisasContext *dc, uint32_t cause) in gen_debug_exception() argument
328 TCGv_i32 pc = tcg_constant_i32(dc->pc); in gen_debug_exception()
331 dc->base.is_jmp = DISAS_NORETURN; in gen_debug_exception()
335 static bool gen_check_privilege(DisasContext *dc) in gen_check_privilege() argument
338 if (!dc->cring) { in gen_check_privilege()
342 gen_exception_cause(dc, PRIVILEGED_CAUSE); in gen_check_privilege()
343 dc->base.is_jmp = DISAS_NORETURN; in gen_check_privilege()
347 static bool gen_check_cpenable(DisasContext *dc, uint32_t cp_mask) in gen_check_cpenable() argument
349 cp_mask &= ~dc->cpenable; in gen_check_cpenable()
351 if (option_enabled(dc, XTENSA_OPTION_COPROCESSOR) && cp_mask) { in gen_check_cpenable()
352 gen_exception_cause(dc, COPROCESSOR0_DISABLED + ctz32(cp_mask)); in gen_check_cpenable()
353 dc->base.is_jmp = DISAS_NORETURN; in gen_check_cpenable()
359 static int gen_postprocess(DisasContext *dc, int slot);
361 static void gen_jump_slot(DisasContext *dc, TCGv dest, int slot) in gen_jump_slot() argument
364 if (dc->icount) { in gen_jump_slot()
365 tcg_gen_mov_i32(cpu_SR[ICOUNT], dc->next_icount); in gen_jump_slot()
367 if (dc->op_flags & XTENSA_OP_POSTPROCESS) { in gen_jump_slot()
368 slot = gen_postprocess(dc, slot); in gen_jump_slot()
372 tcg_gen_exit_tb(dc->base.tb, slot); in gen_jump_slot()
376 dc->base.is_jmp = DISAS_NORETURN; in gen_jump_slot()
379 static void gen_jump(DisasContext *dc, TCGv dest) in gen_jump() argument
381 gen_jump_slot(dc, dest, -1); in gen_jump()
384 static int adjust_jump_slot(DisasContext *dc, uint32_t dest, int slot) in adjust_jump_slot() argument
386 return translator_use_goto_tb(&dc->base, dest) ? slot : -1; in adjust_jump_slot()
389 static void gen_jumpi(DisasContext *dc, uint32_t dest, int slot) in gen_jumpi() argument
391 gen_jump_slot(dc, tcg_constant_i32(dest), in gen_jumpi()
392 adjust_jump_slot(dc, dest, slot)); in gen_jumpi()
395 static void gen_callw_slot(DisasContext *dc, int callinc, TCGv_i32 dest, in gen_callw_slot() argument
401 (callinc << 30) | (dc->base.pc_next & 0x3fffffff)); in gen_callw_slot()
402 gen_jump_slot(dc, dest, slot); in gen_callw_slot()
405 static bool gen_check_loop_end(DisasContext *dc, int slot) in gen_check_loop_end() argument
407 if (dc->base.pc_next == dc->lend) { in gen_check_loop_end()
412 if (dc->lbeg_off) { in gen_check_loop_end()
413 gen_jumpi(dc, dc->base.pc_next - dc->lbeg_off, slot); in gen_check_loop_end()
415 gen_jump(dc, cpu_SR[LBEG]); in gen_check_loop_end()
418 gen_jumpi(dc, dc->base.pc_next, -1); in gen_check_loop_end()
424 static void gen_jumpi_check_loop_end(DisasContext *dc, int slot) in gen_jumpi_check_loop_end() argument
426 if (!gen_check_loop_end(dc, slot)) { in gen_jumpi_check_loop_end()
427 gen_jumpi(dc, dc->base.pc_next, slot); in gen_jumpi_check_loop_end()
431 static void gen_brcond(DisasContext *dc, TCGCond cond, in gen_brcond() argument
437 gen_jumpi_check_loop_end(dc, 0); in gen_brcond()
439 gen_jumpi(dc, addr, 1); in gen_brcond()
442 static void gen_brcondi(DisasContext *dc, TCGCond cond, in gen_brcondi() argument
445 gen_brcond(dc, cond, t0, tcg_constant_i32(t1), addr); in gen_brcondi()
448 static uint32_t test_exceptions_sr(DisasContext *dc, const OpcodeArg arg[], in test_exceptions_sr() argument
451 return xtensa_option_enabled(dc->config, par[1]) ? 0 : XTENSA_OP_ILL; in test_exceptions_sr()
454 static uint32_t test_exceptions_ccompare(DisasContext *dc, in test_exceptions_ccompare() argument
460 if (n >= dc->config->nccompare) { in test_exceptions_ccompare()
463 return test_exceptions_sr(dc, arg, par); in test_exceptions_ccompare()
466 static uint32_t test_exceptions_dbreak(DisasContext *dc, const OpcodeArg arg[], in test_exceptions_dbreak() argument
477 if (n >= dc->config->ndbreak) { in test_exceptions_dbreak()
480 return test_exceptions_sr(dc, arg, par); in test_exceptions_dbreak()
483 static uint32_t test_exceptions_ibreak(DisasContext *dc, const OpcodeArg arg[], in test_exceptions_ibreak() argument
488 if (n >= dc->config->nibreak) { in test_exceptions_ibreak()
491 return test_exceptions_sr(dc, arg, par); in test_exceptions_ibreak()
494 static uint32_t test_exceptions_hpi(DisasContext *dc, const OpcodeArg arg[], in test_exceptions_hpi() argument
508 if (n > dc->config->nlevel) { in test_exceptions_hpi()
511 return test_exceptions_sr(dc, arg, par); in test_exceptions_hpi()
514 static MemOp gen_load_store_alignment(DisasContext *dc, MemOp mop, in gen_load_store_alignment() argument
521 !option_enabled(dc, XTENSA_OPTION_HW_ALIGNMENT)) { in gen_load_store_alignment()
524 if (!option_enabled(dc, XTENSA_OPTION_UNALIGNED_EXCEPTION)) { in gen_load_store_alignment()
530 static bool gen_window_check(DisasContext *dc, uint32_t mask) in gen_window_check() argument
534 if (r / 4 > dc->window) { in gen_window_check()
535 TCGv_i32 pc = tcg_constant_i32(dc->pc); in gen_window_check()
539 dc->base.is_jmp = DISAS_NORETURN; in gen_window_check()
557 static void gen_zero_check(DisasContext *dc, const OpcodeArg arg[]) in gen_zero_check() argument
562 gen_exception_cause(dc, INTEGER_DIVIDE_BY_ZERO_CAUSE); in gen_zero_check()
566 static inline unsigned xtensa_op0_insn_len(DisasContext *dc, uint8_t op0) in xtensa_op0_insn_len() argument
568 return xtensa_isa_length_from_chars(dc->config->isa, &op0); in xtensa_op0_insn_len()
571 static int gen_postprocess(DisasContext *dc, int slot) in gen_postprocess() argument
573 uint32_t op_flags = dc->op_flags; in gen_postprocess()
577 translator_io_start(&dc->base); in gen_postprocess()
837 static void disas_xtensa_insn(CPUXtensaState *env, DisasContext *dc) in disas_xtensa_insn() argument
839 xtensa_isa isa = dc->config->isa; in disas_xtensa_insn()
840 unsigned char b[MAX_INSN_LENGTH] = {translator_ldub(env, &dc->base, in disas_xtensa_insn()
841 dc->pc)}; in disas_xtensa_insn()
842 unsigned len = xtensa_op0_insn_len(dc, b[0]); in disas_xtensa_insn()
858 dc->pc); in disas_xtensa_insn()
859 gen_exception_cause(dc, ILLEGAL_INSTRUCTION_CAUSE); in disas_xtensa_insn()
860 dc->base.pc_next = dc->pc + 1; in disas_xtensa_insn()
864 dc->base.pc_next = dc->pc + len; in disas_xtensa_insn()
866 b[i] = translator_ldub(env, &dc->base, dc->pc + i); in disas_xtensa_insn()
868 xtensa_insnbuf_from_chars(isa, dc->insnbuf, b, len); in disas_xtensa_insn()
869 fmt = xtensa_format_decode(isa, dc->insnbuf); in disas_xtensa_insn()
873 dc->pc); in disas_xtensa_insn()
874 gen_exception_cause(dc, ILLEGAL_INSTRUCTION_CAUSE); in disas_xtensa_insn()
884 xtensa_format_get_slot(isa, fmt, slot, dc->insnbuf, dc->slotbuf); in disas_xtensa_insn()
885 opc = xtensa_opcode_decode(isa, fmt, slot, dc->slotbuf); in disas_xtensa_insn()
889 slot, dc->pc); in disas_xtensa_insn()
890 gen_exception_cause(dc, ILLEGAL_INSTRUCTION_CAUSE); in disas_xtensa_insn()
901 register_file = dc->config->regfile[rf]; in disas_xtensa_insn()
903 if (rf == dc->config->a_regfile) { in disas_xtensa_insn()
907 dc->slotbuf, &v); in disas_xtensa_insn()
916 dc->slotbuf, &v); in disas_xtensa_insn()
920 xtensa_operand_undo_reloc(isa, opc, opnd, &v, dc->pc); in disas_xtensa_insn()
933 ops = dc->config->opcode_ops[opc]; in disas_xtensa_insn()
939 op_flags |= ops->test_exceptions(dc, arg, ops->par); in disas_xtensa_insn()
944 xtensa_opcode_name(isa, opc), slot, dc->pc); in disas_xtensa_insn()
948 gen_exception_cause(dc, ILLEGAL_INSTRUCTION_CAUSE); in disas_xtensa_insn()
955 windowed_register |= ops->test_overflow(dc, arg, ops->par); in disas_xtensa_insn()
974 dc->slotbuf, &v); in disas_xtensa_insn()
1014 dc->pc); in disas_xtensa_insn()
1015 gen_exception_cause(dc, ILLEGAL_INSTRUCTION_CAUSE); in disas_xtensa_insn()
1023 !gen_check_privilege(dc)) { in disas_xtensa_insn()
1028 gen_exception_cause(dc, SYSCALL_CAUSE); in disas_xtensa_insn()
1032 if ((op_flags & XTENSA_OP_DEBUG_BREAK) && dc->debug) { in disas_xtensa_insn()
1033 gen_debug_exception(dc, debug_cause); in disas_xtensa_insn()
1037 if (windowed_register && !gen_window_check(dc, windowed_register)) { in disas_xtensa_insn()
1042 TCGv_i32 pc = tcg_constant_i32(dc->pc); in disas_xtensa_insn()
1048 TCGv_i32 pc = tcg_constant_i32(dc->pc); in disas_xtensa_insn()
1053 if (coprocessor && !gen_check_cpenable(dc, coprocessor)) { in disas_xtensa_insn()
1090 gen_zero_check(dc, slot_prop[slot].arg); in disas_xtensa_insn()
1095 dc->op_flags = op_flags; in disas_xtensa_insn()
1101 ops->translate(dc, pslot->arg, ops->par); in disas_xtensa_insn()
1104 if (dc->base.is_jmp == DISAS_NEXT) { in disas_xtensa_insn()
1105 gen_postprocess(dc, 0); in disas_xtensa_insn()
1106 dc->op_flags = 0; in disas_xtensa_insn()
1109 gen_jumpi_check_loop_end(dc, -1); in disas_xtensa_insn()
1111 gen_jumpi_check_loop_end(dc, 0); in disas_xtensa_insn()
1113 gen_check_loop_end(dc, 0); in disas_xtensa_insn()
1116 dc->pc = dc->base.pc_next; in disas_xtensa_insn()
1119 static inline unsigned xtensa_insn_len(CPUXtensaState *env, DisasContext *dc) in xtensa_insn_len() argument
1121 uint8_t b0 = translator_ldub(env, &dc->base, dc->pc); in xtensa_insn_len()
1122 return xtensa_op0_insn_len(dc, b0); in xtensa_insn_len()
1128 DisasContext *dc = container_of(dcbase, DisasContext, base); in xtensa_tr_init_disas_context() local
1129 uint32_t tb_flags = dc->base.tb->flags; in xtensa_tr_init_disas_context()
1131 dc->config = cpu_env(cpu)->config; in xtensa_tr_init_disas_context()
1132 dc->pc = dc->base.pc_first; in xtensa_tr_init_disas_context()
1133 dc->ring = tb_flags & XTENSA_TBFLAG_RING_MASK; in xtensa_tr_init_disas_context()
1134 dc->cring = (tb_flags & XTENSA_TBFLAG_EXCM) ? 0 : dc->ring; in xtensa_tr_init_disas_context()
1135 dc->lbeg_off = (dc->base.tb->cs_base & XTENSA_CSBASE_LBEG_OFF_MASK) >> in xtensa_tr_init_disas_context()
1137 dc->lend = (dc->base.tb->cs_base & XTENSA_CSBASE_LEND_MASK) + in xtensa_tr_init_disas_context()
1138 (dc->base.pc_first & TARGET_PAGE_MASK); in xtensa_tr_init_disas_context()
1139 dc->debug = tb_flags & XTENSA_TBFLAG_DEBUG; in xtensa_tr_init_disas_context()
1140 dc->icount = tb_flags & XTENSA_TBFLAG_ICOUNT; in xtensa_tr_init_disas_context()
1141 dc->cpenable = (tb_flags & XTENSA_TBFLAG_CPENABLE_MASK) >> in xtensa_tr_init_disas_context()
1143 dc->window = ((tb_flags & XTENSA_TBFLAG_WINDOW_MASK) >> in xtensa_tr_init_disas_context()
1145 dc->cwoe = tb_flags & XTENSA_TBFLAG_CWOE; in xtensa_tr_init_disas_context()
1146 dc->callinc = ((tb_flags & XTENSA_TBFLAG_CALLINC_MASK) >> in xtensa_tr_init_disas_context()
1148 init_sar_tracker(dc); in xtensa_tr_init_disas_context()
1153 DisasContext *dc = container_of(dcbase, DisasContext, base); in xtensa_tr_tb_start() local
1155 if (dc->icount) { in xtensa_tr_tb_start()
1156 dc->next_icount = tcg_temp_new_i32(); in xtensa_tr_tb_start()
1167 DisasContext *dc = container_of(dcbase, DisasContext, base); in xtensa_tr_translate_insn() local
1173 if ((tb_cflags(dc->base.tb) & CF_USE_ICOUNT) in xtensa_tr_translate_insn()
1174 && (dc->base.tb->flags & XTENSA_TBFLAG_YIELD)) { in xtensa_tr_translate_insn()
1175 gen_exception(dc, EXCP_YIELD); in xtensa_tr_translate_insn()
1176 dc->base.pc_next = dc->pc + 1; in xtensa_tr_translate_insn()
1177 dc->base.is_jmp = DISAS_NORETURN; in xtensa_tr_translate_insn()
1181 if (dc->icount) { in xtensa_tr_translate_insn()
1184 tcg_gen_addi_i32(dc->next_icount, cpu_SR[ICOUNT], 1); in xtensa_tr_translate_insn()
1185 tcg_gen_brcondi_i32(TCG_COND_NE, dc->next_icount, 0, label); in xtensa_tr_translate_insn()
1186 tcg_gen_mov_i32(dc->next_icount, cpu_SR[ICOUNT]); in xtensa_tr_translate_insn()
1187 if (dc->debug) { in xtensa_tr_translate_insn()
1188 gen_debug_exception(dc, DEBUGCAUSE_IC); in xtensa_tr_translate_insn()
1193 disas_xtensa_insn(env, dc); in xtensa_tr_translate_insn()
1195 if (dc->icount) { in xtensa_tr_translate_insn()
1196 tcg_gen_mov_i32(cpu_SR[ICOUNT], dc->next_icount); in xtensa_tr_translate_insn()
1200 page_start = dc->base.pc_first & TARGET_PAGE_MASK; in xtensa_tr_translate_insn()
1201 if (dc->base.is_jmp == DISAS_NEXT && in xtensa_tr_translate_insn()
1202 (dc->pc - page_start >= TARGET_PAGE_SIZE || in xtensa_tr_translate_insn()
1203 dc->pc - page_start + xtensa_insn_len(env, dc) > TARGET_PAGE_SIZE)) { in xtensa_tr_translate_insn()
1204 dc->base.is_jmp = DISAS_TOO_MANY; in xtensa_tr_translate_insn()
1210 DisasContext *dc = container_of(dcbase, DisasContext, base); in xtensa_tr_tb_stop() local
1212 switch (dc->base.is_jmp) { in xtensa_tr_tb_stop()
1216 gen_jumpi(dc, dc->pc, 0); in xtensa_tr_tb_stop()
1234 DisasContext dc = {}; in xtensa_translate_code() local
1236 &xtensa_translator_ops, &dc.base); in xtensa_translate_code()
1306 static void translate_abs(DisasContext *dc, const OpcodeArg arg[], in translate_abs() argument
1312 static void translate_add(DisasContext *dc, const OpcodeArg arg[], in translate_add() argument
1318 static void translate_addi(DisasContext *dc, const OpcodeArg arg[], in translate_addi() argument
1324 static void translate_addx(DisasContext *dc, const OpcodeArg arg[], in translate_addx() argument
1332 static void translate_all(DisasContext *dc, const OpcodeArg arg[], in translate_all() argument
1350 static void translate_and(DisasContext *dc, const OpcodeArg arg[], in translate_and() argument
1356 static void translate_ball(DisasContext *dc, const OpcodeArg arg[], in translate_ball() argument
1361 gen_brcond(dc, par[0], tmp, arg[1].in, arg[2].imm); in translate_ball()
1364 static void translate_bany(DisasContext *dc, const OpcodeArg arg[], in translate_bany() argument
1369 gen_brcondi(dc, par[0], tmp, 0, arg[2].imm); in translate_bany()
1372 static void translate_b(DisasContext *dc, const OpcodeArg arg[], in translate_b() argument
1375 gen_brcond(dc, par[0], arg[0].in, arg[1].in, arg[2].imm); in translate_b()
1378 static void translate_bb(DisasContext *dc, const OpcodeArg arg[], in translate_bb() argument
1390 gen_brcondi(dc, par[0], tmp, 0, arg[2].imm); in translate_bb()
1393 static void translate_bbi(DisasContext *dc, const OpcodeArg arg[], in translate_bbi() argument
1402 gen_brcondi(dc, par[0], tmp, 0, arg[2].imm); in translate_bbi()
1405 static void translate_bi(DisasContext *dc, const OpcodeArg arg[], in translate_bi() argument
1408 gen_brcondi(dc, par[0], arg[0].in, arg[1].imm, arg[2].imm); in translate_bi()
1411 static void translate_bz(DisasContext *dc, const OpcodeArg arg[], in translate_bz() argument
1414 gen_brcondi(dc, par[0], arg[0].in, 0, arg[1].imm); in translate_bz()
1425 static void translate_boolean(DisasContext *dc, const OpcodeArg arg[], in translate_boolean() argument
1445 static void translate_bp(DisasContext *dc, const OpcodeArg arg[], in translate_bp() argument
1451 gen_brcondi(dc, par[0], tmp, 0, arg[1].imm); in translate_bp()
1454 static void translate_call0(DisasContext *dc, const OpcodeArg arg[], in translate_call0() argument
1457 tcg_gen_movi_i32(cpu_R[0], dc->base.pc_next); in translate_call0()
1458 gen_jumpi(dc, arg[0].imm, 0); in translate_call0()
1461 static void translate_callw(DisasContext *dc, const OpcodeArg arg[], in translate_callw() argument
1465 gen_callw_slot(dc, par[0], tmp, adjust_jump_slot(dc, arg[0].imm, 0)); in translate_callw()
1468 static void translate_callx0(DisasContext *dc, const OpcodeArg arg[], in translate_callx0() argument
1473 tcg_gen_movi_i32(cpu_R[0], dc->base.pc_next); in translate_callx0()
1474 gen_jump(dc, tmp); in translate_callx0()
1477 static void translate_callxw(DisasContext *dc, const OpcodeArg arg[], in translate_callxw() argument
1483 gen_callw_slot(dc, par[0], tmp, -1); in translate_callxw()
1486 static void translate_clamps(DisasContext *dc, const OpcodeArg arg[], in translate_clamps() argument
1496 static void translate_clrb_expstate(DisasContext *dc, const OpcodeArg arg[], in translate_clrb_expstate() argument
1503 static void translate_clrex(DisasContext *dc, const OpcodeArg arg[], in translate_clrex() argument
1509 static void translate_const16(DisasContext *dc, const OpcodeArg arg[], in translate_const16() argument
1517 static void translate_dcache(DisasContext *dc, const OpcodeArg arg[], in translate_dcache() argument
1524 tcg_gen_qemu_ld_i32(res, addr, dc->cring, MO_UB); in translate_dcache()
1527 static void translate_depbits(DisasContext *dc, const OpcodeArg arg[], in translate_depbits() argument
1534 static void translate_diwbuip(DisasContext *dc, const OpcodeArg arg[], in translate_diwbuip() argument
1537 tcg_gen_addi_i32(arg[0].out, arg[0].in, dc->config->dcache_line_bytes); in translate_diwbuip()
1540 static uint32_t test_exceptions_entry(DisasContext *dc, const OpcodeArg arg[], in test_exceptions_entry() argument
1543 if (arg[0].imm > 3 || !dc->cwoe) { in test_exceptions_entry()
1545 "Illegal entry instruction(pc = %08x)\n", dc->pc); in test_exceptions_entry()
1552 static uint32_t test_overflow_entry(DisasContext *dc, const OpcodeArg arg[], in test_overflow_entry() argument
1555 return 1 << (dc->callinc * 4); in test_overflow_entry()
1558 static void translate_entry(DisasContext *dc, const OpcodeArg arg[], in translate_entry() argument
1561 TCGv_i32 pc = tcg_constant_i32(dc->pc); in translate_entry()
1567 static void translate_extui(DisasContext *dc, const OpcodeArg arg[], in translate_extui() argument
1577 static void translate_getex(DisasContext *dc, const OpcodeArg arg[], in translate_getex() argument
1587 static void translate_icache(DisasContext *dc, const OpcodeArg arg[], in translate_icache() argument
1593 tcg_gen_movi_i32(cpu_pc, dc->pc); in translate_icache()
1599 static void translate_itlb(DisasContext *dc, const OpcodeArg arg[], in translate_itlb() argument
1609 static void translate_j(DisasContext *dc, const OpcodeArg arg[], in translate_j() argument
1612 gen_jumpi(dc, arg[0].imm, 0); in translate_j()
1615 static void translate_jx(DisasContext *dc, const OpcodeArg arg[], in translate_jx() argument
1618 gen_jump(dc, arg[0].in); in translate_jx()
1621 static void translate_l32e(DisasContext *dc, const OpcodeArg arg[], in translate_l32e() argument
1628 mop = gen_load_store_alignment(dc, MO_TEUL, addr); in translate_l32e()
1629 tcg_gen_qemu_ld_tl(arg[0].out, addr, dc->ring, mop); in translate_l32e()
1633 static void gen_check_exclusive(DisasContext *dc, TCGv_i32 addr, bool is_write) in gen_check_exclusive() argument
1637 static void gen_check_exclusive(DisasContext *dc, TCGv_i32 addr, bool is_write) in gen_check_exclusive() argument
1639 if (!option_enabled(dc, XTENSA_OPTION_MPU)) { in gen_check_exclusive()
1640 TCGv_i32 pc = tcg_constant_i32(dc->pc); in gen_check_exclusive()
1648 static void translate_l32ex(DisasContext *dc, const OpcodeArg arg[], in translate_l32ex() argument
1655 mop = gen_load_store_alignment(dc, MO_TEUL | MO_ALIGN, addr); in translate_l32ex()
1656 gen_check_exclusive(dc, addr, false); in translate_l32ex()
1657 tcg_gen_qemu_ld_i32(arg[0].out, addr, dc->cring, mop); in translate_l32ex()
1662 static void translate_ldst(DisasContext *dc, const OpcodeArg arg[], in translate_ldst() argument
1669 mop = gen_load_store_alignment(dc, par[0], addr); in translate_ldst()
1675 tcg_gen_qemu_st_tl(arg[0].in, addr, dc->cring, mop); in translate_ldst()
1677 tcg_gen_qemu_ld_tl(arg[0].out, addr, dc->cring, mop); in translate_ldst()
1684 static void translate_lct(DisasContext *dc, const OpcodeArg arg[], in translate_lct() argument
1690 static void translate_l32r(DisasContext *dc, const OpcodeArg arg[], in translate_l32r() argument
1695 if (dc->base.tb->flags & XTENSA_TBFLAG_LITBASE) { in translate_l32r()
1701 tcg_gen_qemu_ld_i32(arg[0].out, tmp, dc->cring, MO_TEUL); in translate_l32r()
1704 static void translate_loop(DisasContext *dc, const OpcodeArg arg[], in translate_loop() argument
1710 tcg_gen_movi_i32(cpu_SR[LBEG], dc->base.pc_next); in translate_loop()
1716 gen_jumpi(dc, lend, 1); in translate_loop()
1720 gen_jumpi(dc, dc->base.pc_next, 0); in translate_loop()
1741 static void translate_mac16(DisasContext *dc, const OpcodeArg arg[], in translate_mac16() argument
1755 mop = gen_load_store_alignment(dc, MO_TEUL, vaddr); in translate_mac16()
1756 tcg_gen_qemu_ld_tl(mem32, vaddr, dc->cring, mop); in translate_mac16()
1795 static void translate_memw(DisasContext *dc, const OpcodeArg arg[], in translate_memw() argument
1801 static void translate_smin(DisasContext *dc, const OpcodeArg arg[], in translate_smin() argument
1807 static void translate_umin(DisasContext *dc, const OpcodeArg arg[], in translate_umin() argument
1813 static void translate_smax(DisasContext *dc, const OpcodeArg arg[], in translate_smax() argument
1819 static void translate_umax(DisasContext *dc, const OpcodeArg arg[], in translate_umax() argument
1825 static void translate_mov(DisasContext *dc, const OpcodeArg arg[], in translate_mov() argument
1831 static void translate_movcond(DisasContext *dc, const OpcodeArg arg[], in translate_movcond() argument
1840 static void translate_movi(DisasContext *dc, const OpcodeArg arg[], in translate_movi() argument
1846 static void translate_movp(DisasContext *dc, const OpcodeArg arg[], in translate_movp() argument
1858 static void translate_movsp(DisasContext *dc, const OpcodeArg arg[], in translate_movsp() argument
1864 static void translate_mul16(DisasContext *dc, const OpcodeArg arg[], in translate_mul16() argument
1880 static void translate_mull(DisasContext *dc, const OpcodeArg arg[], in translate_mull() argument
1886 static void translate_mulh(DisasContext *dc, const OpcodeArg arg[], in translate_mulh() argument
1898 static void translate_neg(DisasContext *dc, const OpcodeArg arg[], in translate_neg() argument
1904 static void translate_nop(DisasContext *dc, const OpcodeArg arg[], in translate_nop() argument
1909 static void translate_nsa(DisasContext *dc, const OpcodeArg arg[], in translate_nsa() argument
1915 static void translate_nsau(DisasContext *dc, const OpcodeArg arg[], in translate_nsau() argument
1921 static void translate_or(DisasContext *dc, const OpcodeArg arg[], in translate_or() argument
1927 static void translate_ptlb(DisasContext *dc, const OpcodeArg arg[], in translate_ptlb() argument
1933 tcg_gen_movi_i32(cpu_pc, dc->pc); in translate_ptlb()
1938 static void translate_pptlb(DisasContext *dc, const OpcodeArg arg[], in translate_pptlb() argument
1942 tcg_gen_movi_i32(cpu_pc, dc->pc); in translate_pptlb()
1947 static void translate_quos(DisasContext *dc, const OpcodeArg arg[], in translate_quos() argument
1971 static void translate_quou(DisasContext *dc, const OpcodeArg arg[], in translate_quou() argument
1978 static void translate_read_impwire(DisasContext *dc, const OpcodeArg arg[], in translate_read_impwire() argument
1985 static void translate_remu(DisasContext *dc, const OpcodeArg arg[], in translate_remu() argument
1992 static void translate_rer(DisasContext *dc, const OpcodeArg arg[], in translate_rer() argument
1998 static void translate_ret(DisasContext *dc, const OpcodeArg arg[], in translate_ret() argument
2001 gen_jump(dc, cpu_R[0]); in translate_ret()
2004 static uint32_t test_exceptions_retw(DisasContext *dc, const OpcodeArg arg[], in test_exceptions_retw() argument
2007 if (!dc->cwoe) { in test_exceptions_retw()
2009 "Illegal retw instruction(pc = %08x)\n", dc->pc); in test_exceptions_retw()
2012 TCGv_i32 pc = tcg_constant_i32(dc->pc); in test_exceptions_retw()
2019 static void translate_retw(DisasContext *dc, const OpcodeArg arg[], in translate_retw() argument
2026 tcg_gen_movi_i32(tmp, dc->pc); in translate_retw()
2029 gen_jump(dc, tmp); in translate_retw()
2032 static void translate_rfde(DisasContext *dc, const OpcodeArg arg[], in translate_rfde() argument
2035 gen_jump(dc, cpu_SR[dc->config->ndepc ? DEPC : EPC1]); in translate_rfde()
2038 static void translate_rfe(DisasContext *dc, const OpcodeArg arg[], in translate_rfe() argument
2042 gen_jump(dc, cpu_SR[EPC1]); in translate_rfe()
2045 static void translate_rfi(DisasContext *dc, const OpcodeArg arg[], in translate_rfi() argument
2049 gen_jump(dc, cpu_SR[EPC1 + arg[0].imm - 1]); in translate_rfi()
2052 static void translate_rfw(DisasContext *dc, const OpcodeArg arg[], in translate_rfw() argument
2069 gen_jump(dc, cpu_SR[EPC1]); in translate_rfw()
2072 static void translate_rotw(DisasContext *dc, const OpcodeArg arg[], in translate_rotw() argument
2078 static void translate_rsil(DisasContext *dc, const OpcodeArg arg[], in translate_rsil() argument
2086 static void translate_rsr(DisasContext *dc, const OpcodeArg arg[], in translate_rsr() argument
2096 static void translate_rsr_ccount(DisasContext *dc, const OpcodeArg arg[], in translate_rsr_ccount() argument
2100 translator_io_start(&dc->base); in translate_rsr_ccount()
2106 static void translate_rsr_ptevaddr(DisasContext *dc, const OpcodeArg arg[], in translate_rsr_ptevaddr() argument
2118 static void translate_rtlb(DisasContext *dc, const OpcodeArg arg[], in translate_rtlb() argument
2133 static void translate_rptlb0(DisasContext *dc, const OpcodeArg arg[], in translate_rptlb0() argument
2141 static void translate_rptlb1(DisasContext *dc, const OpcodeArg arg[], in translate_rptlb1() argument
2149 static void translate_rur(DisasContext *dc, const OpcodeArg arg[], in translate_rur() argument
2155 static void translate_setb_expstate(DisasContext *dc, const OpcodeArg arg[], in translate_setb_expstate() argument
2163 static void gen_check_atomctl(DisasContext *dc, TCGv_i32 addr) in gen_check_atomctl() argument
2167 static void gen_check_atomctl(DisasContext *dc, TCGv_i32 addr) in gen_check_atomctl() argument
2169 TCGv_i32 pc = tcg_constant_i32(dc->pc); in gen_check_atomctl()
2175 static void translate_s32c1i(DisasContext *dc, const OpcodeArg arg[], in translate_s32c1i() argument
2184 mop = gen_load_store_alignment(dc, MO_TEUL | MO_ALIGN, addr); in translate_s32c1i()
2185 gen_check_atomctl(dc, addr); in translate_s32c1i()
2187 tmp, dc->cring, mop); in translate_s32c1i()
2190 static void translate_s32e(DisasContext *dc, const OpcodeArg arg[], in translate_s32e() argument
2197 mop = gen_load_store_alignment(dc, MO_TEUL, addr); in translate_s32e()
2198 tcg_gen_qemu_st_tl(arg[0].in, addr, dc->ring, mop); in translate_s32e()
2201 static void translate_s32ex(DisasContext *dc, const OpcodeArg arg[], in translate_s32ex() argument
2212 mop = gen_load_store_alignment(dc, MO_TEUL | MO_ALIGN, addr); in translate_s32ex()
2214 gen_check_exclusive(dc, addr, true); in translate_s32ex()
2216 arg[0].in, dc->cring, mop); in translate_s32ex()
2226 static void translate_salt(DisasContext *dc, const OpcodeArg arg[], in translate_salt() argument
2234 static void translate_sext(DisasContext *dc, const OpcodeArg arg[], in translate_sext() argument
2240 static uint32_t test_exceptions_simcall(DisasContext *dc, in test_exceptions_simcall() argument
2245 if (semihosting_enabled(dc->cring != 0)) { in test_exceptions_simcall()
2252 return dc->config->hw_version <= 250002 ? XTENSA_OP_ILL : 0; in test_exceptions_simcall()
2255 static void translate_simcall(DisasContext *dc, const OpcodeArg arg[], in translate_simcall() argument
2259 if (semihosting_enabled(dc->cring != 0)) { in translate_simcall()
2278 static void translate_sll(DisasContext *dc, const OpcodeArg arg[], in translate_sll() argument
2281 if (dc->sar_m32_5bit) { in translate_sll()
2282 tcg_gen_shl_i32(arg[0].out, arg[1].in, dc->sar_m32); in translate_sll()
2293 static void translate_slli(DisasContext *dc, const OpcodeArg arg[], in translate_slli() argument
2303 static void translate_sra(DisasContext *dc, const OpcodeArg arg[], in translate_sra() argument
2306 if (dc->sar_m32_5bit) { in translate_sra()
2315 static void translate_srai(DisasContext *dc, const OpcodeArg arg[], in translate_srai() argument
2321 static void translate_src(DisasContext *dc, const OpcodeArg arg[], in translate_src() argument
2329 static void translate_srl(DisasContext *dc, const OpcodeArg arg[], in translate_srl() argument
2332 if (dc->sar_m32_5bit) { in translate_srl()
2344 static void translate_srli(DisasContext *dc, const OpcodeArg arg[], in translate_srli() argument
2350 static void translate_ssa8b(DisasContext *dc, const OpcodeArg arg[], in translate_ssa8b() argument
2355 gen_left_shift_sar(dc, tmp); in translate_ssa8b()
2358 static void translate_ssa8l(DisasContext *dc, const OpcodeArg arg[], in translate_ssa8l() argument
2363 gen_right_shift_sar(dc, tmp); in translate_ssa8l()
2366 static void translate_ssai(DisasContext *dc, const OpcodeArg arg[], in translate_ssai() argument
2369 gen_right_shift_sar(dc, tcg_constant_i32(arg[0].imm)); in translate_ssai()
2372 static void translate_ssl(DisasContext *dc, const OpcodeArg arg[], in translate_ssl() argument
2375 gen_left_shift_sar(dc, arg[0].in); in translate_ssl()
2378 static void translate_ssr(DisasContext *dc, const OpcodeArg arg[], in translate_ssr() argument
2381 gen_right_shift_sar(dc, arg[0].in); in translate_ssr()
2384 static void translate_sub(DisasContext *dc, const OpcodeArg arg[], in translate_sub() argument
2390 static void translate_subx(DisasContext *dc, const OpcodeArg arg[], in translate_subx() argument
2398 static void translate_waiti(DisasContext *dc, const OpcodeArg arg[], in translate_waiti() argument
2402 TCGv_i32 pc = tcg_constant_i32(dc->base.pc_next); in translate_waiti()
2404 translator_io_start(&dc->base); in translate_waiti()
2409 static void translate_wtlb(DisasContext *dc, const OpcodeArg arg[], in translate_wtlb() argument
2419 static void translate_wptlb(DisasContext *dc, const OpcodeArg arg[], in translate_wptlb() argument
2427 static void translate_wer(DisasContext *dc, const OpcodeArg arg[], in translate_wer() argument
2433 static void translate_wrmsk_expstate(DisasContext *dc, const OpcodeArg arg[], in translate_wrmsk_expstate() argument
2440 static void translate_wsr(DisasContext *dc, const OpcodeArg arg[], in translate_wsr() argument
2448 static void translate_wsr_mask(DisasContext *dc, const OpcodeArg arg[], in translate_wsr_mask() argument
2456 static void translate_wsr_acchi(DisasContext *dc, const OpcodeArg arg[], in translate_wsr_acchi() argument
2462 static void translate_wsr_ccompare(DisasContext *dc, const OpcodeArg arg[], in translate_wsr_ccompare() argument
2468 assert(id < dc->config->nccompare); in translate_wsr_ccompare()
2469 translator_io_start(&dc->base); in translate_wsr_ccompare()
2475 static void translate_wsr_ccount(DisasContext *dc, const OpcodeArg arg[], in translate_wsr_ccount() argument
2479 translator_io_start(&dc->base); in translate_wsr_ccount()
2484 static void translate_wsr_dbreaka(DisasContext *dc, const OpcodeArg arg[], in translate_wsr_dbreaka() argument
2490 assert(id < dc->config->ndbreak); in translate_wsr_dbreaka()
2495 static void translate_wsr_dbreakc(DisasContext *dc, const OpcodeArg arg[], in translate_wsr_dbreakc() argument
2501 assert(id < dc->config->ndbreak); in translate_wsr_dbreakc()
2506 static void translate_wsr_ibreaka(DisasContext *dc, const OpcodeArg arg[], in translate_wsr_ibreaka() argument
2512 assert(id < dc->config->nibreak); in translate_wsr_ibreaka()
2517 static void translate_wsr_ibreakenable(DisasContext *dc, const OpcodeArg arg[], in translate_wsr_ibreakenable() argument
2525 static void translate_wsr_icount(DisasContext *dc, const OpcodeArg arg[], in translate_wsr_icount() argument
2529 if (dc->icount) { in translate_wsr_icount()
2530 tcg_gen_mov_i32(dc->next_icount, arg[0].in); in translate_wsr_icount()
2537 static void translate_wsr_intclear(DisasContext *dc, const OpcodeArg arg[], in translate_wsr_intclear() argument
2545 static void translate_wsr_intset(DisasContext *dc, const OpcodeArg arg[], in translate_wsr_intset() argument
2553 static void translate_wsr_memctl(DisasContext *dc, const OpcodeArg arg[], in translate_wsr_memctl() argument
2561 static void translate_wsr_mpuenb(DisasContext *dc, const OpcodeArg arg[], in translate_wsr_mpuenb() argument
2569 static void translate_wsr_ps(DisasContext *dc, const OpcodeArg arg[], in translate_wsr_ps() argument
2576 if (option_enabled(dc, XTENSA_OPTION_MMU) || in translate_wsr_ps()
2577 option_enabled(dc, XTENSA_OPTION_MPU)) { in translate_wsr_ps()
2584 static void translate_wsr_rasid(DisasContext *dc, const OpcodeArg arg[], in translate_wsr_rasid() argument
2592 static void translate_wsr_sar(DisasContext *dc, const OpcodeArg arg[], in translate_wsr_sar() argument
2596 if (dc->sar_m32_5bit) { in translate_wsr_sar()
2597 tcg_gen_discard_i32(dc->sar_m32); in translate_wsr_sar()
2599 dc->sar_5bit = false; in translate_wsr_sar()
2600 dc->sar_m32_5bit = false; in translate_wsr_sar()
2603 static void translate_wsr_windowbase(DisasContext *dc, const OpcodeArg arg[], in translate_wsr_windowbase() argument
2611 static void translate_wsr_windowstart(DisasContext *dc, const OpcodeArg arg[], in translate_wsr_windowstart() argument
2616 (1 << dc->config->nareg / 4) - 1); in translate_wsr_windowstart()
2620 static void translate_wur(DisasContext *dc, const OpcodeArg arg[], in translate_wur() argument
2626 static void translate_xor(DisasContext *dc, const OpcodeArg arg[], in translate_xor() argument
2632 static void translate_xsr(DisasContext *dc, const OpcodeArg arg[], in translate_xsr() argument
2646 static void translate_xsr_mask(DisasContext *dc, const OpcodeArg arg[], in translate_xsr_mask() argument
2660 static void translate_xsr_ccount(DisasContext *dc, const OpcodeArg arg[], in translate_xsr_ccount() argument
2666 translator_io_start(&dc->base); in translate_xsr_ccount()
2676 static void translate_xsr_##name(DisasContext *dc, const OpcodeArg arg[], \
2686 translate_wsr_##name(dc, arg, par); \
6239 static void translate_abs_d(DisasContext *dc, const OpcodeArg arg[], in translate_abs_d() argument
6245 static void translate_abs_s(DisasContext *dc, const OpcodeArg arg[], in translate_abs_s() argument
6255 static void translate_fpu2k_add_s(DisasContext *dc, const OpcodeArg arg[], in translate_fpu2k_add_s() argument
6272 static void translate_compare_d(DisasContext *dc, const OpcodeArg arg[], in translate_compare_d() argument
6299 static void translate_compare_s(DisasContext *dc, const OpcodeArg arg[], in translate_compare_s() argument
6329 static void translate_const_d(DisasContext *dc, const OpcodeArg arg[], in translate_const_d() argument
6347 static void translate_const_s(DisasContext *dc, const OpcodeArg arg[], in translate_const_s() argument
6369 static void translate_float_d(DisasContext *dc, const OpcodeArg arg[], in translate_float_d() argument
6381 static void translate_float_s(DisasContext *dc, const OpcodeArg arg[], in translate_float_s() argument
6396 static void translate_ftoi_d(DisasContext *dc, const OpcodeArg arg[], in translate_ftoi_d() argument
6411 static void translate_ftoi_s(DisasContext *dc, const OpcodeArg arg[], in translate_ftoi_s() argument
6429 static void translate_ldsti(DisasContext *dc, const OpcodeArg arg[], in translate_ldsti() argument
6436 mop = gen_load_store_alignment(dc, MO_TEUL, addr); in translate_ldsti()
6438 tcg_gen_qemu_st_tl(arg[0].in, addr, dc->cring, mop); in translate_ldsti()
6440 tcg_gen_qemu_ld_tl(arg[0].out, addr, dc->cring, mop); in translate_ldsti()
6447 static void translate_ldstx(DisasContext *dc, const OpcodeArg arg[], in translate_ldstx() argument
6454 mop = gen_load_store_alignment(dc, MO_TEUL, addr); in translate_ldstx()
6456 tcg_gen_qemu_st_tl(arg[0].in, addr, dc->cring, mop); in translate_ldstx()
6458 tcg_gen_qemu_ld_tl(arg[0].out, addr, dc->cring, mop); in translate_ldstx()
6465 static void translate_fpu2k_madd_s(DisasContext *dc, const OpcodeArg arg[], in translate_fpu2k_madd_s() argument
6472 static void translate_mov_d(DisasContext *dc, const OpcodeArg arg[], in translate_mov_d() argument
6478 static void translate_mov_s(DisasContext *dc, const OpcodeArg arg[], in translate_mov_s() argument
6488 static void translate_movcond_d(DisasContext *dc, const OpcodeArg arg[], in translate_movcond_d() argument
6500 static void translate_movcond_s(DisasContext *dc, const OpcodeArg arg[], in translate_movcond_s() argument
6510 translate_movcond_d(dc, arg, par); in translate_movcond_s()
6514 static void translate_movp_d(DisasContext *dc, const OpcodeArg arg[], in translate_movp_d() argument
6528 static void translate_movp_s(DisasContext *dc, const OpcodeArg arg[], in translate_movp_s() argument
6540 translate_movp_d(dc, arg, par); in translate_movp_s()
6544 static void translate_fpu2k_mul_s(DisasContext *dc, const OpcodeArg arg[], in translate_fpu2k_mul_s() argument
6551 static void translate_fpu2k_msub_s(DisasContext *dc, const OpcodeArg arg[], in translate_fpu2k_msub_s() argument
6558 static void translate_neg_d(DisasContext *dc, const OpcodeArg arg[], in translate_neg_d() argument
6564 static void translate_neg_s(DisasContext *dc, const OpcodeArg arg[], in translate_neg_s() argument
6574 static void translate_rfr_d(DisasContext *dc, const OpcodeArg arg[], in translate_rfr_d() argument
6580 static void translate_rfr_s(DisasContext *dc, const OpcodeArg arg[], in translate_rfr_s() argument
6590 static void translate_fpu2k_sub_s(DisasContext *dc, const OpcodeArg arg[], in translate_fpu2k_sub_s() argument
6597 static void translate_wfr_d(DisasContext *dc, const OpcodeArg arg[], in translate_wfr_d() argument
6603 static void translate_wfr_s(DisasContext *dc, const OpcodeArg arg[], in translate_wfr_s() argument
6613 static void translate_wur_fpu2k_fcr(DisasContext *dc, const OpcodeArg arg[], in translate_wur_fpu2k_fcr() argument
6619 static void translate_wur_fpu2k_fsr(DisasContext *dc, const OpcodeArg arg[], in translate_wur_fpu2k_fsr() argument
6842 static void translate_add_d(DisasContext *dc, const OpcodeArg arg[], in translate_add_d() argument
6848 static void translate_add_s(DisasContext *dc, const OpcodeArg arg[], in translate_add_s() argument
6851 if (option_enabled(dc, XTENSA_OPTION_DFPU_SINGLE_ONLY)) { in translate_add_s()
6863 static void translate_cvtd_s(DisasContext *dc, const OpcodeArg arg[], in translate_cvtd_s() argument
6872 static void translate_cvts_d(DisasContext *dc, const OpcodeArg arg[], in translate_cvts_d() argument
6881 static void translate_ldsti_d(DisasContext *dc, const OpcodeArg arg[], in translate_ldsti_d() argument
6893 mop = gen_load_store_alignment(dc, MO_TEUQ, addr); in translate_ldsti_d()
6895 tcg_gen_qemu_st_i64(arg[0].in, addr, dc->cring, mop); in translate_ldsti_d()
6897 tcg_gen_qemu_ld_i64(arg[0].out, addr, dc->cring, mop); in translate_ldsti_d()
6908 static void translate_ldsti_s(DisasContext *dc, const OpcodeArg arg[], in translate_ldsti_s() argument
6921 mop = gen_load_store_alignment(dc, MO_TEUL, addr); in translate_ldsti_s()
6924 tcg_gen_qemu_st_tl(arg32[0].in, addr, dc->cring, mop); in translate_ldsti_s()
6928 tcg_gen_qemu_ld_tl(arg32[0].out, addr, dc->cring, mop); in translate_ldsti_s()
6940 static void translate_ldstx_d(DisasContext *dc, const OpcodeArg arg[], in translate_ldstx_d() argument
6952 mop = gen_load_store_alignment(dc, MO_TEUQ, addr); in translate_ldstx_d()
6954 tcg_gen_qemu_st_i64(arg[0].in, addr, dc->cring, mop); in translate_ldstx_d()
6956 tcg_gen_qemu_ld_i64(arg[0].out, addr, dc->cring, mop); in translate_ldstx_d()
6967 static void translate_ldstx_s(DisasContext *dc, const OpcodeArg arg[], in translate_ldstx_s() argument
6980 mop = gen_load_store_alignment(dc, MO_TEUL, addr); in translate_ldstx_s()
6983 tcg_gen_qemu_st_tl(arg32[0].in, addr, dc->cring, mop); in translate_ldstx_s()
6987 tcg_gen_qemu_ld_tl(arg32[0].out, addr, dc->cring, mop); in translate_ldstx_s()
6999 static void translate_madd_d(DisasContext *dc, const OpcodeArg arg[], in translate_madd_d() argument
7006 static void translate_madd_s(DisasContext *dc, const OpcodeArg arg[], in translate_madd_s() argument
7009 if (option_enabled(dc, XTENSA_OPTION_DFPU_SINGLE_ONLY)) { in translate_madd_s()
7022 static void translate_mul_d(DisasContext *dc, const OpcodeArg arg[], in translate_mul_d() argument
7028 static void translate_mul_s(DisasContext *dc, const OpcodeArg arg[], in translate_mul_s() argument
7031 if (option_enabled(dc, XTENSA_OPTION_DFPU_SINGLE_ONLY)) { in translate_mul_s()
7043 static void translate_msub_d(DisasContext *dc, const OpcodeArg arg[], in translate_msub_d() argument
7050 static void translate_msub_s(DisasContext *dc, const OpcodeArg arg[], in translate_msub_s() argument
7053 if (option_enabled(dc, XTENSA_OPTION_DFPU_SINGLE_ONLY)) { in translate_msub_s()
7066 static void translate_sub_d(DisasContext *dc, const OpcodeArg arg[], in translate_sub_d() argument
7072 static void translate_sub_s(DisasContext *dc, const OpcodeArg arg[], in translate_sub_s() argument
7075 if (option_enabled(dc, XTENSA_OPTION_DFPU_SINGLE_ONLY)) { in translate_sub_s()
7087 static void translate_mkdadj_d(DisasContext *dc, const OpcodeArg arg[], in translate_mkdadj_d() argument
7093 static void translate_mkdadj_s(DisasContext *dc, const OpcodeArg arg[], in translate_mkdadj_s() argument
7103 static void translate_mksadj_d(DisasContext *dc, const OpcodeArg arg[], in translate_mksadj_d() argument
7109 static void translate_mksadj_s(DisasContext *dc, const OpcodeArg arg[], in translate_mksadj_s() argument
7119 static void translate_wur_fpu_fcr(DisasContext *dc, const OpcodeArg arg[], in translate_wur_fpu_fcr() argument
7125 static void translate_rur_fpu_fsr(DisasContext *dc, const OpcodeArg arg[], in translate_rur_fpu_fsr() argument
7131 static void translate_wur_fpu_fsr(DisasContext *dc, const OpcodeArg arg[], in translate_wur_fpu_fsr() argument