2  * Xtensa gdb server stub
4  * Copyright (c) 2003-2005 Fabrice Bellard
5  * Copyright (c) 2013 SUSE LINUX Products GmbH
28   xtRegisterTypeUserReg,        /* User defined registers (rur).  */
29   xtRegisterTypeTieRegfile,     /* User define register files.  */
30   xtRegisterTypeTieState,       /* TIE States (mapped on user regs).  */
49     for (i = 0; config->gdb_regmap.reg[i].targno >= 0; ++i) {  in xtensa_count_regs()
50         if (config->gdb_regmap.reg[i].type != xtRegisterTypeTieState &&  in xtensa_count_regs()
51             config->gdb_regmap.reg[i].type != xtRegisterTypeMapped &&  in xtensa_count_regs()
52             config->gdb_regmap.reg[i].type != xtRegisterTypeUnmapped) {  in xtensa_count_regs()
55                 if ((config->gdb_regmap.reg[i].flags &  in xtensa_count_regs()
69     const XtensaGdbReg *reg = env->config->gdb_regmap.reg + n;  in xtensa_cpu_gdb_read_register()
71     int num_regs = env->config->gdb_regmap.num_core_regs;  in xtensa_cpu_gdb_read_register()
73     int num_regs = env->config->gdb_regmap.num_regs;  in xtensa_cpu_gdb_read_register()
81     switch (reg->type) {  in xtensa_cpu_gdb_read_register()
83         return gdb_get_reg32(mem_buf, env->pc);  in xtensa_cpu_gdb_read_register()
87         return gdb_get_reg32(mem_buf, env->phys_regs[(reg->targno & 0xff)  in xtensa_cpu_gdb_read_register()
88                                                      % env->config->nareg]);  in xtensa_cpu_gdb_read_register()
91         return gdb_get_reg32(mem_buf, env->sregs[reg->targno & 0xff]);  in xtensa_cpu_gdb_read_register()
94         return gdb_get_reg32(mem_buf, env->uregs[reg->targno & 0xff]);  in xtensa_cpu_gdb_read_register()
97         i = reg->targno & 0x0f;  in xtensa_cpu_gdb_read_register()
98         switch (reg->size) {  in xtensa_cpu_gdb_read_register()
101                                  float32_val(env->fregs[i].f32[FP_F32_LOW]));  in xtensa_cpu_gdb_read_register()
103             return gdb_get_reg64(mem_buf, float64_val(env->fregs[i].f64));  in xtensa_cpu_gdb_read_register()
106                           __func__, n, reg->size);  in xtensa_cpu_gdb_read_register()
107             return gdb_get_zeroes(mem_buf, reg->size);  in xtensa_cpu_gdb_read_register()
111         return gdb_get_reg32(mem_buf, env->regs[reg->targno & 0x0f]);  in xtensa_cpu_gdb_read_register()
115                       __func__, n, reg->type);  in xtensa_cpu_gdb_read_register()
116         return gdb_get_zeroes(mem_buf, reg->size);  in xtensa_cpu_gdb_read_register()
124     const XtensaGdbReg *reg = env->config->gdb_regmap.reg + n;  in xtensa_cpu_gdb_write_register()
126     int num_regs = env->config->gdb_regmap.num_core_regs;  in xtensa_cpu_gdb_write_register()
128     int num_regs = env->config->gdb_regmap.num_regs;  in xtensa_cpu_gdb_write_register()
137     switch (reg->type) {  in xtensa_cpu_gdb_write_register()
139         env->pc = tmp;  in xtensa_cpu_gdb_write_register()
143         env->phys_regs[(reg->targno & 0xff) % env->config->nareg] = tmp;  in xtensa_cpu_gdb_write_register()
148         env->sregs[reg->targno & 0xff] = tmp;  in xtensa_cpu_gdb_write_register()
152         env->uregs[reg->targno & 0xff] = tmp;  in xtensa_cpu_gdb_write_register()
156         switch (reg->size) {  in xtensa_cpu_gdb_write_register()
158             env->fregs[reg->targno & 0x0f].f32[FP_F32_LOW] = make_float32(tmp);  in xtensa_cpu_gdb_write_register()
161             env->fregs[reg->targno & 0x0f].f64 = make_float64(tmp);  in xtensa_cpu_gdb_write_register()
165                           __func__, n, reg->size);  in xtensa_cpu_gdb_write_register()
166             return reg->size;  in xtensa_cpu_gdb_write_register()
170         env->regs[reg->targno & 0x0f] = tmp;  in xtensa_cpu_gdb_write_register()
175                       __func__, n, reg->type);  in xtensa_cpu_gdb_write_register()
176         return reg->size;  in xtensa_cpu_gdb_write_register()