Lines Matching refs:xtensa_arg_internal

2713 static xtensa_arg_internal Iclass_xt_iclass_rfe_stateArgs[] = {
2718 static xtensa_arg_internal Iclass_xt_iclass_rfde_stateArgs[] = {
2722 static xtensa_arg_internal Iclass_xt_iclass_call12_args[] = {
2727 static xtensa_arg_internal Iclass_xt_iclass_call12_stateArgs[] = {
2731 static xtensa_arg_internal Iclass_xt_iclass_call8_args[] = {
2736 static xtensa_arg_internal Iclass_xt_iclass_call8_stateArgs[] = {
2740 static xtensa_arg_internal Iclass_xt_iclass_call4_args[] = {
2745 static xtensa_arg_internal Iclass_xt_iclass_call4_stateArgs[] = {
2749 static xtensa_arg_internal Iclass_xt_iclass_callx12_args[] = {
2754 static xtensa_arg_internal Iclass_xt_iclass_callx12_stateArgs[] = {
2758 static xtensa_arg_internal Iclass_xt_iclass_callx8_args[] = {
2763 static xtensa_arg_internal Iclass_xt_iclass_callx8_stateArgs[] = {
2767 static xtensa_arg_internal Iclass_xt_iclass_callx4_args[] = {
2772 static xtensa_arg_internal Iclass_xt_iclass_callx4_stateArgs[] = {
2776 static xtensa_arg_internal Iclass_xt_iclass_entry_args[] = {
2782 static xtensa_arg_internal Iclass_xt_iclass_entry_stateArgs[] = {
2790 static xtensa_arg_internal Iclass_xt_iclass_movsp_args[] = {
2795 static xtensa_arg_internal Iclass_xt_iclass_movsp_stateArgs[] = {
2800 static xtensa_arg_internal Iclass_xt_iclass_rotw_args[] = {
2804 static xtensa_arg_internal Iclass_xt_iclass_rotw_stateArgs[] = {
2808 static xtensa_arg_internal Iclass_xt_iclass_retw_args[] = {
2812 static xtensa_arg_internal Iclass_xt_iclass_retw_stateArgs[] = {
2820 static xtensa_arg_internal Iclass_xt_iclass_rfwou_stateArgs[] = {
2828 static xtensa_arg_internal Iclass_xt_iclass_l32e_args[] = {
2834 static xtensa_arg_internal Iclass_xt_iclass_s32e_args[] = {
2840 static xtensa_arg_internal Iclass_xt_iclass_rsr_windowbase_args[] = {
2844 static xtensa_arg_internal Iclass_xt_iclass_rsr_windowbase_stateArgs[] = {
2848 static xtensa_arg_internal Iclass_xt_iclass_wsr_windowbase_args[] = {
2852 static xtensa_arg_internal Iclass_xt_iclass_wsr_windowbase_stateArgs[] = {
2856 static xtensa_arg_internal Iclass_xt_iclass_xsr_windowbase_args[] = {
2860 static xtensa_arg_internal Iclass_xt_iclass_xsr_windowbase_stateArgs[] = {
2864 static xtensa_arg_internal Iclass_xt_iclass_rsr_windowstart_args[] = {
2868 static xtensa_arg_internal Iclass_xt_iclass_rsr_windowstart_stateArgs[] = {
2872 static xtensa_arg_internal Iclass_xt_iclass_wsr_windowstart_args[] = {
2876 static xtensa_arg_internal Iclass_xt_iclass_wsr_windowstart_stateArgs[] = {
2880 static xtensa_arg_internal Iclass_xt_iclass_xsr_windowstart_args[] = {
2884 static xtensa_arg_internal Iclass_xt_iclass_xsr_windowstart_stateArgs[] = {
2888 static xtensa_arg_internal Iclass_xt_iclass_add_n_args[] = {
2894 static xtensa_arg_internal Iclass_xt_iclass_addi_n_args[] = {
2900 static xtensa_arg_internal Iclass_xt_iclass_bz6_args[] = {
2905 static xtensa_arg_internal Iclass_xt_iclass_loadi4_args[] = {
2911 static xtensa_arg_internal Iclass_xt_iclass_mov_n_args[] = {
2916 static xtensa_arg_internal Iclass_xt_iclass_movi_n_args[] = {
2921 static xtensa_arg_internal Iclass_xt_iclass_retn_args[] = {
2925 static xtensa_arg_internal Iclass_xt_iclass_storei4_args[] = {
2931 static xtensa_arg_internal Iclass_xt_iclass_addi_args[] = {
2937 static xtensa_arg_internal Iclass_xt_iclass_addmi_args[] = {
2943 static xtensa_arg_internal Iclass_xt_iclass_addsub_args[] = {
2949 static xtensa_arg_internal Iclass_xt_iclass_bit_args[] = {
2955 static xtensa_arg_internal Iclass_xt_iclass_bsi8_args[] = {
2961 static xtensa_arg_internal Iclass_xt_iclass_bsi8b_args[] = {
2967 static xtensa_arg_internal Iclass_xt_iclass_bsi8u_args[] = {
2973 static xtensa_arg_internal Iclass_xt_iclass_bst8_args[] = {
2979 static xtensa_arg_internal Iclass_xt_iclass_bsz12_args[] = {
2984 static xtensa_arg_internal Iclass_xt_iclass_call0_args[] = {
2989 static xtensa_arg_internal Iclass_xt_iclass_callx0_args[] = {
2994 static xtensa_arg_internal Iclass_xt_iclass_exti_args[] = {
3001 static xtensa_arg_internal Iclass_xt_iclass_jump_args[] = {
3005 static xtensa_arg_internal Iclass_xt_iclass_jumpx_args[] = {
3009 static xtensa_arg_internal Iclass_xt_iclass_l16ui_args[] = {
3015 static xtensa_arg_internal Iclass_xt_iclass_l16si_args[] = {
3021 static xtensa_arg_internal Iclass_xt_iclass_l32i_args[] = {
3027 static xtensa_arg_internal Iclass_xt_iclass_l32r_args[] = {
3032 static xtensa_arg_internal Iclass_xt_iclass_l8i_args[] = {
3038 static xtensa_arg_internal Iclass_xt_iclass_movi_args[] = {
3043 static xtensa_arg_internal Iclass_xt_iclass_movz_args[] = {
3049 static xtensa_arg_internal Iclass_xt_iclass_neg_args[] = {
3054 static xtensa_arg_internal Iclass_xt_iclass_return_args[] = {
3058 static xtensa_arg_internal Iclass_xt_iclass_s16i_args[] = {
3064 static xtensa_arg_internal Iclass_xt_iclass_s32i_args[] = {
3070 static xtensa_arg_internal Iclass_xt_iclass_s32nb_args[] = {
3076 static xtensa_arg_internal Iclass_xt_iclass_s8i_args[] = {
3082 static xtensa_arg_internal Iclass_xt_iclass_sar_args[] = {
3086 static xtensa_arg_internal Iclass_xt_iclass_sar_stateArgs[] = {
3090 static xtensa_arg_internal Iclass_xt_iclass_sari_args[] = {
3094 static xtensa_arg_internal Iclass_xt_iclass_sari_stateArgs[] = {
3098 static xtensa_arg_internal Iclass_xt_iclass_shifts_args[] = {
3103 static xtensa_arg_internal Iclass_xt_iclass_shifts_stateArgs[] = {
3107 static xtensa_arg_internal Iclass_xt_iclass_shiftst_args[] = {
3113 static xtensa_arg_internal Iclass_xt_iclass_shiftst_stateArgs[] = {
3117 static xtensa_arg_internal Iclass_xt_iclass_shiftt_args[] = {
3122 static xtensa_arg_internal Iclass_xt_iclass_shiftt_stateArgs[] = {
3126 static xtensa_arg_internal Iclass_xt_iclass_slli_args[] = {
3132 static xtensa_arg_internal Iclass_xt_iclass_srai_args[] = {
3138 static xtensa_arg_internal Iclass_xt_iclass_srli_args[] = {
3144 static xtensa_arg_internal Iclass_xt_iclass_sync_stateArgs[] = {
3148 static xtensa_arg_internal Iclass_xt_iclass_rsil_args[] = {
3153 static xtensa_arg_internal Iclass_xt_iclass_rsil_stateArgs[] = {
3162 static xtensa_arg_internal Iclass_xt_iclass_rsr_sar_args[] = {
3166 static xtensa_arg_internal Iclass_xt_iclass_rsr_sar_stateArgs[] = {
3170 static xtensa_arg_internal Iclass_xt_iclass_wsr_sar_args[] = {
3174 static xtensa_arg_internal Iclass_xt_iclass_wsr_sar_stateArgs[] = {
3179 static xtensa_arg_internal Iclass_xt_iclass_xsr_sar_args[] = {
3183 static xtensa_arg_internal Iclass_xt_iclass_xsr_sar_stateArgs[] = {
3187 static xtensa_arg_internal Iclass_xt_iclass_rsr_memctl_args[] = {
3191 static xtensa_arg_internal Iclass_xt_iclass_wsr_memctl_args[] = {
3195 static xtensa_arg_internal Iclass_xt_iclass_xsr_memctl_args[] = {
3199 static xtensa_arg_internal Iclass_xt_iclass_rsr_litbase_args[] = {
3203 static xtensa_arg_internal Iclass_xt_iclass_wsr_litbase_args[] = {
3207 static xtensa_arg_internal Iclass_xt_iclass_xsr_litbase_args[] = {
3211 static xtensa_arg_internal Iclass_xt_iclass_rsr_configid0_args[] = {
3215 static xtensa_arg_internal Iclass_xt_iclass_wsr_configid0_args[] = {
3219 static xtensa_arg_internal Iclass_xt_iclass_rsr_configid1_args[] = {
3223 static xtensa_arg_internal Iclass_xt_iclass_rsr_ps_args[] = {
3227 static xtensa_arg_internal Iclass_xt_iclass_rsr_ps_stateArgs[] = {
3236 static xtensa_arg_internal Iclass_xt_iclass_wsr_ps_args[] = {
3240 static xtensa_arg_internal Iclass_xt_iclass_wsr_ps_stateArgs[] = {
3249 static xtensa_arg_internal Iclass_xt_iclass_xsr_ps_args[] = {
3253 static xtensa_arg_internal Iclass_xt_iclass_xsr_ps_stateArgs[] = {
3262 static xtensa_arg_internal Iclass_xt_iclass_rsr_epc1_args[] = {
3266 static xtensa_arg_internal Iclass_xt_iclass_rsr_epc1_stateArgs[] = {
3270 static xtensa_arg_internal Iclass_xt_iclass_wsr_epc1_args[] = {
3274 static xtensa_arg_internal Iclass_xt_iclass_wsr_epc1_stateArgs[] = {
3278 static xtensa_arg_internal Iclass_xt_iclass_xsr_epc1_args[] = {
3282 static xtensa_arg_internal Iclass_xt_iclass_xsr_epc1_stateArgs[] = {
3286 static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave1_args[] = {
3290 static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave1_stateArgs[] = {
3294 static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave1_args[] = {
3298 static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave1_stateArgs[] = {
3302 static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave1_args[] = {
3306 static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave1_stateArgs[] = {
3310 static xtensa_arg_internal Iclass_xt_iclass_rsr_epc2_args[] = {
3314 static xtensa_arg_internal Iclass_xt_iclass_rsr_epc2_stateArgs[] = {
3318 static xtensa_arg_internal Iclass_xt_iclass_wsr_epc2_args[] = {
3322 static xtensa_arg_internal Iclass_xt_iclass_wsr_epc2_stateArgs[] = {
3326 static xtensa_arg_internal Iclass_xt_iclass_xsr_epc2_args[] = {
3330 static xtensa_arg_internal Iclass_xt_iclass_xsr_epc2_stateArgs[] = {
3334 static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave2_args[] = {
3338 static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave2_stateArgs[] = {
3342 static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave2_args[] = {
3346 static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave2_stateArgs[] = {
3350 static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave2_args[] = {
3354 static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave2_stateArgs[] = {
3358 static xtensa_arg_internal Iclass_xt_iclass_rsr_epc3_args[] = {
3362 static xtensa_arg_internal Iclass_xt_iclass_rsr_epc3_stateArgs[] = {
3366 static xtensa_arg_internal Iclass_xt_iclass_wsr_epc3_args[] = {
3370 static xtensa_arg_internal Iclass_xt_iclass_wsr_epc3_stateArgs[] = {
3374 static xtensa_arg_internal Iclass_xt_iclass_xsr_epc3_args[] = {
3378 static xtensa_arg_internal Iclass_xt_iclass_xsr_epc3_stateArgs[] = {
3382 static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave3_args[] = {
3386 static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave3_stateArgs[] = {
3390 static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave3_args[] = {
3394 static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave3_stateArgs[] = {
3398 static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave3_args[] = {
3402 static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave3_stateArgs[] = {
3406 static xtensa_arg_internal Iclass_xt_iclass_rsr_epc4_args[] = {
3410 static xtensa_arg_internal Iclass_xt_iclass_rsr_epc4_stateArgs[] = {
3414 static xtensa_arg_internal Iclass_xt_iclass_wsr_epc4_args[] = {
3418 static xtensa_arg_internal Iclass_xt_iclass_wsr_epc4_stateArgs[] = {
3422 static xtensa_arg_internal Iclass_xt_iclass_xsr_epc4_args[] = {
3426 static xtensa_arg_internal Iclass_xt_iclass_xsr_epc4_stateArgs[] = {
3430 static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave4_args[] = {
3434 static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave4_stateArgs[] = {
3438 static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave4_args[] = {
3442 static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave4_stateArgs[] = {
3446 static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave4_args[] = {
3450 static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave4_stateArgs[] = {
3454 static xtensa_arg_internal Iclass_xt_iclass_rsr_epc5_args[] = {
3458 static xtensa_arg_internal Iclass_xt_iclass_rsr_epc5_stateArgs[] = {
3462 static xtensa_arg_internal Iclass_xt_iclass_wsr_epc5_args[] = {
3466 static xtensa_arg_internal Iclass_xt_iclass_wsr_epc5_stateArgs[] = {
3470 static xtensa_arg_internal Iclass_xt_iclass_xsr_epc5_args[] = {
3474 static xtensa_arg_internal Iclass_xt_iclass_xsr_epc5_stateArgs[] = {
3478 static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave5_args[] = {
3482 static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave5_stateArgs[] = {
3486 static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave5_args[] = {
3490 static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave5_stateArgs[] = {
3494 static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave5_args[] = {
3498 static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave5_stateArgs[] = {
3502 static xtensa_arg_internal Iclass_xt_iclass_rsr_epc6_args[] = {
3506 static xtensa_arg_internal Iclass_xt_iclass_rsr_epc6_stateArgs[] = {
3510 static xtensa_arg_internal Iclass_xt_iclass_wsr_epc6_args[] = {
3514 static xtensa_arg_internal Iclass_xt_iclass_wsr_epc6_stateArgs[] = {
3518 static xtensa_arg_internal Iclass_xt_iclass_xsr_epc6_args[] = {
3522 static xtensa_arg_internal Iclass_xt_iclass_xsr_epc6_stateArgs[] = {
3526 static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave6_args[] = {
3530 static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave6_stateArgs[] = {
3534 static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave6_args[] = {
3538 static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave6_stateArgs[] = {
3542 static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave6_args[] = {
3546 static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave6_stateArgs[] = {
3550 static xtensa_arg_internal Iclass_xt_iclass_rsr_epc7_args[] = {
3554 static xtensa_arg_internal Iclass_xt_iclass_rsr_epc7_stateArgs[] = {
3558 static xtensa_arg_internal Iclass_xt_iclass_wsr_epc7_args[] = {
3562 static xtensa_arg_internal Iclass_xt_iclass_wsr_epc7_stateArgs[] = {
3566 static xtensa_arg_internal Iclass_xt_iclass_xsr_epc7_args[] = {
3570 static xtensa_arg_internal Iclass_xt_iclass_xsr_epc7_stateArgs[] = {
3574 static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave7_args[] = {
3578 static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave7_stateArgs[] = {
3582 static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave7_args[] = {
3586 static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave7_stateArgs[] = {
3590 static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave7_args[] = {
3594 static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave7_stateArgs[] = {
3598 static xtensa_arg_internal Iclass_xt_iclass_rsr_eps2_args[] = {
3602 static xtensa_arg_internal Iclass_xt_iclass_rsr_eps2_stateArgs[] = {
3606 static xtensa_arg_internal Iclass_xt_iclass_wsr_eps2_args[] = {
3610 static xtensa_arg_internal Iclass_xt_iclass_wsr_eps2_stateArgs[] = {
3614 static xtensa_arg_internal Iclass_xt_iclass_xsr_eps2_args[] = {
3618 static xtensa_arg_internal Iclass_xt_iclass_xsr_eps2_stateArgs[] = {
3622 static xtensa_arg_internal Iclass_xt_iclass_rsr_eps3_args[] = {
3626 static xtensa_arg_internal Iclass_xt_iclass_rsr_eps3_stateArgs[] = {
3630 static xtensa_arg_internal Iclass_xt_iclass_wsr_eps3_args[] = {
3634 static xtensa_arg_internal Iclass_xt_iclass_wsr_eps3_stateArgs[] = {
3638 static xtensa_arg_internal Iclass_xt_iclass_xsr_eps3_args[] = {
3642 static xtensa_arg_internal Iclass_xt_iclass_xsr_eps3_stateArgs[] = {
3646 static xtensa_arg_internal Iclass_xt_iclass_rsr_eps4_args[] = {
3650 static xtensa_arg_internal Iclass_xt_iclass_rsr_eps4_stateArgs[] = {
3654 static xtensa_arg_internal Iclass_xt_iclass_wsr_eps4_args[] = {
3658 static xtensa_arg_internal Iclass_xt_iclass_wsr_eps4_stateArgs[] = {
3662 static xtensa_arg_internal Iclass_xt_iclass_xsr_eps4_args[] = {
3666 static xtensa_arg_internal Iclass_xt_iclass_xsr_eps4_stateArgs[] = {
3670 static xtensa_arg_internal Iclass_xt_iclass_rsr_eps5_args[] = {
3674 static xtensa_arg_internal Iclass_xt_iclass_rsr_eps5_stateArgs[] = {
3678 static xtensa_arg_internal Iclass_xt_iclass_wsr_eps5_args[] = {
3682 static xtensa_arg_internal Iclass_xt_iclass_wsr_eps5_stateArgs[] = {
3686 static xtensa_arg_internal Iclass_xt_iclass_xsr_eps5_args[] = {
3690 static xtensa_arg_internal Iclass_xt_iclass_xsr_eps5_stateArgs[] = {
3694 static xtensa_arg_internal Iclass_xt_iclass_rsr_eps6_args[] = {
3698 static xtensa_arg_internal Iclass_xt_iclass_rsr_eps6_stateArgs[] = {
3702 static xtensa_arg_internal Iclass_xt_iclass_wsr_eps6_args[] = {
3706 static xtensa_arg_internal Iclass_xt_iclass_wsr_eps6_stateArgs[] = {
3710 static xtensa_arg_internal Iclass_xt_iclass_xsr_eps6_args[] = {
3714 static xtensa_arg_internal Iclass_xt_iclass_xsr_eps6_stateArgs[] = {
3718 static xtensa_arg_internal Iclass_xt_iclass_rsr_eps7_args[] = {
3722 static xtensa_arg_internal Iclass_xt_iclass_rsr_eps7_stateArgs[] = {
3726 static xtensa_arg_internal Iclass_xt_iclass_wsr_eps7_args[] = {
3730 static xtensa_arg_internal Iclass_xt_iclass_wsr_eps7_stateArgs[] = {
3734 static xtensa_arg_internal Iclass_xt_iclass_xsr_eps7_args[] = {
3738 static xtensa_arg_internal Iclass_xt_iclass_xsr_eps7_stateArgs[] = {
3742 static xtensa_arg_internal Iclass_xt_iclass_rsr_excvaddr_args[] = {
3746 static xtensa_arg_internal Iclass_xt_iclass_rsr_excvaddr_stateArgs[] = {
3750 static xtensa_arg_internal Iclass_xt_iclass_wsr_excvaddr_args[] = {
3754 static xtensa_arg_internal Iclass_xt_iclass_wsr_excvaddr_stateArgs[] = {
3758 static xtensa_arg_internal Iclass_xt_iclass_xsr_excvaddr_args[] = {
3762 static xtensa_arg_internal Iclass_xt_iclass_xsr_excvaddr_stateArgs[] = {
3766 static xtensa_arg_internal Iclass_xt_iclass_rsr_depc_args[] = {
3770 static xtensa_arg_internal Iclass_xt_iclass_rsr_depc_stateArgs[] = {
3774 static xtensa_arg_internal Iclass_xt_iclass_wsr_depc_args[] = {
3778 static xtensa_arg_internal Iclass_xt_iclass_wsr_depc_stateArgs[] = {
3782 static xtensa_arg_internal Iclass_xt_iclass_xsr_depc_args[] = {
3786 static xtensa_arg_internal Iclass_xt_iclass_xsr_depc_stateArgs[] = {
3790 static xtensa_arg_internal Iclass_xt_iclass_rsr_exccause_args[] = {
3794 static xtensa_arg_internal Iclass_xt_iclass_rsr_exccause_stateArgs[] = {
3799 static xtensa_arg_internal Iclass_xt_iclass_wsr_exccause_args[] = {
3803 static xtensa_arg_internal Iclass_xt_iclass_wsr_exccause_stateArgs[] = {
3807 static xtensa_arg_internal Iclass_xt_iclass_xsr_exccause_args[] = {
3811 static xtensa_arg_internal Iclass_xt_iclass_xsr_exccause_stateArgs[] = {
3815 static xtensa_arg_internal Iclass_xt_iclass_rsr_misc0_args[] = {
3819 static xtensa_arg_internal Iclass_xt_iclass_rsr_misc0_stateArgs[] = {
3823 static xtensa_arg_internal Iclass_xt_iclass_wsr_misc0_args[] = {
3827 static xtensa_arg_internal Iclass_xt_iclass_wsr_misc0_stateArgs[] = {
3831 static xtensa_arg_internal Iclass_xt_iclass_xsr_misc0_args[] = {
3835 static xtensa_arg_internal Iclass_xt_iclass_xsr_misc0_stateArgs[] = {
3839 static xtensa_arg_internal Iclass_xt_iclass_rsr_misc1_args[] = {
3843 static xtensa_arg_internal Iclass_xt_iclass_rsr_misc1_stateArgs[] = {
3847 static xtensa_arg_internal Iclass_xt_iclass_wsr_misc1_args[] = {
3851 static xtensa_arg_internal Iclass_xt_iclass_wsr_misc1_stateArgs[] = {
3855 static xtensa_arg_internal Iclass_xt_iclass_xsr_misc1_args[] = {
3859 static xtensa_arg_internal Iclass_xt_iclass_xsr_misc1_stateArgs[] = {
3863 static xtensa_arg_internal Iclass_xt_iclass_rsr_prid_args[] = {
3867 static xtensa_arg_internal Iclass_xt_iclass_rsr_vecbase_args[] = {
3871 static xtensa_arg_internal Iclass_xt_iclass_rsr_vecbase_stateArgs[] = {
3875 static xtensa_arg_internal Iclass_xt_iclass_wsr_vecbase_args[] = {
3879 static xtensa_arg_internal Iclass_xt_iclass_wsr_vecbase_stateArgs[] = {
3883 static xtensa_arg_internal Iclass_xt_iclass_xsr_vecbase_args[] = {
3887 static xtensa_arg_internal Iclass_xt_iclass_xsr_vecbase_stateArgs[] = {
3891 static xtensa_arg_internal Iclass_xt_iclass_salt_args[] = {
3897 static xtensa_arg_internal Iclass_xt_mul16_args[] = {
3903 static xtensa_arg_internal Iclass_xt_mul32_args[] = {
3909 static xtensa_arg_internal Iclass_xt_iclass_rfi_args[] = {
3913 static xtensa_arg_internal Iclass_xt_iclass_rfi_stateArgs[] = {
3936 static xtensa_arg_internal Iclass_xt_iclass_wait_args[] = {
3940 static xtensa_arg_internal Iclass_xt_iclass_wait_stateArgs[] = {
3944 static xtensa_arg_internal Iclass_xt_iclass_rsr_interrupt_args[] = {
3948 static xtensa_arg_internal Iclass_xt_iclass_rsr_interrupt_stateArgs[] = {
3952 static xtensa_arg_internal Iclass_xt_iclass_wsr_intset_args[] = {
3956 static xtensa_arg_internal Iclass_xt_iclass_wsr_intset_stateArgs[] = {
3961 static xtensa_arg_internal Iclass_xt_iclass_wsr_intclear_args[] = {
3965 static xtensa_arg_internal Iclass_xt_iclass_wsr_intclear_stateArgs[] = {
3970 static xtensa_arg_internal Iclass_xt_iclass_rsr_intenable_args[] = {
3974 static xtensa_arg_internal Iclass_xt_iclass_rsr_intenable_stateArgs[] = {
3978 static xtensa_arg_internal Iclass_xt_iclass_wsr_intenable_args[] = {
3982 static xtensa_arg_internal Iclass_xt_iclass_wsr_intenable_stateArgs[] = {
3986 static xtensa_arg_internal Iclass_xt_iclass_xsr_intenable_args[] = {
3990 static xtensa_arg_internal Iclass_xt_iclass_xsr_intenable_stateArgs[] = {
3994 static xtensa_arg_internal Iclass_xt_iclass_break_args[] = {
3999 static xtensa_arg_internal Iclass_xt_iclass_break_stateArgs[] = {
4004 static xtensa_arg_internal Iclass_xt_iclass_break_n_args[] = {
4008 static xtensa_arg_internal Iclass_xt_iclass_break_n_stateArgs[] = {
4013 static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreaka0_args[] = {
4017 static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreaka0_stateArgs[] = {
4021 static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreaka0_args[] = {
4025 static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreaka0_stateArgs[] = {
4030 static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreaka0_args[] = {
4034 static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreaka0_stateArgs[] = {
4039 static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreakc0_args[] = {
4043 static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreakc0_stateArgs[] = {
4047 static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreakc0_args[] = {
4051 static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreakc0_stateArgs[] = {
4056 static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreakc0_args[] = {
4060 static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreakc0_stateArgs[] = {
4065 static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreaka1_args[] = {
4069 static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreaka1_stateArgs[] = {
4073 static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreaka1_args[] = {
4077 static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreaka1_stateArgs[] = {
4082 static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreaka1_args[] = {
4086 static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreaka1_stateArgs[] = {
4091 static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreakc1_args[] = {
4095 static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreakc1_stateArgs[] = {
4099 static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreakc1_args[] = {
4103 static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreakc1_stateArgs[] = {
4108 static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreakc1_args[] = {
4112 static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreakc1_stateArgs[] = {
4117 static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreaka0_args[] = {
4121 static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreaka0_stateArgs[] = {
4125 static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreaka0_args[] = {
4129 static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreaka0_stateArgs[] = {
4133 static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreaka0_args[] = {
4137 static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreaka0_stateArgs[] = {
4141 static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreaka1_args[] = {
4145 static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreaka1_stateArgs[] = {
4149 static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreaka1_args[] = {
4153 static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreaka1_stateArgs[] = {
4157 static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreaka1_args[] = {
4161 static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreaka1_stateArgs[] = {
4165 static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreakenable_args[] = {
4169 static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreakenable_stateArgs[] = {
4173 static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreakenable_args[] = {
4177 static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreakenable_stateArgs[] = {
4181 static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreakenable_args[] = {
4185 static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreakenable_stateArgs[] = {
4189 static xtensa_arg_internal Iclass_xt_iclass_rsr_debugcause_args[] = {
4193 static xtensa_arg_internal Iclass_xt_iclass_rsr_debugcause_stateArgs[] = {
4198 static xtensa_arg_internal Iclass_xt_iclass_wsr_debugcause_args[] = {
4202 static xtensa_arg_internal Iclass_xt_iclass_wsr_debugcause_stateArgs[] = {
4207 static xtensa_arg_internal Iclass_xt_iclass_xsr_debugcause_args[] = {
4211 static xtensa_arg_internal Iclass_xt_iclass_xsr_debugcause_stateArgs[] = {
4216 static xtensa_arg_internal Iclass_xt_iclass_rsr_icount_args[] = {
4220 static xtensa_arg_internal Iclass_xt_iclass_rsr_icount_stateArgs[] = {
4224 static xtensa_arg_internal Iclass_xt_iclass_wsr_icount_args[] = {
4228 static xtensa_arg_internal Iclass_xt_iclass_wsr_icount_stateArgs[] = {
4233 static xtensa_arg_internal Iclass_xt_iclass_xsr_icount_args[] = {
4237 static xtensa_arg_internal Iclass_xt_iclass_xsr_icount_stateArgs[] = {
4242 static xtensa_arg_internal Iclass_xt_iclass_rsr_icountlevel_args[] = {
4246 static xtensa_arg_internal Iclass_xt_iclass_rsr_icountlevel_stateArgs[] = {
4250 static xtensa_arg_internal Iclass_xt_iclass_wsr_icountlevel_args[] = {
4254 static xtensa_arg_internal Iclass_xt_iclass_wsr_icountlevel_stateArgs[] = {
4258 static xtensa_arg_internal Iclass_xt_iclass_xsr_icountlevel_args[] = {
4262 static xtensa_arg_internal Iclass_xt_iclass_xsr_icountlevel_stateArgs[] = {
4266 static xtensa_arg_internal Iclass_xt_iclass_rsr_ddr_args[] = {
4270 static xtensa_arg_internal Iclass_xt_iclass_rsr_ddr_stateArgs[] = {
4274 static xtensa_arg_internal Iclass_xt_iclass_wsr_ddr_args[] = {
4278 static xtensa_arg_internal Iclass_xt_iclass_wsr_ddr_stateArgs[] = {
4283 static xtensa_arg_internal Iclass_xt_iclass_xsr_ddr_args[] = {
4287 static xtensa_arg_internal Iclass_xt_iclass_xsr_ddr_stateArgs[] = {
4292 static xtensa_arg_internal Iclass_xt_iclass_lddr32_p_args[] = {
4296 static xtensa_arg_internal Iclass_xt_iclass_lddr32_p_stateArgs[] = {
4302 static xtensa_arg_internal Iclass_xt_iclass_sddr32_p_args[] = {
4306 static xtensa_arg_internal Iclass_xt_iclass_sddr32_p_stateArgs[] = {
4311 static xtensa_arg_internal Iclass_xt_iclass_rfdo_args[] = {
4315 static xtensa_arg_internal Iclass_xt_iclass_rfdo_stateArgs[] = {
4327 static xtensa_arg_internal Iclass_xt_iclass_rfdd_stateArgs[] = {
4331 static xtensa_arg_internal Iclass_xt_iclass_wsr_mmid_args[] = {
4335 static xtensa_arg_internal Iclass_xt_iclass_wsr_mmid_stateArgs[] = {
4339 static xtensa_arg_internal Iclass_xt_iclass_rsr_ccount_args[] = {
4343 static xtensa_arg_internal Iclass_xt_iclass_rsr_ccount_stateArgs[] = {
4347 static xtensa_arg_internal Iclass_xt_iclass_wsr_ccount_args[] = {
4351 static xtensa_arg_internal Iclass_xt_iclass_wsr_ccount_stateArgs[] = {
4356 static xtensa_arg_internal Iclass_xt_iclass_xsr_ccount_args[] = {
4360 static xtensa_arg_internal Iclass_xt_iclass_xsr_ccount_stateArgs[] = {
4365 static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare0_args[] = {
4369 static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare0_stateArgs[] = {
4373 static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare0_args[] = {
4377 static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare0_stateArgs[] = {
4382 static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare0_args[] = {
4386 static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare0_stateArgs[] = {
4391 static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare1_args[] = {
4395 static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare1_stateArgs[] = {
4399 static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare1_args[] = {
4403 static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare1_stateArgs[] = {
4408 static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare1_args[] = {
4412 static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare1_stateArgs[] = {
4417 static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare2_args[] = {
4421 static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare2_stateArgs[] = {
4425 static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare2_args[] = {
4429 static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare2_stateArgs[] = {
4434 static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare2_args[] = {
4438 static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare2_stateArgs[] = {
4443 static xtensa_arg_internal Iclass_xt_iclass_idtlb_args[] = {
4447 static xtensa_arg_internal Iclass_xt_iclass_idtlb_stateArgs[] = {
4451 static xtensa_arg_internal Iclass_xt_iclass_rdtlb_args[] = {
4456 static xtensa_arg_internal Iclass_xt_iclass_wdtlb_args[] = {
4461 static xtensa_arg_internal Iclass_xt_iclass_wdtlb_stateArgs[] = {
4465 static xtensa_arg_internal Iclass_xt_iclass_iitlb_args[] = {
4469 static xtensa_arg_internal Iclass_xt_iclass_ritlb_args[] = {
4474 static xtensa_arg_internal Iclass_xt_iclass_witlb_args[] = {
4479 static xtensa_arg_internal Iclass_xt_iclass_minmax_args[] = {
4485 static xtensa_arg_internal Iclass_xt_iclass_nsa_args[] = {
4490 static xtensa_arg_internal Iclass_xt_iclass_sx_args[] = {
4496 static xtensa_arg_internal Iclass_xt_iclass_l32ai_args[] = {
4502 static xtensa_arg_internal Iclass_xt_iclass_s32ri_args[] = {
4508 static xtensa_arg_internal Iclass_xt_iclass_s32c1i_args[] = {
4514 static xtensa_arg_internal Iclass_xt_iclass_s32c1i_stateArgs[] = {
4520 static xtensa_arg_internal Iclass_xt_iclass_rsr_scompare1_args[] = {
4524 static xtensa_arg_internal Iclass_xt_iclass_rsr_scompare1_stateArgs[] = {
4528 static xtensa_arg_internal Iclass_xt_iclass_wsr_scompare1_args[] = {
4532 static xtensa_arg_internal Iclass_xt_iclass_wsr_scompare1_stateArgs[] = {
4536 static xtensa_arg_internal Iclass_xt_iclass_xsr_scompare1_args[] = {
4540 static xtensa_arg_internal Iclass_xt_iclass_xsr_scompare1_stateArgs[] = {
4544 static xtensa_arg_internal Iclass_xt_iclass_rsr_atomctl_args[] = {
4548 static xtensa_arg_internal Iclass_xt_iclass_rsr_atomctl_stateArgs[] = {
4552 static xtensa_arg_internal Iclass_xt_iclass_wsr_atomctl_args[] = {
4556 static xtensa_arg_internal Iclass_xt_iclass_wsr_atomctl_stateArgs[] = {
4561 static xtensa_arg_internal Iclass_xt_iclass_xsr_atomctl_args[] = {
4565 static xtensa_arg_internal Iclass_xt_iclass_xsr_atomctl_stateArgs[] = {
4570 static xtensa_arg_internal Iclass_xt_iclass_div_args[] = {
4576 static xtensa_arg_internal Iclass_xt_iclass_rsr_eraccess_args[] = {
4580 static xtensa_arg_internal Iclass_xt_iclass_wsr_eraccess_args[] = {
4584 static xtensa_arg_internal Iclass_xt_iclass_xsr_eraccess_args[] = {
4588 static xtensa_arg_internal Iclass_xt_iclass_rer_args[] = {
4593 static xtensa_arg_internal Iclass_xt_iclass_wer_args[] = {
4598 static xtensa_arg_internal Iclass_rur_expstate_args[] = {
4602 static xtensa_arg_internal Iclass_rur_expstate_stateArgs[] = {
4606 static xtensa_arg_internal Iclass_wur_expstate_args[] = {
4610 static xtensa_arg_internal Iclass_wur_expstate_stateArgs[] = {
4614 static xtensa_arg_internal Iclass_iclass_READ_IMPWIRE_args[] = {
4622 static xtensa_arg_internal Iclass_iclass_SETB_EXPSTATE_args[] = {
4626 static xtensa_arg_internal Iclass_iclass_SETB_EXPSTATE_stateArgs[] = {
4630 static xtensa_arg_internal Iclass_iclass_CLRB_EXPSTATE_args[] = {
4634 static xtensa_arg_internal Iclass_iclass_CLRB_EXPSTATE_stateArgs[] = {
4638 static xtensa_arg_internal Iclass_iclass_WRMSK_EXPSTATE_args[] = {
4643 static xtensa_arg_internal Iclass_iclass_WRMSK_EXPSTATE_stateArgs[] = {