Lines Matching full:static

31 static xtensa_sysreg_internal sysregs[] = {
105 static xtensa_state_internal states[] = {
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1615 static xtensa_regfile_internal regfiles[] = {
1623 static xtensa_interface_internal interfaces[] = {
1645 static const unsigned CONST_TBL_ai4c_0[] = {
1666 static const unsigned CONST_TBL_b4c_0[] = {
1687 static const unsigned CONST_TBL_b4cu_0[] = {
1710 static int
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2747 static int
2754 static xtensa_operand_internal operands[] = {
3107 static xtensa_arg_internal Iclass_xt_iclass_rfe_stateArgs[] = {
3112 static xtensa_arg_internal Iclass_xt_iclass_rfde_stateArgs[] = {
3116 static xtensa_arg_internal Iclass_xt_iclass_call12_args[] = {
3121 static xtensa_arg_internal Iclass_xt_iclass_call12_stateArgs[] = {
3125 static xtensa_arg_internal Iclass_xt_iclass_call8_args[] = {
3130 static xtensa_arg_internal Iclass_xt_iclass_call8_stateArgs[] = {
3134 static xtensa_arg_internal Iclass_xt_iclass_call4_args[] = {
3139 static xtensa_arg_internal Iclass_xt_iclass_call4_stateArgs[] = {
3143 static xtensa_arg_internal Iclass_xt_iclass_callx12_args[] = {
3148 static xtensa_arg_internal Iclass_xt_iclass_callx12_stateArgs[] = {
3152 static xtensa_arg_internal Iclass_xt_iclass_callx8_args[] = {
3157 static xtensa_arg_internal Iclass_xt_iclass_callx8_stateArgs[] = {
3161 static xtensa_arg_internal Iclass_xt_iclass_callx4_args[] = {
3166 static xtensa_arg_internal Iclass_xt_iclass_callx4_stateArgs[] = {
3170 static xtensa_arg_internal Iclass_xt_iclass_entry_args[] = {
3176 static xtensa_arg_internal Iclass_xt_iclass_entry_stateArgs[] = {
3184 static xtensa_arg_internal Iclass_xt_iclass_movsp_args[] = {
3189 static xtensa_arg_internal Iclass_xt_iclass_movsp_stateArgs[] = {
3194 static xtensa_arg_internal Iclass_xt_iclass_rotw_args[] = {
3198 static xtensa_arg_internal Iclass_xt_iclass_rotw_stateArgs[] = {
3202 static xtensa_arg_internal Iclass_xt_iclass_retw_args[] = {
3206 static xtensa_arg_internal Iclass_xt_iclass_retw_stateArgs[] = {
3214 static xtensa_arg_internal Iclass_xt_iclass_rfwou_stateArgs[] = {
3222 static xtensa_arg_internal Iclass_xt_iclass_l32e_args[] = {
3228 static xtensa_arg_internal Iclass_xt_iclass_s32e_args[] = {
3234 static xtensa_arg_internal Iclass_xt_iclass_rsr_windowbase_args[] = {
3238 static xtensa_arg_internal Iclass_xt_iclass_rsr_windowbase_stateArgs[] = {
3242 static xtensa_arg_internal Iclass_xt_iclass_wsr_windowbase_args[] = {
3246 static xtensa_arg_internal Iclass_xt_iclass_wsr_windowbase_stateArgs[] = {
3250 static xtensa_arg_internal Iclass_xt_iclass_xsr_windowbase_args[] = {
3254 static xtensa_arg_internal Iclass_xt_iclass_xsr_windowbase_stateArgs[] = {
3258 static xtensa_arg_internal Iclass_xt_iclass_rsr_windowstart_args[] = {
3262 static xtensa_arg_internal Iclass_xt_iclass_rsr_windowstart_stateArgs[] = {
3266 static xtensa_arg_internal Iclass_xt_iclass_wsr_windowstart_args[] = {
3270 static xtensa_arg_internal Iclass_xt_iclass_wsr_windowstart_stateArgs[] = {
3274 static xtensa_arg_internal Iclass_xt_iclass_xsr_windowstart_args[] = {
3278 static xtensa_arg_internal Iclass_xt_iclass_xsr_windowstart_stateArgs[] = {
3282 static xtensa_arg_internal Iclass_xt_iclass_add_n_args[] = {
3288 static xtensa_arg_internal Iclass_xt_iclass_addi_n_args[] = {
3294 static xtensa_arg_internal Iclass_xt_iclass_bz6_args[] = {
3299 static xtensa_arg_internal Iclass_xt_iclass_loadi4_args[] = {
3305 static xtensa_arg_internal Iclass_xt_iclass_mov_n_args[] = {
3310 static xtensa_arg_internal Iclass_xt_iclass_movi_n_args[] = {
3315 static xtensa_arg_internal Iclass_xt_iclass_retn_args[] = {
3319 static xtensa_arg_internal Iclass_xt_iclass_storei4_args[] = {
3325 static xtensa_arg_internal Iclass_xt_iclass_addi_args[] = {
3331 static xtensa_arg_internal Iclass_xt_iclass_addmi_args[] = {
3337 static xtensa_arg_internal Iclass_xt_iclass_addsub_args[] = {
3343 static xtensa_arg_internal Iclass_xt_iclass_bit_args[] = {
3349 static xtensa_arg_internal Iclass_xt_iclass_bsi8_args[] = {
3355 static xtensa_arg_internal Iclass_xt_iclass_bsi8b_args[] = {
3361 static xtensa_arg_internal Iclass_xt_iclass_bsi8u_args[] = {
3367 static xtensa_arg_internal Iclass_xt_iclass_bst8_args[] = {
3373 static xtensa_arg_internal Iclass_xt_iclass_bsz12_args[] = {
3378 static xtensa_arg_internal Iclass_xt_iclass_call0_args[] = {
3383 static xtensa_arg_internal Iclass_xt_iclass_callx0_args[] = {
3388 static xtensa_arg_internal Iclass_xt_iclass_exti_args[] = {
3395 static xtensa_arg_internal Iclass_xt_iclass_jump_args[] = {
3399 static xtensa_arg_internal Iclass_xt_iclass_jumpx_args[] = {
3403 static xtensa_arg_internal Iclass_xt_iclass_l16ui_args[] = {
3409 static xtensa_arg_internal Iclass_xt_iclass_l16si_args[] = {
3415 static xtensa_arg_internal Iclass_xt_iclass_l32i_args[] = {
3421 static xtensa_arg_internal Iclass_xt_iclass_l32r_args[] = {
3426 static xtensa_arg_internal Iclass_xt_iclass_l8i_args[] = {
3432 static xtensa_arg_internal Iclass_xt_iclass_loop_args[] = {
3437 static xtensa_arg_internal Iclass_xt_iclass_loop_stateArgs[] = {
3443 static xtensa_arg_internal Iclass_xt_iclass_loopz_args[] = {
3448 static xtensa_arg_internal Iclass_xt_iclass_loopz_stateArgs[] = {
3454 static xtensa_arg_internal Iclass_xt_iclass_movi_args[] = {
3459 static xtensa_arg_internal Iclass_xt_iclass_movz_args[] = {
3465 static xtensa_arg_internal Iclass_xt_iclass_neg_args[] = {
3470 static xtensa_arg_internal Iclass_xt_iclass_return_args[] = {
3474 static xtensa_arg_internal Iclass_xt_iclass_s16i_args[] = {
3480 static xtensa_arg_internal Iclass_xt_iclass_s32i_args[] = {
3486 static xtensa_arg_internal Iclass_xt_iclass_s32nb_args[] = {
3492 static xtensa_arg_internal Iclass_xt_iclass_s8i_args[] = {
3498 static xtensa_arg_internal Iclass_xt_iclass_sar_args[] = {
3502 static xtensa_arg_internal Iclass_xt_iclass_sar_stateArgs[] = {
3506 static xtensa_arg_internal Iclass_xt_iclass_sari_args[] = {
3510 static xtensa_arg_internal Iclass_xt_iclass_sari_stateArgs[] = {
3514 static xtensa_arg_internal Iclass_xt_iclass_shifts_args[] = {
3519 static xtensa_arg_internal Iclass_xt_iclass_shifts_stateArgs[] = {
3523 static xtensa_arg_internal Iclass_xt_iclass_shiftst_args[] = {
3529 static xtensa_arg_internal Iclass_xt_iclass_shiftst_stateArgs[] = {
3533 static xtensa_arg_internal Iclass_xt_iclass_shiftt_args[] = {
3538 static xtensa_arg_internal Iclass_xt_iclass_shiftt_stateArgs[] = {
3542 static xtensa_arg_internal Iclass_xt_iclass_slli_args[] = {
3548 static xtensa_arg_internal Iclass_xt_iclass_srai_args[] = {
3554 static xtensa_arg_internal Iclass_xt_iclass_srli_args[] = {
3560 static xtensa_arg_internal Iclass_xt_iclass_sync_stateArgs[] = {
3564 static xtensa_arg_internal Iclass_xt_iclass_rsil_args[] = {
3569 static xtensa_arg_internal Iclass_xt_iclass_rsil_stateArgs[] = {
3578 static xtensa_arg_internal Iclass_xt_iclass_rsr_lend_args[] = {
3582 static xtensa_arg_internal Iclass_xt_iclass_rsr_lend_stateArgs[] = {
3586 static xtensa_arg_internal Iclass_xt_iclass_wsr_lend_args[] = {
3590 static xtensa_arg_internal Iclass_xt_iclass_wsr_lend_stateArgs[] = {
3594 static xtensa_arg_internal Iclass_xt_iclass_xsr_lend_args[] = {
3598 static xtensa_arg_internal Iclass_xt_iclass_xsr_lend_stateArgs[] = {
3602 static xtensa_arg_internal Iclass_xt_iclass_rsr_lcount_args[] = {
3606 static xtensa_arg_internal Iclass_xt_iclass_rsr_lcount_stateArgs[] = {
3610 static xtensa_arg_internal Iclass_xt_iclass_wsr_lcount_args[] = {
3614 static xtensa_arg_internal Iclass_xt_iclass_wsr_lcount_stateArgs[] = {
3619 static xtensa_arg_internal Iclass_xt_iclass_xsr_lcount_args[] = {
3623 static xtensa_arg_internal Iclass_xt_iclass_xsr_lcount_stateArgs[] = {
3628 static xtensa_arg_internal Iclass_xt_iclass_rsr_lbeg_args[] = {
3632 static xtensa_arg_internal Iclass_xt_iclass_rsr_lbeg_stateArgs[] = {
3636 static xtensa_arg_internal Iclass_xt_iclass_wsr_lbeg_args[] = {
3640 static xtensa_arg_internal Iclass_xt_iclass_wsr_lbeg_stateArgs[] = {
3644 static xtensa_arg_internal Iclass_xt_iclass_xsr_lbeg_args[] = {
3648 static xtensa_arg_internal Iclass_xt_iclass_xsr_lbeg_stateArgs[] = {
3652 static xtensa_arg_internal Iclass_xt_iclass_rsr_sar_args[] = {
3656 static xtensa_arg_internal Iclass_xt_iclass_rsr_sar_stateArgs[] = {
3660 static xtensa_arg_internal Iclass_xt_iclass_wsr_sar_args[] = {
3664 static xtensa_arg_internal Iclass_xt_iclass_wsr_sar_stateArgs[] = {
3669 static xtensa_arg_internal Iclass_xt_iclass_xsr_sar_args[] = {
3673 static xtensa_arg_internal Iclass_xt_iclass_xsr_sar_stateArgs[] = {
3677 static xtensa_arg_internal Iclass_xt_iclass_rsr_memctl_args[] = {
3681 static xtensa_arg_internal Iclass_xt_iclass_wsr_memctl_args[] = {
3685 static xtensa_arg_internal Iclass_xt_iclass_xsr_memctl_args[] = {
3689 static xtensa_arg_internal Iclass_xt_iclass_rsr_litbase_args[] = {
3693 static xtensa_arg_internal Iclass_xt_iclass_wsr_litbase_args[] = {
3697 static xtensa_arg_internal Iclass_xt_iclass_xsr_litbase_args[] = {
3701 static xtensa_arg_internal Iclass_xt_iclass_rsr_configid0_args[] = {
3705 static xtensa_arg_internal Iclass_xt_iclass_wsr_configid0_args[] = {
3709 static xtensa_arg_internal Iclass_xt_iclass_rsr_configid1_args[] = {
3713 static xtensa_arg_internal Iclass_xt_iclass_rsr_ps_args[] = {
3717 static xtensa_arg_internal Iclass_xt_iclass_rsr_ps_stateArgs[] = {
3726 static xtensa_arg_internal Iclass_xt_iclass_wsr_ps_args[] = {
3730 static xtensa_arg_internal Iclass_xt_iclass_wsr_ps_stateArgs[] = {
3739 static xtensa_arg_internal Iclass_xt_iclass_xsr_ps_args[] = {
3743 static xtensa_arg_internal Iclass_xt_iclass_xsr_ps_stateArgs[] = {
3752 static xtensa_arg_internal Iclass_xt_iclass_rsr_epc1_args[] = {
3756 static xtensa_arg_internal Iclass_xt_iclass_rsr_epc1_stateArgs[] = {
3760 static xtensa_arg_internal Iclass_xt_iclass_wsr_epc1_args[] = {
3764 static xtensa_arg_internal Iclass_xt_iclass_wsr_epc1_stateArgs[] = {
3768 static xtensa_arg_internal Iclass_xt_iclass_xsr_epc1_args[] = {
3772 static xtensa_arg_internal Iclass_xt_iclass_xsr_epc1_stateArgs[] = {
3776 static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave1_args[] = {
3780 static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave1_stateArgs[] = {
3784 static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave1_args[] = {
3788 static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave1_stateArgs[] = {
3792 static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave1_args[] = {
3796 static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave1_stateArgs[] = {
3800 static xtensa_arg_internal Iclass_xt_iclass_rsr_epc2_args[] = {
3804 static xtensa_arg_internal Iclass_xt_iclass_rsr_epc2_stateArgs[] = {
3808 static xtensa_arg_internal Iclass_xt_iclass_wsr_epc2_args[] = {
3812 static xtensa_arg_internal Iclass_xt_iclass_wsr_epc2_stateArgs[] = {
3816 static xtensa_arg_internal Iclass_xt_iclass_xsr_epc2_args[] = {
3820 static xtensa_arg_internal Iclass_xt_iclass_xsr_epc2_stateArgs[] = {
3824 static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave2_args[] = {
3828 static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave2_stateArgs[] = {
3832 static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave2_args[] = {
3836 static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave2_stateArgs[] = {
3840 static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave2_args[] = {
3844 static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave2_stateArgs[] = {
3848 static xtensa_arg_internal Iclass_xt_iclass_rsr_epc3_args[] = {
3852 static xtensa_arg_internal Iclass_xt_iclass_rsr_epc3_stateArgs[] = {
3856 static xtensa_arg_internal Iclass_xt_iclass_wsr_epc3_args[] = {
3860 static xtensa_arg_internal Iclass_xt_iclass_wsr_epc3_stateArgs[] = {
3864 static xtensa_arg_internal Iclass_xt_iclass_xsr_epc3_args[] = {
3868 static xtensa_arg_internal Iclass_xt_iclass_xsr_epc3_stateArgs[] = {
3872 static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave3_args[] = {
3876 static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave3_stateArgs[] = {
3880 static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave3_args[] = {
3884 static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave3_stateArgs[] = {
3888 static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave3_args[] = {
3892 static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave3_stateArgs[] = {
3896 static xtensa_arg_internal Iclass_xt_iclass_rsr_epc4_args[] = {
3900 static xtensa_arg_internal Iclass_xt_iclass_rsr_epc4_stateArgs[] = {
3904 static xtensa_arg_internal Iclass_xt_iclass_wsr_epc4_args[] = {
3908 static xtensa_arg_internal Iclass_xt_iclass_wsr_epc4_stateArgs[] = {
3912 static xtensa_arg_internal Iclass_xt_iclass_xsr_epc4_args[] = {
3916 static xtensa_arg_internal Iclass_xt_iclass_xsr_epc4_stateArgs[] = {
3920 static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave4_args[] = {
3924 static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave4_stateArgs[] = {
3928 static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave4_args[] = {
3932 static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave4_stateArgs[] = {
3936 static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave4_args[] = {
3940 static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave4_stateArgs[] = {
3944 static xtensa_arg_internal Iclass_xt_iclass_rsr_epc5_args[] = {
3948 static xtensa_arg_internal Iclass_xt_iclass_rsr_epc5_stateArgs[] = {
3952 static xtensa_arg_internal Iclass_xt_iclass_wsr_epc5_args[] = {
3956 static xtensa_arg_internal Iclass_xt_iclass_wsr_epc5_stateArgs[] = {
3960 static xtensa_arg_internal Iclass_xt_iclass_xsr_epc5_args[] = {
3964 static xtensa_arg_internal Iclass_xt_iclass_xsr_epc5_stateArgs[] = {
3968 static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave5_args[] = {
3972 static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave5_stateArgs[] = {
3976 static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave5_args[] = {
3980 static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave5_stateArgs[] = {
3984 static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave5_args[] = {
3988 static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave5_stateArgs[] = {
3992 static xtensa_arg_internal Iclass_xt_iclass_rsr_epc6_args[] = {
3996 static xtensa_arg_internal Iclass_xt_iclass_rsr_epc6_stateArgs[] = {
4000 static xtensa_arg_internal Iclass_xt_iclass_wsr_epc6_args[] = {
4004 static xtensa_arg_internal Iclass_xt_iclass_wsr_epc6_stateArgs[] = {
4008 static xtensa_arg_internal Iclass_xt_iclass_xsr_epc6_args[] = {
4012 static xtensa_arg_internal Iclass_xt_iclass_xsr_epc6_stateArgs[] = {
4016 static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave6_args[] = {
4020 static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave6_stateArgs[] = {
4024 static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave6_args[] = {
4028 static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave6_stateArgs[] = {
4032 static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave6_args[] = {
4036 static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave6_stateArgs[] = {
4040 static xtensa_arg_internal Iclass_xt_iclass_rsr_epc7_args[] = {
4044 static xtensa_arg_internal Iclass_xt_iclass_rsr_epc7_stateArgs[] = {
4048 static xtensa_arg_internal Iclass_xt_iclass_wsr_epc7_args[] = {
4052 static xtensa_arg_internal Iclass_xt_iclass_wsr_epc7_stateArgs[] = {
4056 static xtensa_arg_internal Iclass_xt_iclass_xsr_epc7_args[] = {
4060 static xtensa_arg_internal Iclass_xt_iclass_xsr_epc7_stateArgs[] = {
4064 static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave7_args[] = {
4068 static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave7_stateArgs[] = {
4072 static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave7_args[] = {
4076 static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave7_stateArgs[] = {
4080 static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave7_args[] = {
4084 static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave7_stateArgs[] = {
4088 static xtensa_arg_internal Iclass_xt_iclass_rsr_eps2_args[] = {
4092 static xtensa_arg_internal Iclass_xt_iclass_rsr_eps2_stateArgs[] = {
4096 static xtensa_arg_internal Iclass_xt_iclass_wsr_eps2_args[] = {
4100 static xtensa_arg_internal Iclass_xt_iclass_wsr_eps2_stateArgs[] = {
4104 static xtensa_arg_internal Iclass_xt_iclass_xsr_eps2_args[] = {
4108 static xtensa_arg_internal Iclass_xt_iclass_xsr_eps2_stateArgs[] = {
4112 static xtensa_arg_internal Iclass_xt_iclass_rsr_eps3_args[] = {
4116 static xtensa_arg_internal Iclass_xt_iclass_rsr_eps3_stateArgs[] = {
4120 static xtensa_arg_internal Iclass_xt_iclass_wsr_eps3_args[] = {
4124 static xtensa_arg_internal Iclass_xt_iclass_wsr_eps3_stateArgs[] = {
4128 static xtensa_arg_internal Iclass_xt_iclass_xsr_eps3_args[] = {
4132 static xtensa_arg_internal Iclass_xt_iclass_xsr_eps3_stateArgs[] = {
4136 static xtensa_arg_internal Iclass_xt_iclass_rsr_eps4_args[] = {
4140 static xtensa_arg_internal Iclass_xt_iclass_rsr_eps4_stateArgs[] = {
4144 static xtensa_arg_internal Iclass_xt_iclass_wsr_eps4_args[] = {
4148 static xtensa_arg_internal Iclass_xt_iclass_wsr_eps4_stateArgs[] = {
4152 static xtensa_arg_internal Iclass_xt_iclass_xsr_eps4_args[] = {
4156 static xtensa_arg_internal Iclass_xt_iclass_xsr_eps4_stateArgs[] = {
4160 static xtensa_arg_internal Iclass_xt_iclass_rsr_eps5_args[] = {
4164 static xtensa_arg_internal Iclass_xt_iclass_rsr_eps5_stateArgs[] = {
4168 static xtensa_arg_internal Iclass_xt_iclass_wsr_eps5_args[] = {
4172 static xtensa_arg_internal Iclass_xt_iclass_wsr_eps5_stateArgs[] = {
4176 static xtensa_arg_internal Iclass_xt_iclass_xsr_eps5_args[] = {
4180 static xtensa_arg_internal Iclass_xt_iclass_xsr_eps5_stateArgs[] = {
4184 static xtensa_arg_internal Iclass_xt_iclass_rsr_eps6_args[] = {
4188 static xtensa_arg_internal Iclass_xt_iclass_rsr_eps6_stateArgs[] = {
4192 static xtensa_arg_internal Iclass_xt_iclass_wsr_eps6_args[] = {
4196 static xtensa_arg_internal Iclass_xt_iclass_wsr_eps6_stateArgs[] = {
4200 static xtensa_arg_internal Iclass_xt_iclass_xsr_eps6_args[] = {
4204 static xtensa_arg_internal Iclass_xt_iclass_xsr_eps6_stateArgs[] = {
4208 static xtensa_arg_internal Iclass_xt_iclass_rsr_eps7_args[] = {
4212 static xtensa_arg_internal Iclass_xt_iclass_rsr_eps7_stateArgs[] = {
4216 static xtensa_arg_internal Iclass_xt_iclass_wsr_eps7_args[] = {
4220 static xtensa_arg_internal Iclass_xt_iclass_wsr_eps7_stateArgs[] = {
4224 static xtensa_arg_internal Iclass_xt_iclass_xsr_eps7_args[] = {
4228 static xtensa_arg_internal Iclass_xt_iclass_xsr_eps7_stateArgs[] = {
4232 static xtensa_arg_internal Iclass_xt_iclass_rsr_excvaddr_args[] = {
4236 static xtensa_arg_internal Iclass_xt_iclass_rsr_excvaddr_stateArgs[] = {
4240 static xtensa_arg_internal Iclass_xt_iclass_wsr_excvaddr_args[] = {
4244 static xtensa_arg_internal Iclass_xt_iclass_wsr_excvaddr_stateArgs[] = {
4248 static xtensa_arg_internal Iclass_xt_iclass_xsr_excvaddr_args[] = {
4252 static xtensa_arg_internal Iclass_xt_iclass_xsr_excvaddr_stateArgs[] = {
4256 static xtensa_arg_internal Iclass_xt_iclass_rsr_depc_args[] = {
4260 static xtensa_arg_internal Iclass_xt_iclass_rsr_depc_stateArgs[] = {
4264 static xtensa_arg_internal Iclass_xt_iclass_wsr_depc_args[] = {
4268 static xtensa_arg_internal Iclass_xt_iclass_wsr_depc_stateArgs[] = {
4272 static xtensa_arg_internal Iclass_xt_iclass_xsr_depc_args[] = {
4276 static xtensa_arg_internal Iclass_xt_iclass_xsr_depc_stateArgs[] = {
4280 static xtensa_arg_internal Iclass_xt_iclass_rsr_exccause_args[] = {
4284 static xtensa_arg_internal Iclass_xt_iclass_rsr_exccause_stateArgs[] = {
4289 static xtensa_arg_internal Iclass_xt_iclass_wsr_exccause_args[] = {
4293 static xtensa_arg_internal Iclass_xt_iclass_wsr_exccause_stateArgs[] = {
4297 static xtensa_arg_internal Iclass_xt_iclass_xsr_exccause_args[] = {
4301 static xtensa_arg_internal Iclass_xt_iclass_xsr_exccause_stateArgs[] = {
4305 static xtensa_arg_internal Iclass_xt_iclass_rsr_misc0_args[] = {
4309 static xtensa_arg_internal Iclass_xt_iclass_rsr_misc0_stateArgs[] = {
4313 static xtensa_arg_internal Iclass_xt_iclass_wsr_misc0_args[] = {
4317 static xtensa_arg_internal Iclass_xt_iclass_wsr_misc0_stateArgs[] = {
4321 static xtensa_arg_internal Iclass_xt_iclass_xsr_misc0_args[] = {
4325 static xtensa_arg_internal Iclass_xt_iclass_xsr_misc0_stateArgs[] = {
4329 static xtensa_arg_internal Iclass_xt_iclass_rsr_misc1_args[] = {
4333 static xtensa_arg_internal Iclass_xt_iclass_rsr_misc1_stateArgs[] = {
4337 static xtensa_arg_internal Iclass_xt_iclass_wsr_misc1_args[] = {
4341 static xtensa_arg_internal Iclass_xt_iclass_wsr_misc1_stateArgs[] = {
4345 static xtensa_arg_internal Iclass_xt_iclass_xsr_misc1_args[] = {
4349 static xtensa_arg_internal Iclass_xt_iclass_xsr_misc1_stateArgs[] = {
4353 static xtensa_arg_internal Iclass_xt_iclass_rsr_prid_args[] = {
4357 static xtensa_arg_internal Iclass_xt_iclass_rsr_vecbase_args[] = {
4361 static xtensa_arg_internal Iclass_xt_iclass_rsr_vecbase_stateArgs[] = {
4365 static xtensa_arg_internal Iclass_xt_iclass_wsr_vecbase_args[] = {
4369 static xtensa_arg_internal Iclass_xt_iclass_wsr_vecbase_stateArgs[] = {
4373 static xtensa_arg_internal Iclass_xt_iclass_xsr_vecbase_args[] = {
4377 static xtensa_arg_internal Iclass_xt_iclass_xsr_vecbase_stateArgs[] = {
4381 static xtensa_arg_internal Iclass_xt_mul16_args[] = {
4387 static xtensa_arg_internal Iclass_xt_mul32_args[] = {
4393 static xtensa_arg_internal Iclass_xt_iclass_mac16_aa_args[] = {
4398 static xtensa_arg_internal Iclass_xt_iclass_mac16_aa_stateArgs[] = {
4402 static xtensa_arg_internal Iclass_xt_iclass_mac16_ad_args[] = {
4407 static xtensa_arg_internal Iclass_xt_iclass_mac16_ad_stateArgs[] = {
4411 static xtensa_arg_internal Iclass_xt_iclass_mac16_da_args[] = {
4416 static xtensa_arg_internal Iclass_xt_iclass_mac16_da_stateArgs[] = {
4420 static xtensa_arg_internal Iclass_xt_iclass_mac16_dd_args[] = {
4425 static xtensa_arg_internal Iclass_xt_iclass_mac16_dd_stateArgs[] = {
4429 static xtensa_arg_internal Iclass_xt_iclass_mac16a_aa_args[] = {
4434 static xtensa_arg_internal Iclass_xt_iclass_mac16a_aa_stateArgs[] = {
4438 static xtensa_arg_internal Iclass_xt_iclass_mac16a_ad_args[] = {
4443 static xtensa_arg_internal Iclass_xt_iclass_mac16a_ad_stateArgs[] = {
4447 static xtensa_arg_internal Iclass_xt_iclass_mac16a_da_args[] = {
4452 static xtensa_arg_internal Iclass_xt_iclass_mac16a_da_stateArgs[] = {
4456 static xtensa_arg_internal Iclass_xt_iclass_mac16a_dd_args[] = {
4461 static xtensa_arg_internal Iclass_xt_iclass_mac16a_dd_stateArgs[] = {
4465 static xtensa_arg_internal Iclass_xt_iclass_mac16al_da_args[] = {
4472 static xtensa_arg_internal Iclass_xt_iclass_mac16al_da_stateArgs[] = {
4476 static xtensa_arg_internal Iclass_xt_iclass_mac16al_dd_args[] = {
4483 static xtensa_arg_internal Iclass_xt_iclass_mac16al_dd_stateArgs[] = {
4487 static xtensa_arg_internal Iclass_xt_iclass_mac16_l_args[] = {
4492 static xtensa_arg_internal Iclass_xt_iclass_rsr_m0_args[] = {
4497 static xtensa_arg_internal Iclass_xt_iclass_wsr_m0_args[] = {
4502 static xtensa_arg_internal Iclass_xt_iclass_xsr_m0_args[] = {
4507 static xtensa_arg_internal Iclass_xt_iclass_rsr_m1_args[] = {
4512 static xtensa_arg_internal Iclass_xt_iclass_wsr_m1_args[] = {
4517 static xtensa_arg_internal Iclass_xt_iclass_xsr_m1_args[] = {
4522 static xtensa_arg_internal Iclass_xt_iclass_rsr_m2_args[] = {
4527 static xtensa_arg_internal Iclass_xt_iclass_wsr_m2_args[] = {
4532 static xtensa_arg_internal Iclass_xt_iclass_xsr_m2_args[] = {
4537 static xtensa_arg_internal Iclass_xt_iclass_rsr_m3_args[] = {
4542 static xtensa_arg_internal Iclass_xt_iclass_wsr_m3_args[] = {
4547 static xtensa_arg_internal Iclass_xt_iclass_xsr_m3_args[] = {
4552 static xtensa_arg_internal Iclass_xt_iclass_rsr_acclo_args[] = {
4556 static xtensa_arg_internal Iclass_xt_iclass_rsr_acclo_stateArgs[] = {
4560 static xtensa_arg_internal Iclass_xt_iclass_wsr_acclo_args[] = {
4564 static xtensa_arg_internal Iclass_xt_iclass_wsr_acclo_stateArgs[] = {
4568 static xtensa_arg_internal Iclass_xt_iclass_xsr_acclo_args[] = {
4572 static xtensa_arg_internal Iclass_xt_iclass_xsr_acclo_stateArgs[] = {
4576 static xtensa_arg_internal Iclass_xt_iclass_rsr_acchi_args[] = {
4580 static xtensa_arg_internal Iclass_xt_iclass_rsr_acchi_stateArgs[] = {
4584 static xtensa_arg_internal Iclass_xt_iclass_wsr_acchi_args[] = {
4588 static xtensa_arg_internal Iclass_xt_iclass_wsr_acchi_stateArgs[] = {
4592 static xtensa_arg_internal Iclass_xt_iclass_xsr_acchi_args[] = {
4596 static xtensa_arg_internal Iclass_xt_iclass_xsr_acchi_stateArgs[] = {
4600 static xtensa_arg_internal Iclass_xt_iclass_rfi_args[] = {
4604 static xtensa_arg_internal Iclass_xt_iclass_rfi_stateArgs[] = {
4627 static xtensa_arg_internal Iclass_xt_iclass_wait_args[] = {
4631 static xtensa_arg_internal Iclass_xt_iclass_wait_stateArgs[] = {
4635 static xtensa_arg_internal Iclass_xt_iclass_rsr_interrupt_args[] = {
4639 static xtensa_arg_internal Iclass_xt_iclass_rsr_interrupt_stateArgs[] = {
4643 static xtensa_arg_internal Iclass_xt_iclass_wsr_intset_args[] = {
4647 static xtensa_arg_internal Iclass_xt_iclass_wsr_intset_stateArgs[] = {
4652 static xtensa_arg_internal Iclass_xt_iclass_wsr_intclear_args[] = {
4656 static xtensa_arg_internal Iclass_xt_iclass_wsr_intclear_stateArgs[] = {
4661 static xtensa_arg_internal Iclass_xt_iclass_rsr_intenable_args[] = {
4665 static xtensa_arg_internal Iclass_xt_iclass_rsr_intenable_stateArgs[] = {
4669 static xtensa_arg_internal Iclass_xt_iclass_wsr_intenable_args[] = {
4673 static xtensa_arg_internal Iclass_xt_iclass_wsr_intenable_stateArgs[] = {
4677 static xtensa_arg_internal Iclass_xt_iclass_xsr_intenable_args[] = {
4681 static xtensa_arg_internal Iclass_xt_iclass_xsr_intenable_stateArgs[] = {
4685 static xtensa_arg_internal Iclass_xt_iclass_break_args[] = {
4690 static xtensa_arg_internal Iclass_xt_iclass_break_stateArgs[] = {
4695 static xtensa_arg_internal Iclass_xt_iclass_break_n_args[] = {
4699 static xtensa_arg_internal Iclass_xt_iclass_break_n_stateArgs[] = {
4704 static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreaka0_args[] = {
4708 static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreaka0_stateArgs[] = {
4712 static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreaka0_args[] = {
4716 static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreaka0_stateArgs[] = {
4721 static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreaka0_args[] = {
4725 static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreaka0_stateArgs[] = {
4730 static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreakc0_args[] = {
4734 static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreakc0_stateArgs[] = {
4738 static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreakc0_args[] = {
4742 static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreakc0_stateArgs[] = {
4747 static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreakc0_args[] = {
4751 static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreakc0_stateArgs[] = {
4756 static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreaka1_args[] = {
4760 static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreaka1_stateArgs[] = {
4764 static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreaka1_args[] = {
4768 static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreaka1_stateArgs[] = {
4773 static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreaka1_args[] = {
4777 static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreaka1_stateArgs[] = {
4782 static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreakc1_args[] = {
4786 static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreakc1_stateArgs[] = {
4790 static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreakc1_args[] = {
4794 static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreakc1_stateArgs[] = {
4799 static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreakc1_args[] = {
4803 static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreakc1_stateArgs[] = {
4808 static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreaka0_args[] = {
4812 static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreaka0_stateArgs[] = {
4816 static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreaka0_args[] = {
4820 static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreaka0_stateArgs[] = {
4824 static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreaka0_args[] = {
4828 static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreaka0_stateArgs[] = {
4832 static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreaka1_args[] = {
4836 static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreaka1_stateArgs[] = {
4840 static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreaka1_args[] = {
4844 static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreaka1_stateArgs[] = {
4848 static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreaka1_args[] = {
4852 static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreaka1_stateArgs[] = {
4856 static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreakenable_args[] = {
4860 static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreakenable_stateArgs[] = {
4864 static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreakenable_args[] = {
4868 static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreakenable_stateArgs[] = {
4872 static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreakenable_args[] = {
4876 static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreakenable_stateArgs[] = {
4880 static xtensa_arg_internal Iclass_xt_iclass_rsr_debugcause_args[] = {
4884 static xtensa_arg_internal Iclass_xt_iclass_rsr_debugcause_stateArgs[] = {
4889 static xtensa_arg_internal Iclass_xt_iclass_wsr_debugcause_args[] = {
4893 static xtensa_arg_internal Iclass_xt_iclass_wsr_debugcause_stateArgs[] = {
4898 static xtensa_arg_internal Iclass_xt_iclass_xsr_debugcause_args[] = {
4902 static xtensa_arg_internal Iclass_xt_iclass_xsr_debugcause_stateArgs[] = {
4907 static xtensa_arg_internal Iclass_xt_iclass_rsr_icount_args[] = {
4911 static xtensa_arg_internal Iclass_xt_iclass_rsr_icount_stateArgs[] = {
4915 static xtensa_arg_internal Iclass_xt_iclass_wsr_icount_args[] = {
4919 static xtensa_arg_internal Iclass_xt_iclass_wsr_icount_stateArgs[] = {
4924 static xtensa_arg_internal Iclass_xt_iclass_xsr_icount_args[] = {
4928 static xtensa_arg_internal Iclass_xt_iclass_xsr_icount_stateArgs[] = {
4933 static xtensa_arg_internal Iclass_xt_iclass_rsr_icountlevel_args[] = {
4937 static xtensa_arg_internal Iclass_xt_iclass_rsr_icountlevel_stateArgs[] = {
4941 static xtensa_arg_internal Iclass_xt_iclass_wsr_icountlevel_args[] = {
4945 static xtensa_arg_internal Iclass_xt_iclass_wsr_icountlevel_stateArgs[] = {
4949 static xtensa_arg_internal Iclass_xt_iclass_xsr_icountlevel_args[] = {
4953 static xtensa_arg_internal Iclass_xt_iclass_xsr_icountlevel_stateArgs[] = {
4957 static xtensa_arg_internal Iclass_xt_iclass_rsr_ddr_args[] = {
4961 static xtensa_arg_internal Iclass_xt_iclass_rsr_ddr_stateArgs[] = {
4965 static xtensa_arg_internal Iclass_xt_iclass_wsr_ddr_args[] = {
4969 static xtensa_arg_internal Iclass_xt_iclass_wsr_ddr_stateArgs[] = {
4974 static xtensa_arg_internal Iclass_xt_iclass_xsr_ddr_args[] = {
4978 static xtensa_arg_internal Iclass_xt_iclass_xsr_ddr_stateArgs[] = {
4983 static xtensa_arg_internal Iclass_xt_iclass_lddr32_p_args[] = {
4987 static xtensa_arg_internal Iclass_xt_iclass_lddr32_p_stateArgs[] = {
4993 static xtensa_arg_internal Iclass_xt_iclass_sddr32_p_args[] = {
4997 static xtensa_arg_internal Iclass_xt_iclass_sddr32_p_stateArgs[] = {
5002 static xtensa_arg_internal Iclass_xt_iclass_rfdo_args[] = {
5006 static xtensa_arg_internal Iclass_xt_iclass_rfdo_stateArgs[] = {
5018 static xtensa_arg_internal Iclass_xt_iclass_rfdd_stateArgs[] = {
5022 static xtensa_arg_internal Iclass_xt_iclass_wsr_mmid_args[] = {
5026 static xtensa_arg_internal Iclass_xt_iclass_wsr_mmid_stateArgs[] = {
5030 static xtensa_arg_internal Iclass_xt_iclass_rsr_ccount_args[] = {
5034 static xtensa_arg_internal Iclass_xt_iclass_rsr_ccount_stateArgs[] = {
5038 static xtensa_arg_internal Iclass_xt_iclass_wsr_ccount_args[] = {
5042 static xtensa_arg_internal Iclass_xt_iclass_wsr_ccount_stateArgs[] = {
5047 static xtensa_arg_internal Iclass_xt_iclass_xsr_ccount_args[] = {
5051 static xtensa_arg_internal Iclass_xt_iclass_xsr_ccount_stateArgs[] = {
5056 static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare0_args[] = {
5060 static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare0_stateArgs[] = {
5064 static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare0_args[] = {
5068 static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare0_stateArgs[] = {
5073 static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare0_args[] = {
5077 static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare0_stateArgs[] = {
5082 static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare1_args[] = {
5086 static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare1_stateArgs[] = {
5090 static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare1_args[] = {
5094 static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare1_stateArgs[] = {
5099 static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare1_args[] = {
5103 static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare1_stateArgs[] = {
5108 static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare2_args[] = {
5112 static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare2_stateArgs[] = {
5116 static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare2_args[] = {
5120 static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare2_stateArgs[] = {
5125 static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare2_args[] = {
5129 static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare2_stateArgs[] = {
5134 static xtensa_arg_internal Iclass_xt_iclass_icache_args[] = {
5139 static xtensa_arg_internal Iclass_xt_iclass_icache_lock_args[] = {
5144 static xtensa_arg_internal Iclass_xt_iclass_icache_inv_args[] = {
5149 static xtensa_arg_internal Iclass_xt_iclass_licx_args[] = {
5154 static xtensa_arg_internal Iclass_xt_iclass_sicx_args[] = {
5159 static xtensa_arg_internal Iclass_xt_iclass_dcache_args[] = {
5164 static xtensa_arg_internal Iclass_xt_iclass_dcache_dyn_args[] = {
5168 static xtensa_arg_internal Iclass_xt_iclass_dcache_ind_args[] = {
5173 static xtensa_arg_internal Iclass_xt_iclass_dcache_inv_args[] = {
5178 static xtensa_arg_internal Iclass_xt_iclass_dpf_args[] = {
5183 static xtensa_arg_internal Iclass_xt_iclass_dcache_lock_args[] = {
5188 static xtensa_arg_internal Iclass_xt_iclass_sdct_args[] = {
5193 static xtensa_arg_internal Iclass_xt_iclass_ldct_args[] = {
5198 static xtensa_arg_internal Iclass_xt_iclass_idtlb_args[] = {
5202 static xtensa_arg_internal Iclass_xt_iclass_idtlb_stateArgs[] = {
5206 static xtensa_arg_internal Iclass_xt_iclass_rdtlb_args[] = {
5211 static xtensa_arg_internal Iclass_xt_iclass_wdtlb_args[] = {
5216 static xtensa_arg_internal Iclass_xt_iclass_wdtlb_stateArgs[] = {
5220 static xtensa_arg_internal Iclass_xt_iclass_iitlb_args[] = {
5224 static xtensa_arg_internal Iclass_xt_iclass_ritlb_args[] = {
5229 static xtensa_arg_internal Iclass_xt_iclass_witlb_args[] = {
5234 static xtensa_arg_internal Iclass_xt_iclass_clamp_args[] = {
5240 static xtensa_arg_internal Iclass_xt_iclass_minmax_args[] = {
5246 static xtensa_arg_internal Iclass_xt_iclass_nsa_args[] = {
5251 static xtensa_arg_internal Iclass_xt_iclass_sx_args[] = {
5257 static xtensa_arg_internal Iclass_xt_iclass_l32ai_args[] = {
5263 static xtensa_arg_internal Iclass_xt_iclass_s32ri_args[] = {
5269 static xtensa_arg_internal Iclass_xt_iclass_s32c1i_args[] = {
5275 static xtensa_arg_internal Iclass_xt_iclass_s32c1i_stateArgs[] = {
5281 static xtensa_arg_internal Iclass_xt_iclass_rsr_scompare1_args[] = {
5285 static xtensa_arg_internal Iclass_xt_iclass_rsr_scompare1_stateArgs[] = {
5289 static xtensa_arg_internal Iclass_xt_iclass_wsr_scompare1_args[] = {
5293 static xtensa_arg_internal Iclass_xt_iclass_wsr_scompare1_stateArgs[] = {
5297 static xtensa_arg_internal Iclass_xt_iclass_xsr_scompare1_args[] = {
5301 static xtensa_arg_internal Iclass_xt_iclass_xsr_scompare1_stateArgs[] = {
5305 static xtensa_arg_internal Iclass_xt_iclass_rsr_atomctl_args[] = {
5309 static xtensa_arg_internal Iclass_xt_iclass_rsr_atomctl_stateArgs[] = {
5313 static xtensa_arg_internal Iclass_xt_iclass_wsr_atomctl_args[] = {
5317 static xtensa_arg_internal Iclass_xt_iclass_wsr_atomctl_stateArgs[] = {
5322 static xtensa_arg_internal Iclass_xt_iclass_xsr_atomctl_args[] = {
5326 static xtensa_arg_internal Iclass_xt_iclass_xsr_atomctl_stateArgs[] = {
5331 static xtensa_arg_internal Iclass_xt_iclass_div_args[] = {
5337 static xtensa_arg_internal Iclass_xt_iclass_rer_args[] = {
5342 static xtensa_arg_internal Iclass_xt_iclass_rer_stateArgs[] = {
5346 static xtensa_interface Iclass_xt_iclass_rer_intfArgs[] = {
5351 static xtensa_arg_internal Iclass_xt_iclass_wer_args[] = {
5356 static xtensa_arg_internal Iclass_xt_iclass_wer_stateArgs[] = {
5360 static xtensa_interface Iclass_xt_iclass_wer_intfArgs[] = {
5365 static xtensa_arg_internal Iclass_rur_expstate_args[] = {
5369 static xtensa_arg_internal Iclass_rur_expstate_stateArgs[] = {
5373 static xtensa_arg_internal Iclass_wur_expstate_args[] = {
5377 static xtensa_arg_internal Iclass_wur_expstate_stateArgs[] = {
5381 static xtensa_arg_internal Iclass_iclass_READ_IMPWIRE_args[] = {
5385 static xtensa_interface Iclass_iclass_READ_IMPWIRE_intfArgs[] = {
5389 static xtensa_arg_internal Iclass_iclass_SETB_EXPSTATE_args[] = {
5393 static xtensa_arg_internal Iclass_iclass_SETB_EXPSTATE_stateArgs[] = {
5397 static xtensa_arg_internal Iclass_iclass_CLRB_EXPSTATE_args[] = {
5401 static xtensa_arg_internal Iclass_iclass_CLRB_EXPSTATE_stateArgs[] = {
5405 static xtensa_arg_internal Iclass_iclass_WRMSK_EXPSTATE_args[] = {
5410 static xtensa_arg_internal Iclass_iclass_WRMSK_EXPSTATE_stateArgs[] = {
5414 static xtensa_iclass_internal iclasses[] = {
6362 static void
6368 static void
6374 static void
6380 static void
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7646 static void
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7670 static void
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7682 static void
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7790 static void
7796 static void
7802 static void
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8288 static void
8294 static void
8300 static void
8306 static void
8312 static void
8318 static void
8324 static void
8330 static void
8336 static void
8342 static void
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8360 static void
8366 static void
8372 static void
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8402 static void
8408 static void
8414 static void
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8426 static void
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8444 static void
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8798 static void
8804 static void
8810 static void
8816 static void
8822 static void
8828 static void
8834 static void
8840 static void
8846 static void
8852 static void
8858 static void
8864 static void
8870 static void
8876 static void
8882 static void
8888 static void
8894 static void
8900 static void
8906 static void
8912 static void
8918 static void
8924 static void
8930 static void
8936 static void
8942 static void
8948 static void
8954 static void
8960 static void
8966 static void
8972 static void
8978 static void
8984 static void
8990 static void
8996 static xtensa_opcode_encode_fn Opcode_excw_encode_fns[] = {
9000 static xtensa_opcode_encode_fn Opcode_rfe_encode_fns[] = {
9004 static xtensa_opcode_encode_fn Opcode_rfde_encode_fns[] = {
9008 static xtensa_opcode_encode_fn Opcode_syscall_encode_fns[] = {
9012 static xtensa_opcode_encode_fn Opcode_call12_encode_fns[] = {
9016 static xtensa_opcode_encode_fn Opcode_call8_encode_fns[] = {
9020 static xtensa_opcode_encode_fn Opcode_call4_encode_fns[] = {
9024 static xtensa_opcode_encode_fn Opcode_callx12_encode_fns[] = {
9028 static xtensa_opcode_encode_fn Opcode_callx8_encode_fns[] = {
9032 static xtensa_opcode_encode_fn Opcode_callx4_encode_fns[] = {
9036 static xtensa_opcode_encode_fn Opcode_entry_encode_fns[] = {
9040 static xtensa_opcode_encode_fn Opcode_movsp_encode_fns[] = {
9044 static xtensa_opcode_encode_fn Opcode_rotw_encode_fns[] = {
9048 static xtensa_opcode_encode_fn Opcode_retw_encode_fns[] = {
9052 static xtensa_opcode_encode_fn Opcode_retw_n_encode_fns[] = {
9056 static xtensa_opcode_encode_fn Opcode_rfwo_encode_fns[] = {
9060 static xtensa_opcode_encode_fn Opcode_rfwu_encode_fns[] = {
9064 static xtensa_opcode_encode_fn Opcode_l32e_encode_fns[] = {
9068 static xtensa_opcode_encode_fn Opcode_s32e_encode_fns[] = {
9072 static xtensa_opcode_encode_fn Opcode_rsr_windowbase_encode_fns[] = {
9076 static xtensa_opcode_encode_fn Opcode_wsr_windowbase_encode_fns[] = {
9080 static xtensa_opcode_encode_fn Opcode_xsr_windowbase_encode_fns[] = {
9084 static xtensa_opcode_encode_fn Opcode_rsr_windowstart_encode_fns[] = {
9088 static xtensa_opcode_encode_fn Opcode_wsr_windowstart_encode_fns[] = {
9092 static xtensa_opcode_encode_fn Opcode_xsr_windowstart_encode_fns[] = {
9096 static xtensa_opcode_encode_fn Opcode_add_n_encode_fns[] = {
9100 static xtensa_opcode_encode_fn Opcode_addi_n_encode_fns[] = {
9104 static xtensa_opcode_encode_fn Opcode_beqz_n_encode_fns[] = {
9108 static xtensa_opcode_encode_fn Opcode_bnez_n_encode_fns[] = {
9112 static xtensa_opcode_encode_fn Opcode_ill_n_encode_fns[] = {
9116 static xtensa_opcode_encode_fn Opcode_l32i_n_encode_fns[] = {
9120 static xtensa_opcode_encode_fn Opcode_mov_n_encode_fns[] = {
9124 static xtensa_opcode_encode_fn Opcode_movi_n_encode_fns[] = {
9128 static xtensa_opcode_encode_fn Opcode_nop_n_encode_fns[] = {
9132 static xtensa_opcode_encode_fn Opcode_ret_n_encode_fns[] = {
9136 static xtensa_opcode_encode_fn Opcode_s32i_n_encode_fns[] = {
9140 static xtensa_opcode_encode_fn Opcode_addi_encode_fns[] = {
9144 static xtensa_opcode_encode_fn Opcode_addmi_encode_fns[] = {
9148 static xtensa_opcode_encode_fn Opcode_add_encode_fns[] = {
9152 static xtensa_opcode_encode_fn Opcode_sub_encode_fns[] = {
9156 static xtensa_opcode_encode_fn Opcode_addx2_encode_fns[] = {
9160 static xtensa_opcode_encode_fn Opcode_addx4_encode_fns[] = {
9164 static xtensa_opcode_encode_fn Opcode_addx8_encode_fns[] = {
9168 static xtensa_opcode_encode_fn Opcode_subx2_encode_fns[] = {
9172 static xtensa_opcode_encode_fn Opcode_subx4_encode_fns[] = {
9176 static xtensa_opcode_encode_fn Opcode_subx8_encode_fns[] = {
9180 static xtensa_opcode_encode_fn Opcode_and_encode_fns[] = {
9184 static xtensa_opcode_encode_fn Opcode_or_encode_fns[] = {
9188 static xtensa_opcode_encode_fn Opcode_xor_encode_fns[] = {
9192 static xtensa_opcode_encode_fn Opcode_beqi_encode_fns[] = {
9196 static xtensa_opcode_encode_fn Opcode_bnei_encode_fns[] = {
9200 static xtensa_opcode_encode_fn Opcode_bgei_encode_fns[] = {
9204 static xtensa_opcode_encode_fn Opcode_blti_encode_fns[] = {
9208 static xtensa_opcode_encode_fn Opcode_bbci_encode_fns[] = {
9212 static xtensa_opcode_encode_fn Opcode_bbsi_encode_fns[] = {
9216 static xtensa_opcode_encode_fn Opcode_bgeui_encode_fns[] = {
9220 static xtensa_opcode_encode_fn Opcode_bltui_encode_fns[] = {
9224 static xtensa_opcode_encode_fn Opcode_beq_encode_fns[] = {
9228 static xtensa_opcode_encode_fn Opcode_bne_encode_fns[] = {
9232 static xtensa_opcode_encode_fn Opcode_bge_encode_fns[] = {
9236 static xtensa_opcode_encode_fn Opcode_blt_encode_fns[] = {
9240 static xtensa_opcode_encode_fn Opcode_bgeu_encode_fns[] = {
9244 static xtensa_opcode_encode_fn Opcode_bltu_encode_fns[] = {
9248 static xtensa_opcode_encode_fn Opcode_bany_encode_fns[] = {
9252 static xtensa_opcode_encode_fn Opcode_bnone_encode_fns[] = {
9256 static xtensa_opcode_encode_fn Opcode_ball_encode_fns[] = {
9260 static xtensa_opcode_encode_fn Opcode_bnall_encode_fns[] = {
9264 static xtensa_opcode_encode_fn Opcode_bbc_encode_fns[] = {
9268 static xtensa_opcode_encode_fn Opcode_bbs_encode_fns[] = {
9272 static xtensa_opcode_encode_fn Opcode_beqz_encode_fns[] = {
9276 static xtensa_opcode_encode_fn Opcode_bnez_encode_fns[] = {
9280 static xtensa_opcode_encode_fn Opcode_bgez_encode_fns[] = {
9284 static xtensa_opcode_encode_fn Opcode_bltz_encode_fns[] = {
9288 static xtensa_opcode_encode_fn Opcode_call0_encode_fns[] = {
9292 static xtensa_opcode_encode_fn Opcode_callx0_encode_fns[] = {
9296 static xtensa_opcode_encode_fn Opcode_extui_encode_fns[] = {
9300 static xtensa_opcode_encode_fn Opcode_ill_encode_fns[] = {
9304 static xtensa_opcode_encode_fn Opcode_j_encode_fns[] = {
9308 static xtensa_opcode_encode_fn Opcode_jx_encode_fns[] = {
9312 static xtensa_opcode_encode_fn Opcode_l16ui_encode_fns[] = {
9316 static xtensa_opcode_encode_fn Opcode_l16si_encode_fns[] = {
9320 static xtensa_opcode_encode_fn Opcode_l32i_encode_fns[] = {
9324 static xtensa_opcode_encode_fn Opcode_l32r_encode_fns[] = {
9328 static xtensa_opcode_encode_fn Opcode_l8ui_encode_fns[] = {
9332 static xtensa_opcode_encode_fn Opcode_loop_encode_fns[] = {
9336 static xtensa_opcode_encode_fn Opcode_loopnez_encode_fns[] = {
9340 static xtensa_opcode_encode_fn Opcode_loopgtz_encode_fns[] = {
9344 static xtensa_opcode_encode_fn Opcode_movi_encode_fns[] = {
9348 static xtensa_opcode_encode_fn Opcode_moveqz_encode_fns[] = {
9352 static xtensa_opcode_encode_fn Opcode_movnez_encode_fns[] = {
9356 static xtensa_opcode_encode_fn Opcode_movltz_encode_fns[] = {
9360 static xtensa_opcode_encode_fn Opcode_movgez_encode_fns[] = {
9364 static xtensa_opcode_encode_fn Opcode_neg_encode_fns[] = {
9368 static xtensa_opcode_encode_fn Opcode_abs_encode_fns[] = {
9372 static xtensa_opcode_encode_fn Opcode_nop_encode_fns[] = {
9376 static xtensa_opcode_encode_fn Opcode_ret_encode_fns[] = {
9380 static xtensa_opcode_encode_fn Opcode_simcall_encode_fns[] = {
9384 static xtensa_opcode_encode_fn Opcode_s16i_encode_fns[] = {
9388 static xtensa_opcode_encode_fn Opcode_s32i_encode_fns[] = {
9392 static xtensa_opcode_encode_fn Opcode_s32nb_encode_fns[] = {
9396 static xtensa_opcode_encode_fn Opcode_s8i_encode_fns[] = {
9400 static xtensa_opcode_encode_fn Opcode_ssr_encode_fns[] = {
9404 static xtensa_opcode_encode_fn Opcode_ssl_encode_fns[] = {
9408 static xtensa_opcode_encode_fn Opcode_ssa8l_encode_fns[] = {
9412 static xtensa_opcode_encode_fn Opcode_ssa8b_encode_fns[] = {
9416 static xtensa_opcode_encode_fn Opcode_ssai_encode_fns[] = {
9420 static xtensa_opcode_encode_fn Opcode_sll_encode_fns[] = {
9424 static xtensa_opcode_encode_fn Opcode_src_encode_fns[] = {
9428 static xtensa_opcode_encode_fn Opcode_srl_encode_fns[] = {
9432 static xtensa_opcode_encode_fn Opcode_sra_encode_fns[] = {
9436 static xtensa_opcode_encode_fn Opcode_slli_encode_fns[] = {
9440 static xtensa_opcode_encode_fn Opcode_srai_encode_fns[] = {
9444 static xtensa_opcode_encode_fn Opcode_srli_encode_fns[] = {
9448 static xtensa_opcode_encode_fn Opcode_memw_encode_fns[] = {
9452 static xtensa_opcode_encode_fn Opcode_extw_encode_fns[] = {
9456 static xtensa_opcode_encode_fn Opcode_isync_encode_fns[] = {
9460 static xtensa_opcode_encode_fn Opcode_rsync_encode_fns[] = {
9464 static xtensa_opcode_encode_fn Opcode_esync_encode_fns[] = {
9468 static xtensa_opcode_encode_fn Opcode_dsync_encode_fns[] = {
9472 static xtensa_opcode_encode_fn Opcode_rsil_encode_fns[] = {
9476 static xtensa_opcode_encode_fn Opcode_rsr_lend_encode_fns[] = {
9480 static xtensa_opcode_encode_fn Opcode_wsr_lend_encode_fns[] = {
9484 static xtensa_opcode_encode_fn Opcode_xsr_lend_encode_fns[] = {
9488 static xtensa_opcode_encode_fn Opcode_rsr_lcount_encode_fns[] = {
9492 static xtensa_opcode_encode_fn Opcode_wsr_lcount_encode_fns[] = {
9496 static xtensa_opcode_encode_fn Opcode_xsr_lcount_encode_fns[] = {
9500 static xtensa_opcode_encode_fn Opcode_rsr_lbeg_encode_fns[] = {
9504 static xtensa_opcode_encode_fn Opcode_wsr_lbeg_encode_fns[] = {
9508 static xtensa_opcode_encode_fn Opcode_xsr_lbeg_encode_fns[] = {
9512 static xtensa_opcode_encode_fn Opcode_rsr_sar_encode_fns[] = {
9516 static xtensa_opcode_encode_fn Opcode_wsr_sar_encode_fns[] = {
9520 static xtensa_opcode_encode_fn Opcode_xsr_sar_encode_fns[] = {
9524 static xtensa_opcode_encode_fn Opcode_rsr_memctl_encode_fns[] = {
9528 static xtensa_opcode_encode_fn Opcode_wsr_memctl_encode_fns[] = {
9532 static xtensa_opcode_encode_fn Opcode_xsr_memctl_encode_fns[] = {
9536 static xtensa_opcode_encode_fn Opcode_rsr_litbase_encode_fns[] = {
9540 static xtensa_opcode_encode_fn Opcode_wsr_litbase_encode_fns[] = {
9544 static xtensa_opcode_encode_fn Opcode_xsr_litbase_encode_fns[] = {
9548 static xtensa_opcode_encode_fn Opcode_rsr_configid0_encode_fns[] = {
9552 static xtensa_opcode_encode_fn Opcode_wsr_configid0_encode_fns[] = {
9556 static xtensa_opcode_encode_fn Opcode_rsr_configid1_encode_fns[] = {
9560 static xtensa_opcode_encode_fn Opcode_rsr_ps_encode_fns[] = {
9564 static xtensa_opcode_encode_fn Opcode_wsr_ps_encode_fns[] = {
9568 static xtensa_opcode_encode_fn Opcode_xsr_ps_encode_fns[] = {
9572 static xtensa_opcode_encode_fn Opcode_rsr_epc1_encode_fns[] = {
9576 static xtensa_opcode_encode_fn Opcode_wsr_epc1_encode_fns[] = {
9580 static xtensa_opcode_encode_fn Opcode_xsr_epc1_encode_fns[] = {
9584 static xtensa_opcode_encode_fn Opcode_rsr_excsave1_encode_fns[] = {
9588 static xtensa_opcode_encode_fn Opcode_wsr_excsave1_encode_fns[] = {
9592 static xtensa_opcode_encode_fn Opcode_xsr_excsave1_encode_fns[] = {
9596 static xtensa_opcode_encode_fn Opcode_rsr_epc2_encode_fns[] = {
9600 static xtensa_opcode_encode_fn Opcode_wsr_epc2_encode_fns[] = {
9604 static xtensa_opcode_encode_fn Opcode_xsr_epc2_encode_fns[] = {
9608 static xtensa_opcode_encode_fn Opcode_rsr_excsave2_encode_fns[] = {
9612 static xtensa_opcode_encode_fn Opcode_wsr_excsave2_encode_fns[] = {
9616 static xtensa_opcode_encode_fn Opcode_xsr_excsave2_encode_fns[] = {
9620 static xtensa_opcode_encode_fn Opcode_rsr_epc3_encode_fns[] = {
9624 static xtensa_opcode_encode_fn Opcode_wsr_epc3_encode_fns[] = {
9628 static xtensa_opcode_encode_fn Opcode_xsr_epc3_encode_fns[] = {
9632 static xtensa_opcode_encode_fn Opcode_rsr_excsave3_encode_fns[] = {
9636 static xtensa_opcode_encode_fn Opcode_wsr_excsave3_encode_fns[] = {
9640 static xtensa_opcode_encode_fn Opcode_xsr_excsave3_encode_fns[] = {
9644 static xtensa_opcode_encode_fn Opcode_rsr_epc4_encode_fns[] = {
9648 static xtensa_opcode_encode_fn Opcode_wsr_epc4_encode_fns[] = {
9652 static xtensa_opcode_encode_fn Opcode_xsr_epc4_encode_fns[] = {
9656 static xtensa_opcode_encode_fn Opcode_rsr_excsave4_encode_fns[] = {
9660 static xtensa_opcode_encode_fn Opcode_wsr_excsave4_encode_fns[] = {
9664 static xtensa_opcode_encode_fn Opcode_xsr_excsave4_encode_fns[] = {
9668 static xtensa_opcode_encode_fn Opcode_rsr_epc5_encode_fns[] = {
9672 static xtensa_opcode_encode_fn Opcode_wsr_epc5_encode_fns[] = {
9676 static xtensa_opcode_encode_fn Opcode_xsr_epc5_encode_fns[] = {
9680 static xtensa_opcode_encode_fn Opcode_rsr_excsave5_encode_fns[] = {
9684 static xtensa_opcode_encode_fn Opcode_wsr_excsave5_encode_fns[] = {
9688 static xtensa_opcode_encode_fn Opcode_xsr_excsave5_encode_fns[] = {
9692 static xtensa_opcode_encode_fn Opcode_rsr_epc6_encode_fns[] = {
9696 static xtensa_opcode_encode_fn Opcode_wsr_epc6_encode_fns[] = {
9700 static xtensa_opcode_encode_fn Opcode_xsr_epc6_encode_fns[] = {
9704 static xtensa_opcode_encode_fn Opcode_rsr_excsave6_encode_fns[] = {
9708 static xtensa_opcode_encode_fn Opcode_wsr_excsave6_encode_fns[] = {
9712 static xtensa_opcode_encode_fn Opcode_xsr_excsave6_encode_fns[] = {
9716 static xtensa_opcode_encode_fn Opcode_rsr_epc7_encode_fns[] = {
9720 static xtensa_opcode_encode_fn Opcode_wsr_epc7_encode_fns[] = {
9724 static xtensa_opcode_encode_fn Opcode_xsr_epc7_encode_fns[] = {
9728 static xtensa_opcode_encode_fn Opcode_rsr_excsave7_encode_fns[] = {
9732 static xtensa_opcode_encode_fn Opcode_wsr_excsave7_encode_fns[] = {
9736 static xtensa_opcode_encode_fn Opcode_xsr_excsave7_encode_fns[] = {
9740 static xtensa_opcode_encode_fn Opcode_rsr_eps2_encode_fns[] = {
9744 static xtensa_opcode_encode_fn Opcode_wsr_eps2_encode_fns[] = {
9748 static xtensa_opcode_encode_fn Opcode_xsr_eps2_encode_fns[] = {
9752 static xtensa_opcode_encode_fn Opcode_rsr_eps3_encode_fns[] = {
9756 static xtensa_opcode_encode_fn Opcode_wsr_eps3_encode_fns[] = {
9760 static xtensa_opcode_encode_fn Opcode_xsr_eps3_encode_fns[] = {
9764 static xtensa_opcode_encode_fn Opcode_rsr_eps4_encode_fns[] = {
9768 static xtensa_opcode_encode_fn Opcode_wsr_eps4_encode_fns[] = {
9772 static xtensa_opcode_encode_fn Opcode_xsr_eps4_encode_fns[] = {
9776 static xtensa_opcode_encode_fn Opcode_rsr_eps5_encode_fns[] = {
9780 static xtensa_opcode_encode_fn Opcode_wsr_eps5_encode_fns[] = {
9784 static xtensa_opcode_encode_fn Opcode_xsr_eps5_encode_fns[] = {
9788 static xtensa_opcode_encode_fn Opcode_rsr_eps6_encode_fns[] = {
9792 static xtensa_opcode_encode_fn Opcode_wsr_eps6_encode_fns[] = {
9796 static xtensa_opcode_encode_fn Opcode_xsr_eps6_encode_fns[] = {
9800 static xtensa_opcode_encode_fn Opcode_rsr_eps7_encode_fns[] = {
9804 static xtensa_opcode_encode_fn Opcode_wsr_eps7_encode_fns[] = {
9808 static xtensa_opcode_encode_fn Opcode_xsr_eps7_encode_fns[] = {
9812 static xtensa_opcode_encode_fn Opcode_rsr_excvaddr_encode_fns[] = {
9816 static xtensa_opcode_encode_fn Opcode_wsr_excvaddr_encode_fns[] = {
9820 static xtensa_opcode_encode_fn Opcode_xsr_excvaddr_encode_fns[] = {
9824 static xtensa_opcode_encode_fn Opcode_rsr_depc_encode_fns[] = {
9828 static xtensa_opcode_encode_fn Opcode_wsr_depc_encode_fns[] = {
9832 static xtensa_opcode_encode_fn Opcode_xsr_depc_encode_fns[] = {
9836 static xtensa_opcode_encode_fn Opcode_rsr_exccause_encode_fns[] = {
9840 static xtensa_opcode_encode_fn Opcode_wsr_exccause_encode_fns[] = {
9844 static xtensa_opcode_encode_fn Opcode_xsr_exccause_encode_fns[] = {
9848 static xtensa_opcode_encode_fn Opcode_rsr_misc0_encode_fns[] = {
9852 static xtensa_opcode_encode_fn Opcode_wsr_misc0_encode_fns[] = {
9856 static xtensa_opcode_encode_fn Opcode_xsr_misc0_encode_fns[] = {
9860 static xtensa_opcode_encode_fn Opcode_rsr_misc1_encode_fns[] = {
9864 static xtensa_opcode_encode_fn Opcode_wsr_misc1_encode_fns[] = {
9868 static xtensa_opcode_encode_fn Opcode_xsr_misc1_encode_fns[] = {
9872 static xtensa_opcode_encode_fn Opcode_rsr_prid_encode_fns[] = {
9876 static xtensa_opcode_encode_fn Opcode_rsr_vecbase_encode_fns[] = {
9880 static xtensa_opcode_encode_fn Opcode_wsr_vecbase_encode_fns[] = {
9884 static xtensa_opcode_encode_fn Opcode_xsr_vecbase_encode_fns[] = {
9888 static xtensa_opcode_encode_fn Opcode_mul16u_encode_fns[] = {
9892 static xtensa_opcode_encode_fn Opcode_mul16s_encode_fns[] = {
9896 static xtensa_opcode_encode_fn Opcode_mull_encode_fns[] = {
9900 static xtensa_opcode_encode_fn Opcode_mul_aa_ll_encode_fns[] = {
9904 static xtensa_opcode_encode_fn Opcode_mul_aa_hl_encode_fns[] = {
9908 static xtensa_opcode_encode_fn Opcode_mul_aa_lh_encode_fns[] = {
9912 static xtensa_opcode_encode_fn Opcode_mul_aa_hh_encode_fns[] = {
9916 static xtensa_opcode_encode_fn Opcode_umul_aa_ll_encode_fns[] = {
9920 static xtensa_opcode_encode_fn Opcode_umul_aa_hl_encode_fns[] = {
9924 static xtensa_opcode_encode_fn Opcode_umul_aa_lh_encode_fns[] = {
9928 static xtensa_opcode_encode_fn Opcode_umul_aa_hh_encode_fns[] = {
9932 static xtensa_opcode_encode_fn Opcode_mul_ad_ll_encode_fns[] = {
9936 static xtensa_opcode_encode_fn Opcode_mul_ad_hl_encode_fns[] = {
9940 static xtensa_opcode_encode_fn Opcode_mul_ad_lh_encode_fns[] = {
9944 static xtensa_opcode_encode_fn Opcode_mul_ad_hh_encode_fns[] = {
9948 static xtensa_opcode_encode_fn Opcode_mul_da_ll_encode_fns[] = {
9952 static xtensa_opcode_encode_fn Opcode_mul_da_hl_encode_fns[] = {
9956 static xtensa_opcode_encode_fn Opcode_mul_da_lh_encode_fns[] = {
9960 static xtensa_opcode_encode_fn Opcode_mul_da_hh_encode_fns[] = {
9964 static xtensa_opcode_encode_fn Opcode_mul_dd_ll_encode_fns[] = {
9968 static xtensa_opcode_encode_fn Opcode_mul_dd_hl_encode_fns[] = {
9972 static xtensa_opcode_encode_fn Opcode_mul_dd_lh_encode_fns[] = {
9976 static xtensa_opcode_encode_fn Opcode_mul_dd_hh_encode_fns[] = {
9980 static xtensa_opcode_encode_fn Opcode_mula_aa_ll_encode_fns[] = {
9984 static xtensa_opcode_encode_fn Opcode_mula_aa_hl_encode_fns[] = {
9988 static xtensa_opcode_encode_fn Opcode_mula_aa_lh_encode_fns[] = {
9992 static xtensa_opcode_encode_fn Opcode_mula_aa_hh_encode_fns[] = {
9996 static xtensa_opcode_encode_fn Opcode_muls_aa_ll_encode_fns[] = {
10000 static xtensa_opcode_encode_fn Opcode_muls_aa_hl_encode_fns[] = {
10004 static xtensa_opcode_encode_fn Opcode_muls_aa_lh_encode_fns[] = {
10008 static xtensa_opcode_encode_fn Opcode_muls_aa_hh_encode_fns[] = {
10012 static xtensa_opcode_encode_fn Opcode_mula_ad_ll_encode_fns[] = {
10016 static xtensa_opcode_encode_fn Opcode_mula_ad_hl_encode_fns[] = {
10020 static xtensa_opcode_encode_fn Opcode_mula_ad_lh_encode_fns[] = {
10024 static xtensa_opcode_encode_fn Opcode_mula_ad_hh_encode_fns[] = {
10028 static xtensa_opcode_encode_fn Opcode_muls_ad_ll_encode_fns[] = {
10032 static xtensa_opcode_encode_fn Opcode_muls_ad_hl_encode_fns[] = {
10036 static xtensa_opcode_encode_fn Opcode_muls_ad_lh_encode_fns[] = {
10040 static xtensa_opcode_encode_fn Opcode_muls_ad_hh_encode_fns[] = {
10044 static xtensa_opcode_encode_fn Opcode_mula_da_ll_encode_fns[] = {
10048 static xtensa_opcode_encode_fn Opcode_mula_da_hl_encode_fns[] = {
10052 static xtensa_opcode_encode_fn Opcode_mula_da_lh_encode_fns[] = {
10056 static xtensa_opcode_encode_fn Opcode_mula_da_hh_encode_fns[] = {
10060 static xtensa_opcode_encode_fn Opcode_muls_da_ll_encode_fns[] = {
10064 static xtensa_opcode_encode_fn Opcode_muls_da_hl_encode_fns[] = {
10068 static xtensa_opcode_encode_fn Opcode_muls_da_lh_encode_fns[] = {
10072 static xtensa_opcode_encode_fn Opcode_muls_da_hh_encode_fns[] = {
10076 static xtensa_opcode_encode_fn Opcode_mula_dd_ll_encode_fns[] = {
10080 static xtensa_opcode_encode_fn Opcode_mula_dd_hl_encode_fns[] = {
10084 static xtensa_opcode_encode_fn Opcode_mula_dd_lh_encode_fns[] = {
10088 static xtensa_opcode_encode_fn Opcode_mula_dd_hh_encode_fns[] = {
10092 static xtensa_opcode_encode_fn Opcode_muls_dd_ll_encode_fns[] = {
10096 static xtensa_opcode_encode_fn Opcode_muls_dd_hl_encode_fns[] = {
10100 static xtensa_opcode_encode_fn Opcode_muls_dd_lh_encode_fns[] = {
10104 static xtensa_opcode_encode_fn Opcode_muls_dd_hh_encode_fns[] = {
10108 static xtensa_opcode_encode_fn Opcode_mula_da_ll_lddec_encode_fns[] = {
10112 static xtensa_opcode_encode_fn Opcode_mula_da_ll_ldinc_encode_fns[] = {
10116 static xtensa_opcode_encode_fn Opcode_mula_da_hl_lddec_encode_fns[] = {
10120 static xtensa_opcode_encode_fn Opcode_mula_da_hl_ldinc_encode_fns[] = {
10124 static xtensa_opcode_encode_fn Opcode_mula_da_lh_lddec_encode_fns[] = {
10128 static xtensa_opcode_encode_fn Opcode_mula_da_lh_ldinc_encode_fns[] = {
10132 static xtensa_opcode_encode_fn Opcode_mula_da_hh_lddec_encode_fns[] = {
10136 static xtensa_opcode_encode_fn Opcode_mula_da_hh_ldinc_encode_fns[] = {
10140 static xtensa_opcode_encode_fn Opcode_mula_dd_ll_lddec_encode_fns[] = {
10144 static xtensa_opcode_encode_fn Opcode_mula_dd_ll_ldinc_encode_fns[] = {
10148 static xtensa_opcode_encode_fn Opcode_mula_dd_hl_lddec_encode_fns[] = {
10152 static xtensa_opcode_encode_fn Opcode_mula_dd_hl_ldinc_encode_fns[] = {
10156 static xtensa_opcode_encode_fn Opcode_mula_dd_lh_lddec_encode_fns[] = {
10160 static xtensa_opcode_encode_fn Opcode_mula_dd_lh_ldinc_encode_fns[] = {
10164 static xtensa_opcode_encode_fn Opcode_mula_dd_hh_lddec_encode_fns[] = {
10168 static xtensa_opcode_encode_fn Opcode_mula_dd_hh_ldinc_encode_fns[] = {
10172 static xtensa_opcode_encode_fn Opcode_lddec_encode_fns[] = {
10176 static xtensa_opcode_encode_fn Opcode_ldinc_encode_fns[] = {
10180 static xtensa_opcode_encode_fn Opcode_rsr_m0_encode_fns[] = {
10184 static xtensa_opcode_encode_fn Opcode_wsr_m0_encode_fns[] = {
10188 static xtensa_opcode_encode_fn Opcode_xsr_m0_encode_fns[] = {
10192 static xtensa_opcode_encode_fn Opcode_rsr_m1_encode_fns[] = {
10196 static xtensa_opcode_encode_fn Opcode_wsr_m1_encode_fns[] = {
10200 static xtensa_opcode_encode_fn Opcode_xsr_m1_encode_fns[] = {
10204 static xtensa_opcode_encode_fn Opcode_rsr_m2_encode_fns[] = {
10208 static xtensa_opcode_encode_fn Opcode_wsr_m2_encode_fns[] = {
10212 static xtensa_opcode_encode_fn Opcode_xsr_m2_encode_fns[] = {
10216 static xtensa_opcode_encode_fn Opcode_rsr_m3_encode_fns[] = {
10220 static xtensa_opcode_encode_fn Opcode_wsr_m3_encode_fns[] = {
10224 static xtensa_opcode_encode_fn Opcode_xsr_m3_encode_fns[] = {
10228 static xtensa_opcode_encode_fn Opcode_rsr_acclo_encode_fns[] = {
10232 static xtensa_opcode_encode_fn Opcode_wsr_acclo_encode_fns[] = {
10236 static xtensa_opcode_encode_fn Opcode_xsr_acclo_encode_fns[] = {
10240 static xtensa_opcode_encode_fn Opcode_rsr_acchi_encode_fns[] = {
10244 static xtensa_opcode_encode_fn Opcode_wsr_acchi_encode_fns[] = {
10248 static xtensa_opcode_encode_fn Opcode_xsr_acchi_encode_fns[] = {
10252 static xtensa_opcode_encode_fn Opcode_rfi_encode_fns[] = {
10256 static xtensa_opcode_encode_fn Opcode_waiti_encode_fns[] = {
10260 static xtensa_opcode_encode_fn Opcode_rsr_interrupt_encode_fns[] = {
10264 static xtensa_opcode_encode_fn Opcode_wsr_intset_encode_fns[] = {
10268 static xtensa_opcode_encode_fn Opcode_wsr_intclear_encode_fns[] = {
10272 static xtensa_opcode_encode_fn Opcode_rsr_intenable_encode_fns[] = {
10276 static xtensa_opcode_encode_fn Opcode_wsr_intenable_encode_fns[] = {
10280 static xtensa_opcode_encode_fn Opcode_xsr_intenable_encode_fns[] = {
10284 static xtensa_opcode_encode_fn Opcode_break_encode_fns[] = {
10288 static xtensa_opcode_encode_fn Opcode_break_n_encode_fns[] = {
10292 static xtensa_opcode_encode_fn Opcode_rsr_dbreaka0_encode_fns[] = {
10296 static xtensa_opcode_encode_fn Opcode_wsr_dbreaka0_encode_fns[] = {
10300 static xtensa_opcode_encode_fn Opcode_xsr_dbreaka0_encode_fns[] = {
10304 static xtensa_opcode_encode_fn Opcode_rsr_dbreakc0_encode_fns[] = {
10308 static xtensa_opcode_encode_fn Opcode_wsr_dbreakc0_encode_fns[] = {
10312 static xtensa_opcode_encode_fn Opcode_xsr_dbreakc0_encode_fns[] = {
10316 static xtensa_opcode_encode_fn Opcode_rsr_dbreaka1_encode_fns[] = {
10320 static xtensa_opcode_encode_fn Opcode_wsr_dbreaka1_encode_fns[] = {
10324 static xtensa_opcode_encode_fn Opcode_xsr_dbreaka1_encode_fns[] = {
10328 static xtensa_opcode_encode_fn Opcode_rsr_dbreakc1_encode_fns[] = {
10332 static xtensa_opcode_encode_fn Opcode_wsr_dbreakc1_encode_fns[] = {
10336 static xtensa_opcode_encode_fn Opcode_xsr_dbreakc1_encode_fns[] = {
10340 static xtensa_opcode_encode_fn Opcode_rsr_ibreaka0_encode_fns[] = {
10344 static xtensa_opcode_encode_fn Opcode_wsr_ibreaka0_encode_fns[] = {
10348 static xtensa_opcode_encode_fn Opcode_xsr_ibreaka0_encode_fns[] = {
10352 static xtensa_opcode_encode_fn Opcode_rsr_ibreaka1_encode_fns[] = {
10356 static xtensa_opcode_encode_fn Opcode_wsr_ibreaka1_encode_fns[] = {
10360 static xtensa_opcode_encode_fn Opcode_xsr_ibreaka1_encode_fns[] = {
10364 static xtensa_opcode_encode_fn Opcode_rsr_ibreakenable_encode_fns[] = {
10368 static xtensa_opcode_encode_fn Opcode_wsr_ibreakenable_encode_fns[] = {
10372 static xtensa_opcode_encode_fn Opcode_xsr_ibreakenable_encode_fns[] = {
10376 static xtensa_opcode_encode_fn Opcode_rsr_debugcause_encode_fns[] = {
10380 static xtensa_opcode_encode_fn Opcode_wsr_debugcause_encode_fns[] = {
10384 static xtensa_opcode_encode_fn Opcode_xsr_debugcause_encode_fns[] = {
10388 static xtensa_opcode_encode_fn Opcode_rsr_icount_encode_fns[] = {
10392 static xtensa_opcode_encode_fn Opcode_wsr_icount_encode_fns[] = {
10396 static xtensa_opcode_encode_fn Opcode_xsr_icount_encode_fns[] = {
10400 static xtensa_opcode_encode_fn Opcode_rsr_icountlevel_encode_fns[] = {
10404 static xtensa_opcode_encode_fn Opcode_wsr_icountlevel_encode_fns[] = {
10408 static xtensa_opcode_encode_fn Opcode_xsr_icountlevel_encode_fns[] = {
10412 static xtensa_opcode_encode_fn Opcode_rsr_ddr_encode_fns[] = {
10416 static xtensa_opcode_encode_fn Opcode_wsr_ddr_encode_fns[] = {
10420 static xtensa_opcode_encode_fn Opcode_xsr_ddr_encode_fns[] = {
10424 static xtensa_opcode_encode_fn Opcode_lddr32_p_encode_fns[] = {
10428 static xtensa_opcode_encode_fn Opcode_sddr32_p_encode_fns[] = {
10432 static xtensa_opcode_encode_fn Opcode_rfdo_encode_fns[] = {
10436 static xtensa_opcode_encode_fn Opcode_rfdd_encode_fns[] = {
10440 static xtensa_opcode_encode_fn Opcode_wsr_mmid_encode_fns[] = {
10444 static xtensa_opcode_encode_fn Opcode_rsr_ccount_encode_fns[] = {
10448 static xtensa_opcode_encode_fn Opcode_wsr_ccount_encode_fns[] = {
10452 static xtensa_opcode_encode_fn Opcode_xsr_ccount_encode_fns[] = {
10456 static xtensa_opcode_encode_fn Opcode_rsr_ccompare0_encode_fns[] = {
10460 static xtensa_opcode_encode_fn Opcode_wsr_ccompare0_encode_fns[] = {
10464 static xtensa_opcode_encode_fn Opcode_xsr_ccompare0_encode_fns[] = {
10468 static xtensa_opcode_encode_fn Opcode_rsr_ccompare1_encode_fns[] = {
10472 static xtensa_opcode_encode_fn Opcode_wsr_ccompare1_encode_fns[] = {
10476 static xtensa_opcode_encode_fn Opcode_xsr_ccompare1_encode_fns[] = {
10480 static xtensa_opcode_encode_fn Opcode_rsr_ccompare2_encode_fns[] = {
10484 static xtensa_opcode_encode_fn Opcode_wsr_ccompare2_encode_fns[] = {
10488 static xtensa_opcode_encode_fn Opcode_xsr_ccompare2_encode_fns[] = {
10492 static xtensa_opcode_encode_fn Opcode_ipf_encode_fns[] = {
10496 static xtensa_opcode_encode_fn Opcode_ihi_encode_fns[] = {
10500 static xtensa_opcode_encode_fn Opcode_ipfl_encode_fns[] = {
10504 static xtensa_opcode_encode_fn Opcode_ihu_encode_fns[] = {
10508 static xtensa_opcode_encode_fn Opcode_iiu_encode_fns[] = {
10512 static xtensa_opcode_encode_fn Opcode_iii_encode_fns[] = {
10516 static xtensa_opcode_encode_fn Opcode_lict_encode_fns[] = {
10520 static xtensa_opcode_encode_fn Opcode_licw_encode_fns[] = {
10524 static xtensa_opcode_encode_fn Opcode_sict_encode_fns[] = {
10528 static xtensa_opcode_encode_fn Opcode_sicw_encode_fns[] = {
10532 static xtensa_opcode_encode_fn Opcode_dhwb_encode_fns[] = {
10536 static xtensa_opcode_encode_fn Opcode_dhwbi_encode_fns[] = {
10540 static xtensa_opcode_encode_fn Opcode_diwbui_p_encode_fns[] = {
10544 static xtensa_opcode_encode_fn Opcode_diwb_encode_fns[] = {
10548 static xtensa_opcode_encode_fn Opcode_diwbi_encode_fns[] = {
10552 static xtensa_opcode_encode_fn Opcode_dhi_encode_fns[] = {
10556 static xtensa_opcode_encode_fn Opcode_dii_encode_fns[] = {
10560 static xtensa_opcode_encode_fn Opcode_dpfr_encode_fns[] = {
10564 static xtensa_opcode_encode_fn Opcode_dpfw_encode_fns[] = {
10568 static xtensa_opcode_encode_fn Opcode_dpfro_encode_fns[] = {
10572 static xtensa_opcode_encode_fn Opcode_dpfwo_encode_fns[] = {
10576 static xtensa_opcode_encode_fn Opcode_dpfl_encode_fns[] = {
10580 static xtensa_opcode_encode_fn Opcode_dhu_encode_fns[] = {
10584 static xtensa_opcode_encode_fn Opcode_diu_encode_fns[] = {
10588 static xtensa_opcode_encode_fn Opcode_sdct_encode_fns[] = {
10592 static xtensa_opcode_encode_fn Opcode_ldct_encode_fns[] = {
10596 static xtensa_opcode_encode_fn Opcode_idtlb_encode_fns[] = {
10600 static xtensa_opcode_encode_fn Opcode_pdtlb_encode_fns[] = {
10604 static xtensa_opcode_encode_fn Opcode_rdtlb0_encode_fns[] = {
10608 static xtensa_opcode_encode_fn Opcode_rdtlb1_encode_fns[] = {
10612 static xtensa_opcode_encode_fn Opcode_wdtlb_encode_fns[] = {
10616 static xtensa_opcode_encode_fn Opcode_iitlb_encode_fns[] = {
10620 static xtensa_opcode_encode_fn Opcode_pitlb_encode_fns[] = {
10624 static xtensa_opcode_encode_fn Opcode_ritlb0_encode_fns[] = {
10628 static xtensa_opcode_encode_fn Opcode_ritlb1_encode_fns[] = {
10632 static xtensa_opcode_encode_fn Opcode_witlb_encode_fns[] = {
10636 static xtensa_opcode_encode_fn Opcode_clamps_encode_fns[] = {
10640 static xtensa_opcode_encode_fn Opcode_min_encode_fns[] = {
10644 static xtensa_opcode_encode_fn Opcode_max_encode_fns[] = {
10648 static xtensa_opcode_encode_fn Opcode_minu_encode_fns[] = {
10652 static xtensa_opcode_encode_fn Opcode_maxu_encode_fns[] = {
10656 static xtensa_opcode_encode_fn Opcode_nsa_encode_fns[] = {
10660 static xtensa_opcode_encode_fn Opcode_nsau_encode_fns[] = {
10664 static xtensa_opcode_encode_fn Opcode_sext_encode_fns[] = {
10668 static xtensa_opcode_encode_fn Opcode_l32ai_encode_fns[] = {
10672 static xtensa_opcode_encode_fn Opcode_s32ri_encode_fns[] = {
10676 static xtensa_opcode_encode_fn Opcode_s32c1i_encode_fns[] = {
10680 static xtensa_opcode_encode_fn Opcode_rsr_scompare1_encode_fns[] = {
10684 static xtensa_opcode_encode_fn Opcode_wsr_scompare1_encode_fns[] = {
10688 static xtensa_opcode_encode_fn Opcode_xsr_scompare1_encode_fns[] = {
10692 static xtensa_opcode_encode_fn Opcode_rsr_atomctl_encode_fns[] = {
10696 static xtensa_opcode_encode_fn Opcode_wsr_atomctl_encode_fns[] = {
10700 static xtensa_opcode_encode_fn Opcode_xsr_atomctl_encode_fns[] = {
10704 static xtensa_opcode_encode_fn Opcode_quou_encode_fns[] = {
10708 static xtensa_opcode_encode_fn Opcode_quos_encode_fns[] = {
10712 static xtensa_opcode_encode_fn Opcode_remu_encode_fns[] = {
10716 static xtensa_opcode_encode_fn Opcode_rems_encode_fns[] = {
10720 static xtensa_opcode_encode_fn Opcode_rer_encode_fns[] = {
10724 static xtensa_opcode_encode_fn Opcode_wer_encode_fns[] = {
10728 static xtensa_opcode_encode_fn Opcode_rur_expstate_encode_fns[] = {
10732 static xtensa_opcode_encode_fn Opcode_wur_expstate_encode_fns[] = {
10736 static xtensa_opcode_encode_fn Opcode_read_impwire_encode_fns[] = {
10740 static xtensa_opcode_encode_fn Opcode_setb_expstate_encode_fns[] = {
10744 static xtensa_opcode_encode_fn Opcode_clrb_expstate_encode_fns[] = {
10748 static xtensa_opcode_encode_fn Opcode_wrmsk_expstate_encode_fns[] = {
10758 static xtensa_opcode_internal opcodes[] = {
12523 static int
13741 static int
13779 static int
13796 static void
13803 static void
13810 static void
13817 static void
13824 static void
13831 static void
13838 static xtensa_get_field_fn
13898 static xtensa_set_field_fn
13958 static xtensa_get_field_fn
14018 static xtensa_set_field_fn
14078 static xtensa_get_field_fn
14138 static xtensa_set_field_fn
14198 static xtensa_slot_internal slots[] = {
14216 static void
14222 static void
14228 static void
14234 static int Format_x24_slots[] = { 0 };
14236 static int Format_x16a_slots[] = { 1 };
14238 static int Format_x16b_slots[] = { 2 };
14240 static xtensa_format_internal formats[] = {
14247 static int
14259 static int length_table[256] = {
14518 static int