Lines Matching +full:sparc +full:- +full:softmmu
2 * Sparc MMU helpers
4 * Copyright (c) 2003-2005 Fabrice Bellard
24 #include "accel/tcg/cpu-mmu-index.h"
25 #include "exec/page-protection.h"
27 #include "exec/tlb-flags.h"
29 #include "qemu/qemu-print.h"
32 /* Sparc MMU emulation */
36 * Sparc V8 Reference MMU (SRMMU)
87 full->lg_page_size = TARGET_PAGE_BITS; in get_physical_address()
89 if (rw == 2 && (env->mmuregs[0] & env->def.mmu_bm)) { in get_physical_address()
90 full->phys_addr = env->prom_addr | (address & 0x7ffffULL); in get_physical_address()
91 full->prot = PAGE_READ | PAGE_EXEC; in get_physical_address()
94 full->phys_addr = address; in get_physical_address()
95 full->prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; in get_physical_address()
100 full->phys_addr = 0xffffffffffff0000ULL; in get_physical_address()
102 /* SPARC reference MMU table walk: Context table->L1->L2->PTE */ in get_physical_address()
104 pde_ptr = (env->mmuregs[1] << 4) + (env->mmuregs[2] << 2); in get_physical_address()
105 pde = address_space_ldl(cs->as, pde_ptr, MEMTXATTRS_UNSPECIFIED, &result); in get_physical_address()
120 pde = address_space_ldl(cs->as, pde_ptr, in get_physical_address()
134 pde = address_space_ldl(cs->as, pde_ptr, in get_physical_address()
148 pde = address_space_ldl(cs->as, pde_ptr, in get_physical_address()
164 full->lg_page_size = TARGET_PAGE_BITS; in get_physical_address()
168 full->lg_page_size = 18; in get_physical_address()
173 full->lg_page_size = 24; in get_physical_address()
181 if (error_code && !((env->mmuregs[0] & MMU_NF) && is_user)) { in get_physical_address()
192 stl_phys_notdirty(cs->as, pde_ptr, pde); in get_physical_address()
196 full->prot = perm_table[is_user][access_perms]; in get_physical_address()
200 full->prot &= ~PAGE_WRITE; in get_physical_address()
205 full->phys_addr = ((hwaddr)(pde & PTE_ADDR_MASK) << 4) + page_offset; in get_physical_address()
233 "Translate at %" VADDR_PRIx " -> " in sparc_cpu_tlb_fill()
240 if (env->mmuregs[3]) { /* Fault status register */ in sparc_cpu_tlb_fill()
241 env->mmuregs[3] = 1; /* overflow (not read before another fault) */ in sparc_cpu_tlb_fill()
243 env->mmuregs[3] |= (access_index << 5) | error_code | 2; in sparc_cpu_tlb_fill()
244 env->mmuregs[4] = address; /* Fault address register */ in sparc_cpu_tlb_fill()
246 if ((env->mmuregs[0] & MMU_NF) || env->psret == 0) { in sparc_cpu_tlb_fill()
256 cs->exception_index = TT_TFAULT; in sparc_cpu_tlb_fill()
258 cs->exception_index = TT_DFAULT; in sparc_cpu_tlb_fill()
277 pde_ptr = (hwaddr)(env->mmuregs[1] << 4) + in mmu_probe()
278 (env->mmuregs[2] << 2); in mmu_probe()
279 pde = address_space_ldl(cs->as, pde_ptr, MEMTXATTRS_UNSPECIFIED, &result); in mmu_probe()
295 pde = address_space_ldl(cs->as, pde_ptr, in mmu_probe()
313 pde = address_space_ldl(cs->as, pde_ptr, in mmu_probe()
331 pde = address_space_ldl(cs->as, pde_ptr, in mmu_probe()
361 (hwaddr)env->mmuregs[1] << 4, env->mmuregs[2]); in dump_mmu()
393 * that the sparc ABI is followed.
402 int cwp = env->cwp; in sparc_cpu_memory_rw_debug()
405 for (i = 0; i < env->nwindows; i++) { in sparc_cpu_memory_rw_debug()
407 target_ulong fp = env->regbase[cwp * 16 + 22]; in sparc_cpu_memory_rw_debug()
417 if (env->wim & (1 << cwp)) { in sparc_cpu_memory_rw_debug()
433 len1 = fp - addr; in sparc_cpu_memory_rw_debug()
435 return -1; in sparc_cpu_memory_rw_debug()
438 len -= len1; in sparc_cpu_memory_rw_debug()
445 off = addr - fp; in sparc_cpu_memory_rw_debug()
446 len1 = 64 - off; in sparc_cpu_memory_rw_debug()
452 for (; len1; len1--) { in sparc_cpu_memory_rw_debug()
458 u.v = cpu_to_be32(env->regbase[reg]); in sparc_cpu_memory_rw_debug()
461 len--; in sparc_cpu_memory_rw_debug()
492 uint64_t mask = -(8192ULL << 3 * TTE_PGSIZE(tlb->tte)); in ultrasparc_tag_match()
495 if (TTE_IS_VALID(tlb->tte) && in ultrasparc_tag_match()
496 (TTE_IS_GLOBAL(tlb->tte) || tlb_compare_context(tlb, context)) in ultrasparc_tag_match()
497 && compare_masked(address, tlb->tag, mask)) { in ultrasparc_tag_match()
499 *physical = ((tlb->tte & mask) | (address & ~mask)) & 0x1ffffffe000ULL; in ultrasparc_tag_match()
535 if (env->pstate & PS_PRIV) { in build_sfsr()
539 if (env->dmmu.sfsr & SFSR_VALID_BIT) { /* Fault status register */ in build_sfsr()
566 context = env->dmmu.mmu_primary_context & 0x1fff; in get_physical_address_data()
572 context = env->dmmu.mmu_secondary_context & 0x1fff; in get_physical_address_data()
581 if (ultrasparc_tag_match(&env->dtlb[i], address, context, in get_physical_address_data()
582 &full->phys_addr)) { in get_physical_address_data()
585 if (TTE_IS_IE(env->dtlb[i].tte)) { in get_physical_address_data()
586 full->tlb_fill_flags |= TLB_BSWAP; in get_physical_address_data()
591 if (TTE_IS_PRIV(env->dtlb[i].tte) && is_user) { in get_physical_address_data()
594 trace_mmu_helper_dfault(address, context, mmu_idx, env->tl); in get_physical_address_data()
597 if (TTE_IS_SIDEEFFECT(env->dtlb[i].tte)) { in get_physical_address_data()
602 if (TTE_IS_NFO(env->dtlb[i].tte)) { in get_physical_address_data()
610 cs->exception_index = TT_DFAULT; in get_physical_address_data()
611 } else if (!TTE_IS_W_OK(env->dtlb[i].tte) && (rw == 1)) { in get_physical_address_data()
613 cs->exception_index = TT_DPROT; in get_physical_address_data()
615 trace_mmu_helper_dprot(address, context, mmu_idx, env->tl); in get_physical_address_data()
619 full->prot = PAGE_READ; in get_physical_address_data()
620 if (TTE_IS_W_OK(env->dtlb[i].tte)) { in get_physical_address_data()
621 full->prot |= PAGE_WRITE; in get_physical_address_data()
624 TTE_SET_USED(env->dtlb[i].tte); in get_physical_address_data()
629 env->dmmu.sfsr = sfsr; in get_physical_address_data()
630 env->dmmu.sfar = address; /* Fault address register */ in get_physical_address_data()
631 env->dmmu.tag_access = (address & ~0x1fffULL) | context; in get_physical_address_data()
640 * - UltraSPARC IIi: SFSR and SFAR unmodified in get_physical_address_data()
641 * - JPS1: SFAR updated and some fields of SFSR updated in get_physical_address_data()
643 env->dmmu.tag_access = (address & ~0x1fffULL) | context; in get_physical_address_data()
644 cs->exception_index = TT_DMISS; in get_physical_address_data()
665 context = env->dmmu.mmu_primary_context & 0x1fff; in get_physical_address_code()
672 if (env->tl == 0) { in get_physical_address_code()
674 context = env->dmmu.mmu_primary_context & 0x1fff; in get_physical_address_code()
682 if (ultrasparc_tag_match(&env->itlb[i], in get_physical_address_code()
683 address, context, &full->phys_addr)) { in get_physical_address_code()
685 if (TTE_IS_PRIV(env->itlb[i].tte) && is_user) { in get_physical_address_code()
687 if (env->immu.sfsr & SFSR_VALID_BIT) { in get_physical_address_code()
688 env->immu.sfsr = SFSR_OW_BIT; /* overflow (not read before in get_physical_address_code()
691 env->immu.sfsr = 0; in get_physical_address_code()
693 if (env->pstate & PS_PRIV) { in get_physical_address_code()
694 env->immu.sfsr |= SFSR_PR_BIT; in get_physical_address_code()
696 if (env->tl > 0) { in get_physical_address_code()
697 env->immu.sfsr |= SFSR_CT_NUCLEUS; in get_physical_address_code()
701 env->immu.sfsr |= SFSR_FT_PRIV_BIT | SFSR_VALID_BIT; in get_physical_address_code()
702 cs->exception_index = TT_TFAULT; in get_physical_address_code()
704 env->immu.tag_access = (address & ~0x1fffULL) | context; in get_physical_address_code()
710 full->prot = PAGE_EXEC; in get_physical_address_code()
711 TTE_SET_USED(env->itlb[i].tte); in get_physical_address_code()
719 env->immu.tag_access = (address & ~0x1fffULL) | context; in get_physical_address_code()
720 cs->exception_index = TT_TMISS; in get_physical_address_code()
730 full->lg_page_size = TARGET_PAGE_BITS; in get_physical_address()
732 /* safety net to catch wrong softmmu index use from dynamic code */ in get_physical_address()
733 if (env->tl > 0 && mmu_idx != MMU_NUCLEUS_IDX) { in get_physical_address()
735 trace_mmu_helper_get_phys_addr_code(env->tl, mmu_idx, in get_physical_address()
736 env->dmmu.mmu_primary_context, in get_physical_address()
737 env->dmmu.mmu_secondary_context, in get_physical_address()
740 trace_mmu_helper_get_phys_addr_data(env->tl, mmu_idx, in get_physical_address()
741 env->dmmu.mmu_primary_context, in get_physical_address()
742 env->dmmu.mmu_secondary_context, in get_physical_address()
748 full->phys_addr = ultrasparc_truncate_physical(address); in get_physical_address()
749 full->prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; in get_physical_address()
773 trace_mmu_helper_mmu_fault(address, full.phys_addr, mmu_idx, env->tl, in sparc_cpu_tlb_fill()
774 env->dmmu.mmu_primary_context, in sparc_cpu_tlb_fill()
775 env->dmmu.mmu_secondary_context); in sparc_cpu_tlb_fill()
792 env->dmmu.mmu_primary_context, in dump_mmu()
793 env->dmmu.mmu_secondary_context); in dump_mmu()
795 "\n", env->dmmu.tag_access, env->dmmu.tsb_tag_target); in dump_mmu()
796 if ((env->lsu & DMMU_E) == 0) { in dump_mmu()
801 switch (TTE_PGSIZE(env->dtlb[i].tte)) { in dump_mmu()
816 if (TTE_IS_VALID(env->dtlb[i].tte)) { in dump_mmu()
820 env->dtlb[i].tag & (uint64_t)~0x1fffULL, in dump_mmu()
821 TTE_PA(env->dtlb[i].tte), in dump_mmu()
823 TTE_IS_PRIV(env->dtlb[i].tte) ? "priv" : "user", in dump_mmu()
824 TTE_IS_W_OK(env->dtlb[i].tte) ? "RW" : "RO", in dump_mmu()
825 TTE_IS_LOCKED(env->dtlb[i].tte) ? in dump_mmu()
827 TTE_IS_IE(env->dtlb[i].tte) ? in dump_mmu()
829 env->dtlb[i].tag & (uint64_t)0x1fffULL, in dump_mmu()
830 TTE_IS_GLOBAL(env->dtlb[i].tte) ? in dump_mmu()
835 if ((env->lsu & IMMU_E) == 0) { in dump_mmu()
840 switch (TTE_PGSIZE(env->itlb[i].tte)) { in dump_mmu()
855 if (TTE_IS_VALID(env->itlb[i].tte)) { in dump_mmu()
859 env->itlb[i].tag & (uint64_t)~0x1fffULL, in dump_mmu()
860 TTE_PA(env->itlb[i].tte), in dump_mmu()
862 TTE_IS_PRIV(env->itlb[i].tte) ? "priv" : "user", in dump_mmu()
863 TTE_IS_LOCKED(env->itlb[i].tte) ? in dump_mmu()
865 env->itlb[i].tag & (uint64_t)0x1fffULL, in dump_mmu()
866 TTE_IS_GLOBAL(env->itlb[i].tte) ? in dump_mmu()
895 return -1; in cpu_get_phys_page_nofault()
909 return -1; in sparc_cpu_get_phys_page_debug()
923 env->dmmu.sfsr = build_sfsr(env, mmu_idx, access_type); in sparc_cpu_do_unaligned_access()
924 env->dmmu.sfar = addr; in sparc_cpu_do_unaligned_access()
926 env->mmuregs[4] = addr; in sparc_cpu_do_unaligned_access()