Lines Matching +full:asi +full:- +full:format
4 * Copyright (c) 2003-2005 Fabrice Bellard
25 #include "exec/helper-proto.h"
26 #include "exec/exec-all.h"
27 #include "exec/page-protection.h"
29 #include "asi.h"
53 do { printf("ASI: " fmt , ## __VA_ARGS__); } while (0)
65 #define AM_CHECK(env1) ((env1)->pstate & PS_AM)
82 int ctx = mmu->tag_access & 0x1fffULL; in ultrasparc_tsb_pointer()
83 uint64_t ctx_register = mmu->sun4v_ctx_config[ctx ? 1 : 0]; in ultrasparc_tsb_pointer()
88 tsb_register = mmu->sun4v_tsb_pointers[tsb_index]; in ultrasparc_tsb_pointer()
91 tsb_register = mmu->tsb; in ultrasparc_tsb_pointer()
100 uint64_t va = mmu->tag_access >> (3 * page_size + 9); in ultrasparc_tsb_pointer()
129 if (TTE_IS_VALID(tlb->tte)) { in replace_tlb_entry()
132 size = 8192ULL << 3 * TTE_PGSIZE(tlb->tte); in replace_tlb_entry()
135 va = tlb->tag & mask; in replace_tlb_entry()
142 tlb->tag = tlb_tag; in replace_tlb_entry()
143 tlb->tte = tlb_tte; in replace_tlb_entry()
158 context = env1->dmmu.mmu_primary_context; in demap_tlb()
161 context = env1->dmmu.mmu_secondary_context; in demap_tlb()
175 /* will remove non-global entries matching context value */ in demap_tlb()
211 /* is already in the sun4u format */ in sun4v_tte_to_sun4u()
245 DPRINTF_MMU("auto demap entry [%d] %lx->%lx\n", i, vaddr, in replace_tlb_1bit_lru()
303 /* returns true if access using this ASI is to have address translated by MMU
306 static inline int is_translating_asi(int asi) in is_translating_asi() argument
308 /* Ultrasparc IIi translating asi in is_translating_asi()
309 - note this list is defined by cpu implementation in is_translating_asi()
311 switch (asi) { in is_translating_asi()
335 int asi, target_ulong addr) in asi_address_mask() argument
337 if (is_translating_asi(asi)) { in asi_address_mask()
344 static inline void do_check_asi(CPUSPARCState *env, int asi, uintptr_t ra) in do_check_asi() argument
350 if (asi < 0x80 in do_check_asi()
353 || (asi >= 0x30 && cpu_has_hypervisor(env)))) { in do_check_asi()
376 env->mxccdata[0], env->mxccdata[1], in dump_mxcc()
377 env->mxccdata[2], env->mxccdata[3]); in dump_mxcc()
382 env->mxccregs[0], env->mxccregs[1], in dump_mxcc()
383 env->mxccregs[2], env->mxccregs[3], in dump_mxcc()
384 env->mxccregs[4], env->mxccregs[5], in dump_mxcc()
385 env->mxccregs[6], env->mxccregs[7]); in dump_mxcc()
391 static void dump_asi(const char *txt, target_ulong addr, int asi, int size, in dump_asi() argument
396 DPRINTF_ASI("%s "TARGET_FMT_lx " asi 0x%02x = %02" PRIx64 "\n", txt, in dump_asi()
397 addr, asi, r1 & 0xff); in dump_asi()
400 DPRINTF_ASI("%s "TARGET_FMT_lx " asi 0x%02x = %04" PRIx64 "\n", txt, in dump_asi()
401 addr, asi, r1 & 0xffff); in dump_asi()
404 DPRINTF_ASI("%s "TARGET_FMT_lx " asi 0x%02x = %08" PRIx64 "\n", txt, in dump_asi()
405 addr, asi, r1 & 0xffffffff); in dump_asi()
408 DPRINTF_ASI("%s "TARGET_FMT_lx " asi 0x%02x = %016" PRIx64 "\n", txt, in dump_asi()
409 addr, asi, r1); in dump_asi()
427 " asi 0x%02x from " TARGET_FMT_lx "\n", in sparc_raise_mmu_fault()
429 size == 1 ? "" : "s", addr, is_asi, env->pc); in sparc_raise_mmu_fault()
434 size == 1 ? "" : "s", addr, env->pc); in sparc_raise_mmu_fault()
438 fault_type = (env->mmuregs[3] & 0x1c) >> 2; in sparc_raise_mmu_fault()
440 env->mmuregs[3] = 0; /* Fault status register */ in sparc_raise_mmu_fault()
442 env->mmuregs[3] |= 1 << 16; in sparc_raise_mmu_fault()
444 if (env->psrs) { in sparc_raise_mmu_fault()
445 env->mmuregs[3] |= 1 << 5; in sparc_raise_mmu_fault()
448 env->mmuregs[3] |= 1 << 6; in sparc_raise_mmu_fault()
451 env->mmuregs[3] |= 1 << 7; in sparc_raise_mmu_fault()
453 env->mmuregs[3] |= (5 << 2) | 2; in sparc_raise_mmu_fault()
456 env->mmuregs[4] = addr; /* Fault address register */ in sparc_raise_mmu_fault()
460 if (fault_type == ((env->mmuregs[3] & 0x1c)) >> 2) { in sparc_raise_mmu_fault()
461 env->mmuregs[3] |= 1; in sparc_raise_mmu_fault()
464 if ((env->mmuregs[0] & MMU_E) && !(env->mmuregs[0] & MMU_NF)) { in sparc_raise_mmu_fault()
470 * flush neverland mappings created during no-fault mode, in sparc_raise_mmu_fault()
473 if (env->mmuregs[0] & MMU_NF) { in sparc_raise_mmu_fault()
486 "\n", addr, env->pc); in sparc_raise_mmu_fault()
490 if (env->lsu & (IMMU_E)) { in sparc_raise_mmu_fault()
492 } else if (cpu_has_hypervisor(env) && !(env->hpstate & HS_PRIV)) { in sparc_raise_mmu_fault()
496 if (env->lsu & (DMMU_E)) { in sparc_raise_mmu_fault()
498 } else if (cpu_has_hypervisor(env) && !(env->hpstate & HS_PRIV)) { in sparc_raise_mmu_fault()
533 env->cache_control = val; in leon3_cache_control_st()
557 ret = env->cache_control; in leon3_cache_control_ld()
579 int asi, uint32_t memop) in helper_ld_asi() argument
589 do_check_align(env, addr, size - 1, GETPC()); in helper_ld_asi()
590 switch (asi) { in helper_ld_asi()
597 if (env->def.features & CPU_FEATURE_CACHE_CTRL) { in helper_ld_asi()
603 ret = env->mxccregs[3]; in helper_ld_asi()
612 ret = env->mxccregs[3]; in helper_ld_asi()
621 ret = env->mxccregs[5]; in helper_ld_asi()
631 ret = env->mxccregs[7]; in helper_ld_asi()
644 DPRINTF_MXCC("asi = %d, size = %d, sign = %d, " in helper_ld_asi()
645 "addr = %08x -> ret = %" PRIx64 "," in helper_ld_asi()
646 "addr = %08x\n", asi, size, sign, last_addr, ret, addr); in helper_ld_asi()
662 DPRINTF_MMU("mmu_probe: 0x%08x (lev %d) -> 0x%08" PRIx64 "\n", in helper_ld_asi()
671 ret = env->mmuregs[reg]; in helper_ld_asi()
673 env->mmuregs[3] = 0; in helper_ld_asi()
675 ret = env->mmuregs[3]; in helper_ld_asi()
677 ret = env->mmuregs[4]; in helper_ld_asi()
686 case ASI_M_TXTC_TAG: /* SparcStation 5 I-cache tag */ in helper_ld_asi()
687 case ASI_M_TXTC_DATA: /* SparcStation 5 I-cache data */ in helper_ld_asi()
688 case ASI_M_DATAC_TAG: /* SparcStation 5 D-cache tag */ in helper_ld_asi()
689 case ASI_M_DATAC_DATA: /* SparcStation 5 D-cache data */ in helper_ld_asi()
694 hwaddr access_addr = (hwaddr)addr | ((hwaddr)(asi & 0xf) << 32); in helper_ld_asi()
698 ret = address_space_ldub(cs->as, access_addr, in helper_ld_asi()
702 ret = address_space_lduw(cs->as, access_addr, in helper_ld_asi()
707 ret = address_space_ldl(cs->as, access_addr, in helper_ld_asi()
711 ret = address_space_ldq(cs->as, access_addr, in helper_ld_asi()
734 ret = env->mmubpregs[reg]; in helper_ld_asi()
737 ret = env->mmubpregs[reg]; in helper_ld_asi()
740 ret = env->mmubpregs[reg]; in helper_ld_asi()
743 ret = env->mmubpregs[reg]; in helper_ld_asi()
744 env->mmubpregs[reg] = 0ULL; in helper_ld_asi()
752 ret = env->mmubpctrv; in helper_ld_asi()
755 ret = env->mmubpctrc; in helper_ld_asi()
758 ret = env->mmubpctrs; in helper_ld_asi()
761 ret = env->mmubpaction; in helper_ld_asi()
764 sparc_raise_mmu_fault(cs, addr, false, false, asi, size, GETPC()); in helper_ld_asi()
794 dump_asi("read ", last_addr, asi, size, ret); in helper_ld_asi()
800 int asi, uint32_t memop) in helper_st_asi() argument
805 do_check_align(env, addr, size - 1, GETPC()); in helper_st_asi()
806 switch (asi) { in helper_st_asi()
813 if (env->def.features & CPU_FEATURE_CACHE_CTRL) { in helper_st_asi()
820 env->mxccdata[0] = val; in helper_st_asi()
829 env->mxccdata[1] = val; in helper_st_asi()
838 env->mxccdata[2] = val; in helper_st_asi()
847 env->mxccdata[3] = val; in helper_st_asi()
859 env->mxccregs[0] = val; in helper_st_asi()
868 hwaddr access_addr = (env->mxccregs[0] & 0xffffffffULL) + 8 * i; in helper_st_asi()
870 env->mxccdata[i] = address_space_ldq(cs->as, in helper_st_asi()
887 env->mxccregs[1] = val; in helper_st_asi()
896 hwaddr access_addr = (env->mxccregs[1] & 0xffffffffULL) + 8 * i; in helper_st_asi()
898 address_space_stq(cs->as, access_addr, env->mxccdata[i], in helper_st_asi()
911 env->mxccregs[3] = val; in helper_st_asi()
920 env->mxccregs[3] = (env->mxccregs[3] & 0xffffffff00000000ULL) in helper_st_asi()
931 env->mxccregs[6] &= ~val; in helper_st_asi()
940 env->mxccregs[7] = val; in helper_st_asi()
953 DPRINTF_MXCC("asi = %d, size = %d, addr = %08x, val = %" PRIx64 "\n", in helper_st_asi()
954 asi, size, addr, val); in helper_st_asi()
990 oldreg = env->mmuregs[reg]; in helper_st_asi()
993 env->mmuregs[reg] = (env->mmuregs[reg] & 0xff000000) | in helper_st_asi()
995 /* Mappings generated during no-fault mode in helper_st_asi()
997 if ((oldreg ^ env->mmuregs[reg]) in helper_st_asi()
998 & (MMU_NF | env->def.mmu_bm)) { in helper_st_asi()
1003 env->mmuregs[reg] = val & env->def.mmu_ctpr_mask; in helper_st_asi()
1006 env->mmuregs[reg] = val & env->def.mmu_cxr_mask; in helper_st_asi()
1007 if (oldreg != env->mmuregs[reg]) { in helper_st_asi()
1017 env->mmuregs[reg] = val & env->def.mmu_trcr_mask; in helper_st_asi()
1021 env->mmuregs[3] = val & env->def.mmu_sfsr_mask; in helper_st_asi()
1024 env->mmuregs[4] = val; in helper_st_asi()
1027 env->mmuregs[reg] = val; in helper_st_asi()
1030 if (oldreg != env->mmuregs[reg]) { in helper_st_asi()
1031 DPRINTF_MMU("mmu change reg[%d]: 0x%08x -> 0x%08x\n", in helper_st_asi()
1032 reg, oldreg, env->mmuregs[reg]); in helper_st_asi()
1043 case ASI_M_TXTC_TAG: /* I-cache tag */ in helper_st_asi()
1044 case ASI_M_TXTC_DATA: /* I-cache data */ in helper_st_asi()
1045 case ASI_M_DATAC_TAG: /* D-cache tag */ in helper_st_asi()
1046 case ASI_M_DATAC_DATA: /* D-cache data */ in helper_st_asi()
1047 case ASI_M_FLUSH_PAGE: /* I/D-cache flush page */ in helper_st_asi()
1048 case ASI_M_FLUSH_SEG: /* I/D-cache flush segment */ in helper_st_asi()
1049 case ASI_M_FLUSH_REGION: /* I/D-cache flush region */ in helper_st_asi()
1050 case ASI_M_FLUSH_CTX: /* I/D-cache flush context */ in helper_st_asi()
1051 case ASI_M_FLUSH_USER: /* I/D-cache flush user */ in helper_st_asi()
1056 hwaddr access_addr = (hwaddr)addr | ((hwaddr)(asi & 0xf) << 32); in helper_st_asi()
1060 address_space_stb(cs->as, access_addr, val, in helper_st_asi()
1064 address_space_stw(cs->as, access_addr, val, in helper_st_asi()
1069 address_space_stl(cs->as, access_addr, val, in helper_st_asi()
1073 address_space_stq(cs->as, access_addr, val, in helper_st_asi()
1084 case 0x31: /* store buffer data, Ross RT620 I-cache flush or in helper_st_asi()
1088 case 0x36: /* I-cache flash clear */ in helper_st_asi()
1089 case 0x37: /* D-cache flash clear */ in helper_st_asi()
1097 env->mmubpregs[reg] = (val & 0xfffffffffULL); in helper_st_asi()
1100 env->mmubpregs[reg] = (val & 0xfffffffffULL); in helper_st_asi()
1103 env->mmubpregs[reg] = (val & 0x7fULL); in helper_st_asi()
1106 env->mmubpregs[reg] = (val & 0xfULL); in helper_st_asi()
1110 env->mmuregs[reg]); in helper_st_asi()
1114 env->mmubpctrv = val & 0xffffffff; in helper_st_asi()
1117 env->mmubpctrc = val & 0x3; in helper_st_asi()
1120 env->mmubpctrs = val & 0x3; in helper_st_asi()
1123 env->mmubpaction = val & 0x1fff; in helper_st_asi()
1128 sparc_raise_mmu_fault(cs, addr, true, false, asi, size, GETPC()); in helper_st_asi()
1142 dump_asi("write", addr, asi, size, val); in helper_st_asi()
1194 int asi, uint32_t memop) in helper_ld_asi() argument
1200 if (asi < 0x80) { in helper_ld_asi()
1203 do_check_align(env, addr, size - 1, GETPC()); in helper_ld_asi()
1204 addr = asi_address_mask(env, asi, addr); in helper_ld_asi()
1206 switch (asi) { in helper_ld_asi()
1207 case ASI_PNF: /* Primary no-fault */ in helper_ld_asi()
1208 case ASI_PNFL: /* Primary no-fault LE */ in helper_ld_asi()
1209 case ASI_SNF: /* Secondary no-fault */ in helper_ld_asi()
1210 case ASI_SNFL: /* Secondary no-fault LE */ in helper_ld_asi()
1246 switch (asi) { in helper_ld_asi()
1247 case ASI_PNFL: /* Primary no-fault LE */ in helper_ld_asi()
1248 case ASI_SNFL: /* Secondary no-fault LE */ in helper_ld_asi()
1277 dump_asi("read", addr, asi, size, ret); in helper_ld_asi()
1283 int asi, uint32_t memop) in helper_st_asi() argument
1287 dump_asi("write", addr, asi, size, val); in helper_st_asi()
1289 if (asi < 0x80) { in helper_st_asi()
1292 do_check_align(env, addr, size - 1, GETPC()); in helper_st_asi()
1294 switch (asi) { in helper_st_asi()
1302 case ASI_PNF: /* Primary no-fault, RO */ in helper_st_asi()
1303 case ASI_SNF: /* Secondary no-fault, RO */ in helper_st_asi()
1304 case ASI_PNFL: /* Primary no-fault LE, RO */ in helper_st_asi()
1305 case ASI_SNFL: /* Secondary no-fault LE, RO */ in helper_st_asi()
1314 int asi, uint32_t memop) in helper_ld_asi() argument
1324 asi &= 0xff; in helper_ld_asi()
1326 do_check_asi(env, asi, GETPC()); in helper_ld_asi()
1327 do_check_align(env, addr, size - 1, GETPC()); in helper_ld_asi()
1328 addr = asi_address_mask(env, asi, addr); in helper_ld_asi()
1330 switch (asi) { in helper_ld_asi()
1337 int idx = (env->pstate & PS_PRIV in helper_ld_asi()
1338 ? (asi & 1 ? MMU_KERNEL_SECONDARY_IDX : MMU_KERNEL_IDX) in helper_ld_asi()
1339 : (asi & 1 ? MMU_USER_SECONDARY_IDX : MMU_USER_IDX)); in helper_ld_asi()
1341 if (cpu_get_phys_page_nofault(env, addr, idx) == -1ULL) { in helper_ld_asi()
1343 dump_asi("read ", last_addr, asi, size, ret); in helper_ld_asi()
1346 cpu_raise_exception_ra(env, cs->exception_index, GETPC()); in helper_ld_asi()
1377 case ASI_REAL_IO: /* Bypass, non-cacheable */ in helper_ld_asi()
1379 case ASI_REAL_IO_L: /* Bypass, non-cacheable LE */ in helper_ld_asi()
1408 ret = env->lsu; in helper_ld_asi()
1410 case ASI_IMMU: /* I-MMU regs */ in helper_ld_asi()
1415 /* 0x00 I-TSB Tag Target register */ in helper_ld_asi()
1416 ret = ultrasparc_tag_target(env->immu.tag_access); in helper_ld_asi()
1419 ret = env->immu.sfsr; in helper_ld_asi()
1422 ret = env->immu.tsb; in helper_ld_asi()
1425 /* 0x30 I-TSB Tag Access register */ in helper_ld_asi()
1426 ret = env->immu.tag_access; in helper_ld_asi()
1434 case ASI_IMMU_TSB_8KB_PTR: /* I-MMU 8k TSB pointer */ in helper_ld_asi()
1436 /* env->immuregs[5] holds I-MMU TSB register value in helper_ld_asi()
1437 env->immuregs[6] holds I-MMU Tag Access register value */ in helper_ld_asi()
1438 ret = ultrasparc_tsb_pointer(env, &env->immu, 0); in helper_ld_asi()
1441 case ASI_IMMU_TSB_64KB_PTR: /* I-MMU 64k TSB pointer */ in helper_ld_asi()
1443 /* env->immuregs[5] holds I-MMU TSB register value in helper_ld_asi()
1444 env->immuregs[6] holds I-MMU Tag Access register value */ in helper_ld_asi()
1445 ret = ultrasparc_tsb_pointer(env, &env->immu, 1); in helper_ld_asi()
1448 case ASI_ITLB_DATA_ACCESS: /* I-MMU data access */ in helper_ld_asi()
1452 ret = env->itlb[reg].tte; in helper_ld_asi()
1455 case ASI_ITLB_TAG_READ: /* I-MMU tag read */ in helper_ld_asi()
1459 ret = env->itlb[reg].tag; in helper_ld_asi()
1462 case ASI_DMMU: /* D-MMU regs */ in helper_ld_asi()
1467 /* 0x00 D-TSB Tag Target register */ in helper_ld_asi()
1468 ret = ultrasparc_tag_target(env->dmmu.tag_access); in helper_ld_asi()
1471 ret = env->dmmu.mmu_primary_context; in helper_ld_asi()
1474 ret = env->dmmu.mmu_secondary_context; in helper_ld_asi()
1477 ret = env->dmmu.sfsr; in helper_ld_asi()
1480 ret = env->dmmu.sfar; in helper_ld_asi()
1483 ret = env->dmmu.tsb; in helper_ld_asi()
1485 case 6: /* 0x30 D-TSB Tag Access register */ in helper_ld_asi()
1486 ret = env->dmmu.tag_access; in helper_ld_asi()
1489 ret = env->dmmu.virtual_watchpoint; in helper_ld_asi()
1492 ret = env->dmmu.physical_watchpoint; in helper_ld_asi()
1500 case ASI_DMMU_TSB_8KB_PTR: /* D-MMU 8k TSB pointer */ in helper_ld_asi()
1502 /* env->dmmuregs[5] holds D-MMU TSB register value in helper_ld_asi()
1503 env->dmmuregs[6] holds D-MMU Tag Access register value */ in helper_ld_asi()
1504 ret = ultrasparc_tsb_pointer(env, &env->dmmu, 0); in helper_ld_asi()
1507 case ASI_DMMU_TSB_64KB_PTR: /* D-MMU 64k TSB pointer */ in helper_ld_asi()
1509 /* env->dmmuregs[5] holds D-MMU TSB register value in helper_ld_asi()
1510 env->dmmuregs[6] holds D-MMU Tag Access register value */ in helper_ld_asi()
1511 ret = ultrasparc_tsb_pointer(env, &env->dmmu, 1); in helper_ld_asi()
1514 case ASI_DTLB_DATA_ACCESS: /* D-MMU data access */ in helper_ld_asi()
1518 ret = env->dtlb[reg].tte; in helper_ld_asi()
1521 case ASI_DTLB_TAG_READ: /* D-MMU tag read */ in helper_ld_asi()
1525 ret = env->dtlb[reg].tag; in helper_ld_asi()
1531 ret = env->ivec_status; in helper_ld_asi()
1537 ret = env->ivec_data[reg]; in helper_ld_asi()
1550 ret = env->scratch[i]; in helper_ld_asi()
1556 ret = env->dmmu.mmu_primary_context; in helper_ld_asi()
1559 ret = env->dmmu.mmu_secondary_context; in helper_ld_asi()
1565 case ASI_DCACHE_DATA: /* D-cache data */ in helper_ld_asi()
1566 case ASI_DCACHE_TAG: /* D-cache tag access */ in helper_ld_asi()
1567 case ASI_ESTATE_ERROR_EN: /* E-cache error enable */ in helper_ld_asi()
1568 case ASI_AFSR: /* E-cache asynchronous fault status */ in helper_ld_asi()
1569 case ASI_AFAR: /* E-cache asynchronous fault address */ in helper_ld_asi()
1570 case ASI_EC_TAG_DATA: /* E-cache tag data */ in helper_ld_asi()
1571 case ASI_IC_INSTR: /* I-cache instruction access */ in helper_ld_asi()
1572 case ASI_IC_TAG: /* I-cache tag access */ in helper_ld_asi()
1573 case ASI_IC_PRE_DECODE: /* I-cache predecode */ in helper_ld_asi()
1574 case ASI_IC_NEXT_FIELD: /* I-cache LRU etc. */ in helper_ld_asi()
1575 case ASI_EC_W: /* E-cache tag */ in helper_ld_asi()
1576 case ASI_EC_R: /* E-cache tag */ in helper_ld_asi()
1578 case ASI_DMMU_TSB_DIRECT_PTR: /* D-MMU data pointer */ in helper_ld_asi()
1579 case ASI_ITLB_DATA_IN: /* I-MMU data in, WO */ in helper_ld_asi()
1580 case ASI_IMMU_DEMAP: /* I-MMU demap, WO */ in helper_ld_asi()
1581 case ASI_DTLB_DATA_IN: /* D-MMU data in, WO */ in helper_ld_asi()
1582 case ASI_DMMU_DEMAP: /* D-MMU demap, WO */ in helper_ld_asi()
1607 dump_asi("read ", last_addr, asi, size, ret); in helper_ld_asi()
1613 int asi, uint32_t memop) in helper_st_asi() argument
1619 dump_asi("write", addr, asi, size, val); in helper_st_asi()
1622 asi &= 0xff; in helper_st_asi()
1624 do_check_asi(env, asi, GETPC()); in helper_st_asi()
1625 do_check_align(env, addr, size - 1, GETPC()); in helper_st_asi()
1626 addr = asi_address_mask(env, asi, addr); in helper_st_asi()
1628 switch (asi) { in helper_st_asi()
1638 case ASI_REAL_IO: /* Bypass, non-cacheable */ in helper_st_asi()
1640 case ASI_REAL_IO_L: /* Bypass, non-cacheable LE */ in helper_st_asi()
1660 /* these ASIs have different functions on UltraSPARC-IIIi in helper_st_asi()
1674 int idx = ((asi & 2) >> 1) | ((asi & 8) >> 2); in helper_st_asi()
1675 env->dmmu.sun4v_tsb_pointers[idx] = val; in helper_st_asi()
1687 env->dmmu.sun4v_ctx_config[(asi & 8) >> 3] = val; in helper_st_asi()
1703 int idx = ((asi & 2) >> 1) | ((asi & 8) >> 2); in helper_st_asi()
1704 env->immu.sun4v_tsb_pointers[idx] = val; in helper_st_asi()
1716 env->immu.sun4v_ctx_config[(asi & 8) >> 3] = val; in helper_st_asi()
1725 env->lsu = val & (DMMU_E | IMMU_E); in helper_st_asi()
1727 case ASI_IMMU: /* I-MMU regs */ in helper_st_asi()
1732 oldreg = env->immu.mmuregs[reg]; in helper_st_asi()
1736 case 1: /* Not in I-MMU */ in helper_st_asi()
1743 env->immu.sfsr = val; in helper_st_asi()
1748 DPRINTF_MMU("immu TSB write: 0x%016" PRIx64 " -> 0x%016" in helper_st_asi()
1749 PRIx64 "\n", env->immu.tsb, val); in helper_st_asi()
1750 env->immu.tsb = val; in helper_st_asi()
1753 env->immu.tag_access = val; in helper_st_asi()
1763 if (oldreg != env->immu.mmuregs[reg]) { in helper_st_asi()
1764 DPRINTF_MMU("immu change reg[%d]: 0x%016" PRIx64 " -> 0x%016" in helper_st_asi()
1765 PRIx64 "\n", reg, oldreg, env->immuregs[reg]); in helper_st_asi()
1772 case ASI_ITLB_DATA_IN: /* I-MMU data in */ in helper_st_asi()
1775 replace_tlb_1bit_lru(env->itlb, env->immu.tag_access, in helper_st_asi()
1779 case ASI_ITLB_DATA_ACCESS: /* I-MMU data access */ in helper_st_asi()
1787 replace_tlb_entry(&env->itlb[i], env->immu.tag_access, in helper_st_asi()
1796 case ASI_IMMU_DEMAP: /* I-MMU demap */ in helper_st_asi()
1797 demap_tlb(env->itlb, addr, "immu", env); in helper_st_asi()
1799 case ASI_DMMU: /* D-MMU regs */ in helper_st_asi()
1804 oldreg = env->dmmu.mmuregs[reg]; in helper_st_asi()
1812 env->dmmu.sfar = 0; in helper_st_asi()
1814 env->dmmu.sfsr = val; in helper_st_asi()
1817 env->dmmu.mmu_primary_context = val; in helper_st_asi()
1823 env->dmmu.mmu_secondary_context = val; in helper_st_asi()
1829 DPRINTF_MMU("dmmu TSB write: 0x%016" PRIx64 " -> 0x%016" in helper_st_asi()
1830 PRIx64 "\n", env->dmmu.tsb, val); in helper_st_asi()
1831 env->dmmu.tsb = val; in helper_st_asi()
1834 env->dmmu.tag_access = val; in helper_st_asi()
1837 env->dmmu.virtual_watchpoint = val; in helper_st_asi()
1840 env->dmmu.physical_watchpoint = val; in helper_st_asi()
1847 if (oldreg != env->dmmu.mmuregs[reg]) { in helper_st_asi()
1848 DPRINTF_MMU("dmmu change reg[%d]: 0x%016" PRIx64 " -> 0x%016" in helper_st_asi()
1849 PRIx64 "\n", reg, oldreg, env->dmmuregs[reg]); in helper_st_asi()
1856 case ASI_DTLB_DATA_IN: /* D-MMU data in */ in helper_st_asi()
1859 replace_tlb_1bit_lru(env->dtlb, env->dmmu.tag_access, in helper_st_asi()
1863 case ASI_DTLB_DATA_ACCESS: /* D-MMU data access */ in helper_st_asi()
1869 replace_tlb_entry(&env->dtlb[i], env->dmmu.tag_access, in helper_st_asi()
1878 case ASI_DMMU_DEMAP: /* D-MMU demap */ in helper_st_asi()
1879 demap_tlb(env->dtlb, addr, "dmmu", env); in helper_st_asi()
1882 env->ivec_status = val & 0x20; in helper_st_asi()
1893 env->scratch[i] = val; in helper_st_asi()
1900 env->dmmu.mmu_primary_context = val; in helper_st_asi()
1901 env->immu.mmu_primary_context = val; in helper_st_asi()
1906 env->dmmu.mmu_secondary_context = val; in helper_st_asi()
1907 env->immu.mmu_secondary_context = val; in helper_st_asi()
1918 case ASI_DCACHE_DATA: /* D-cache data */ in helper_st_asi()
1919 case ASI_DCACHE_TAG: /* D-cache tag access */ in helper_st_asi()
1920 case ASI_ESTATE_ERROR_EN: /* E-cache error enable */ in helper_st_asi()
1921 case ASI_AFSR: /* E-cache asynchronous fault status */ in helper_st_asi()
1922 case ASI_AFAR: /* E-cache asynchronous fault address */ in helper_st_asi()
1923 case ASI_EC_TAG_DATA: /* E-cache tag data */ in helper_st_asi()
1924 case ASI_IC_INSTR: /* I-cache instruction access */ in helper_st_asi()
1925 case ASI_IC_TAG: /* I-cache tag access */ in helper_st_asi()
1926 case ASI_IC_PRE_DECODE: /* I-cache predecode */ in helper_st_asi()
1927 case ASI_IC_NEXT_FIELD: /* I-cache LRU etc. */ in helper_st_asi()
1928 case ASI_EC_W: /* E-cache tag */ in helper_st_asi()
1929 case ASI_EC_R: /* E-cache tag */ in helper_st_asi()
1931 case ASI_IMMU_TSB_8KB_PTR: /* I-MMU 8k TSB pointer, RO */ in helper_st_asi()
1932 case ASI_IMMU_TSB_64KB_PTR: /* I-MMU 64k TSB pointer, RO */ in helper_st_asi()
1933 case ASI_ITLB_TAG_READ: /* I-MMU tag read, RO */ in helper_st_asi()
1934 case ASI_DMMU_TSB_8KB_PTR: /* D-MMU 8k TSB pointer, RO */ in helper_st_asi()
1935 case ASI_DMMU_TSB_64KB_PTR: /* D-MMU 64k TSB pointer, RO */ in helper_st_asi()
1936 case ASI_DMMU_TSB_DIRECT_PTR: /* D-MMU data pointer, RO */ in helper_st_asi()
1937 case ASI_DTLB_TAG_READ: /* D-MMU tag read, RO */ in helper_st_asi()
1940 case ASI_PNF: /* Primary no-fault, RO */ in helper_st_asi()
1941 case ASI_SNF: /* Secondary no-fault, RO */ in helper_st_asi()
1942 case ASI_PNFL: /* Primary no-fault LE, RO */ in helper_st_asi()
1943 case ASI_SNFL: /* Secondary no-fault LE, RO */ in helper_st_asi()