Lines Matching +full:write +full:- +full:assist
33 #include "s390x-internal.h"
34 #include "tcg/tcg-op.h"
35 #include "tcg/tcg-op-gvec.h"
37 #include "qemu/host-utils.h"
38 #include "exec/helper-proto.h"
39 #include "exec/helper-gen.h"
42 #include "exec/translation-block.h"
47 #include "exec/helper-info.c.inc"
146 * to be executed after base.pc_next - e.g. next sequential instruction
172 if (s->base.tb->flags & FLAG_MASK_32) { in pc_to_link_info()
173 if (s->base.tb->flags & FLAG_MASK_64) { in pc_to_link_info()
179 assert(!(s->base.tb->flags & FLAG_MASK_64)); in pc_to_link_info()
234 /* Convert element size (es) - e.g. MO_8 - to bytes */ in vec_reg_offset()
243 * B: [ 0][ 1][ 2][ 3][ 4][ 5][ 6][ 7] - [ 8][ 9][10][11][12][13][14][15] in vec_reg_offset()
244 * HW: [ 0][ 1][ 2][ 3] - [ 4][ 5][ 6][ 7] in vec_reg_offset()
245 * W: [ 0][ 1] - [ 2][ 3] in vec_reg_offset()
246 * DW: [ 0] - [ 1] in vec_reg_offset()
249 * B: [ 7][ 6][ 5][ 4][ 3][ 2][ 1][ 0] - [15][14][13][12][11][10][ 9][ 8] in vec_reg_offset()
250 * HW: [ 3][ 2][ 1][ 0] - [ 7][ 6][ 5][ 4] in vec_reg_offset()
251 * W: [ 1][ 0] - [ 3][ 2] in vec_reg_offset()
252 * DW: [ 0] - [ 1] in vec_reg_offset()
262 offs ^= (8 - bytes); in vec_reg_offset()
341 tcg_gen_movi_i64(psw_addr, s->base.pc_next); in update_psw_addr()
347 if (s->base.tb->flags & FLAG_MASK_PER_BRANCH) { in per_branch()
348 gen_helper_per_branch(tcg_env, dest, tcg_constant_i32(s->ilen)); in per_branch()
355 tcg_gen_movi_i64(gbea, s->base.pc_next); in per_breaking_event()
360 if (s->cc_op != CC_OP_DYNAMIC && s->cc_op != CC_OP_STATIC) { in update_cc_op()
361 tcg_gen_movi_i32(cc_op, s->cc_op); in update_cc_op()
368 return (uint64_t)translator_lduw(env, &s->base, pc); in ld_code2()
374 return (uint64_t)(uint32_t)translator_ldl(env, &s->base, pc); in ld_code4()
382 if (!(s->base.tb->flags & FLAG_MASK_DAT)) { in get_mem_index()
386 switch (s->base.tb->flags & FLAG_MASK_ASC) { in get_mem_index()
410 tcg_gen_st_i32(tcg_constant_i32(s->ilen), tcg_env, in gen_program_exception()
443 if (!(s->base.tb->flags & FLAG_MASK_64)) { in gen_addi_and_wrap_i64()
444 if (s->base.tb->flags & FLAG_MASK_32) { in gen_addi_and_wrap_i64()
467 } else if (!(s->base.tb->flags & FLAG_MASK_64)) { in get_address()
468 if (s->base.tb->flags & FLAG_MASK_32) { in get_address()
482 return (s->cc_op != CC_OP_DYNAMIC in live_cc_data()
483 && s->cc_op != CC_OP_STATIC in live_cc_data()
484 && s->cc_op > 3); in live_cc_data()
494 s->cc_op = CC_OP_CONST0 + val; in gen_op_movi_cc()
504 s->cc_op = op; in gen_op_update1_cc_i64()
515 s->cc_op = op; in gen_op_update2_cc_i64()
524 s->cc_op = op; in gen_op_update3_cc_i64()
532 /* CC value is in env->cc_op */
540 s->cc_op = CC_OP_STATIC; in set_cc_static()
549 switch (s->cc_op) { in gen_op_calc_cc()
557 local_cc_op = tcg_constant_i32(s->cc_op); in gen_op_calc_cc()
568 switch (s->cc_op) { in gen_op_calc_cc()
573 /* s->cc_op is the cc value */ in gen_op_calc_cc()
574 tcg_gen_movi_i32(cc_op, s->cc_op - CC_OP_CONST0); in gen_op_calc_cc()
577 /* env->cc_op already is the cc value */ in gen_op_calc_cc()
623 /* unknown operation - assume 3 arguments and cc_op in env */ in gen_op_calc_cc()
636 return translator_use_goto_tb(&s->base, dest); in use_goto_tb()
679 /* Interpret MASK in terms of S->CC_OP, and fill in C with all the
684 enum cc_op old_cc_op = s->cc_op; in disas_jcc()
687 c->cond = (mask ? TCG_COND_ALWAYS : TCG_COND_NEVER); in disas_jcc()
688 c->u.s32.a = cc_op; in disas_jcc()
689 c->u.s32.b = cc_op; in disas_jcc()
690 c->is_64 = false; in disas_jcc()
756 case 8: /* src == 0 -> no one bit found */ in disas_jcc()
759 case 2: /* src != 0 -> one bit found */ in disas_jcc()
805 c->is_64 = true; in disas_jcc()
808 c->is_64 = false; in disas_jcc()
809 c->u.s32.a = tcg_temp_new_i32(); in disas_jcc()
810 tcg_gen_extrl_i64_i32(c->u.s32.a, cc_dst); in disas_jcc()
811 c->u.s32.b = tcg_constant_i32(0); in disas_jcc()
815 c->is_64 = false; in disas_jcc()
816 c->u.s32.a = tcg_temp_new_i32(); in disas_jcc()
817 tcg_gen_extrl_i64_i32(c->u.s32.a, cc_src); in disas_jcc()
818 c->u.s32.b = tcg_temp_new_i32(); in disas_jcc()
819 tcg_gen_extrl_i64_i32(c->u.s32.b, cc_dst); in disas_jcc()
825 c->u.s64.a = cc_dst; in disas_jcc()
826 c->u.s64.b = tcg_constant_i64(0); in disas_jcc()
834 c->u.s64.a = cc_src; in disas_jcc()
835 c->u.s64.b = cc_dst; in disas_jcc()
840 c->is_64 = true; in disas_jcc()
841 c->u.s64.b = tcg_constant_i64(0); in disas_jcc()
845 c->u.s64.a = cc_dst; in disas_jcc()
849 c->u.s64.a = cc_src; in disas_jcc()
857 c->is_64 = false; in disas_jcc()
858 c->u.s32.a = cc_op; in disas_jcc()
864 c->u.s32.b = tcg_constant_i32(3); in disas_jcc()
868 c->u.s32.b = tcg_constant_i32(2); in disas_jcc()
872 c->u.s32.b = tcg_constant_i32(1); in disas_jcc()
876 c->u.s32.b = tcg_constant_i32(1); in disas_jcc()
880 c->u.s32.b = tcg_constant_i32(1); in disas_jcc()
882 case 0x4 | 0x2: /* cc == 1 || cc == 2 => (cc - 1) <= 1 */ in disas_jcc()
884 c->u.s32.a = tcg_temp_new_i32(); in disas_jcc()
885 c->u.s32.b = tcg_constant_i32(1); in disas_jcc()
886 tcg_gen_addi_i32(c->u.s32.a, cc_op, -1); in disas_jcc()
890 c->u.s32.b = tcg_constant_i32(0); in disas_jcc()
904 c->cond = cond; in disas_jcc()
918 #include "insn-format.h.inc"
935 return (s->fields.presentO >> c) & 1; in have_field1()
942 return s->fields.c[c]; in get_field1()
983 #include "insn-format.h.inc"
1054 /* Pre-process arguments before HELP_OP. */
1060 * Post-process output after HELP_OP.
1081 if (dest == s->pc_tmp) { in help_goto_direct()
1087 tcg_gen_exit_tb(s->base.tb, 0); in help_goto_direct()
1107 uint64_t dest = s->base.pc_next + (int64_t)imm * 2; in help_branch()
1111 if (c->cond == TCG_COND_NEVER) { in help_branch()
1119 if (c->cond == TCG_COND_ALWAYS in help_branch()
1120 || (dest == s->pc_tmp && in help_branch()
1121 !(s->base.tb->flags & FLAG_MASK_PER_BRANCH))) { in help_branch()
1126 /* E.g. bcr %r0 -> no branch. */ in help_branch()
1129 if (c->cond == TCG_COND_ALWAYS) { in help_branch()
1137 * Ensure the taken branch is fall-through of the tcg branch. in help_branch()
1142 if (c->is_64) { in help_branch()
1143 tcg_gen_brcond_i64(tcg_invert_cond(c->cond), in help_branch()
1144 c->u.s64.a, c->u.s64.b, lab); in help_branch()
1146 tcg_gen_brcond_i32(tcg_invert_cond(c->cond), in help_branch()
1147 c->u.s32.a, c->u.s32.b, lab); in help_branch()
1161 tcg_gen_exit_tb(s->base.tb, 0); in help_branch()
1169 tcg_gen_movi_i64(psw_addr, s->pc_tmp); in help_branch()
1170 if (use_goto_tb(s, s->pc_tmp)) { in help_branch()
1172 tcg_gen_exit_tb(s->base.tb, 1); in help_branch()
1184 tcg_gen_abs_i64(o->out, o->in2); in op_abs()
1190 tcg_gen_andi_i64(o->out, o->in2, 0x7fffffffull); in op_absf32()
1196 tcg_gen_andi_i64(o->out, o->in2, 0x7fffffffffffffffull); in op_absf64()
1202 tcg_gen_andi_i64(o->out, o->in1, 0x7fffffffffffffffull); in op_absf128()
1203 tcg_gen_mov_i64(o->out2, o->in2); in op_absf128()
1209 tcg_gen_add_i64(o->out, o->in1, o->in2); in op_add()
1216 tcg_gen_add2_i64(o->out, cc_src, o->in1, cc_src, o->in2, cc_src); in op_addu64()
1223 switch (s->cc_op) { in compute_carry()
1244 tcg_gen_add_i64(o->out, o->in1, o->in2); in op_addc32()
1245 tcg_gen_add_i64(o->out, o->out, cc_src); in op_addc32()
1252 tcg_gen_addcio_i64(o->out, cc_src, o->in1, o->in2, cc_src); in op_addc64()
1260 o->in1 = tcg_temp_new_i64(); in op_asi()
1262 tcg_gen_qemu_ld_tl(o->in1, o->addr1, get_mem_index(s), s->insn->data); in op_asi()
1265 tcg_gen_atomic_fetch_add_i64(o->in1, o->addr1, o->in2, get_mem_index(s), in op_asi()
1266 s->insn->data); in op_asi()
1270 tcg_gen_add_i64(o->out, o->in1, o->in2); in op_asi()
1273 tcg_gen_qemu_st_tl(o->out, o->addr1, get_mem_index(s), s->insn->data); in op_asi()
1282 o->in1 = tcg_temp_new_i64(); in op_asiu64()
1284 tcg_gen_qemu_ld_tl(o->in1, o->addr1, get_mem_index(s), s->insn->data); in op_asiu64()
1287 tcg_gen_atomic_fetch_add_i64(o->in1, o->addr1, o->in2, get_mem_index(s), in op_asiu64()
1288 s->insn->data); in op_asiu64()
1293 tcg_gen_add2_i64(o->out, cc_src, o->in1, cc_src, o->in2, cc_src); in op_asiu64()
1296 tcg_gen_qemu_st_tl(o->out, o->addr1, get_mem_index(s), s->insn->data); in op_asiu64()
1303 gen_helper_aeb(o->out, tcg_env, o->in1, o->in2); in op_aeb()
1309 gen_helper_adb(o->out, tcg_env, o->in1, o->in2); in op_adb()
1315 gen_helper_axb(o->out_128, tcg_env, o->in1_128, o->in2_128); in op_axb()
1321 tcg_gen_and_i64(o->out, o->in1, o->in2); in op_and()
1327 int shift = s->insn->data & 0xff; in op_andi()
1328 int size = s->insn->data >> 8; in op_andi()
1329 uint64_t mask = ((1ull << size) - 1) << shift; in op_andi()
1332 tcg_gen_shli_i64(t, o->in2, shift); in op_andi()
1334 tcg_gen_and_i64(o->out, o->in1, t); in op_andi()
1337 tcg_gen_andi_i64(cc_dst, o->out, mask); in op_andi()
1344 tcg_gen_andc_i64(o->out, o->in1, o->in2); in op_andc()
1350 tcg_gen_orc_i64(o->out, o->in1, o->in2); in op_orc()
1356 tcg_gen_nand_i64(o->out, o->in1, o->in2); in op_nand()
1362 tcg_gen_nor_i64(o->out, o->in1, o->in2); in op_nor()
1368 tcg_gen_eqv_i64(o->out, o->in1, o->in2); in op_nxor()
1374 o->in1 = tcg_temp_new_i64(); in op_ni()
1377 tcg_gen_qemu_ld_tl(o->in1, o->addr1, get_mem_index(s), s->insn->data); in op_ni()
1380 tcg_gen_atomic_fetch_and_i64(o->in1, o->addr1, o->in2, get_mem_index(s), in op_ni()
1381 s->insn->data); in op_ni()
1385 tcg_gen_and_i64(o->out, o->in1, o->in2); in op_ni()
1388 tcg_gen_qemu_st_tl(o->out, o->addr1, get_mem_index(s), s->insn->data); in op_ni()
1395 pc_to_link_info(o->out, s, s->pc_tmp); in op_bas()
1396 if (o->in2) { in op_bas()
1397 return help_goto_indirect(s, o->in2); in op_bas()
1407 if (s->base.tb->flags & (FLAG_MASK_32 | FLAG_MASK_64)) { in save_link_info()
1408 pc_to_link_info(o->out, s, s->pc_tmp); in save_link_info()
1412 tcg_gen_andi_i64(o->out, o->out, 0xffffffff00000000ull); in save_link_info()
1413 tcg_gen_ori_i64(o->out, o->out, ((s->ilen / 2) << 30) | s->pc_tmp); in save_link_info()
1417 tcg_gen_or_i64(o->out, o->out, t); in save_link_info()
1420 tcg_gen_or_i64(o->out, o->out, t); in save_link_info()
1426 if (o->in2) { in op_bal()
1427 return help_goto_indirect(s, o->in2); in op_bal()
1437 * - bool IS_IMM reflects whether the target is fixed or computed. Non-EXECUTEd
1440 * - int IMM is the value of RI.
1441 * - TCGv_i64 CDEST is the address of the computed target.
1445 if (unlikely(s->ex_value)) { \
1465 pc_to_link_info(o->out, s, s->pc_tmp); in op_basi()
1467 disas_jdest(s, i2, is_imm, imm, o->in2); in op_basi()
1469 return help_branch(s, &c, is_imm, imm, o->in2); in op_basi()
1483 /* FIXME: check for fast-BCR-serialization facility */ in op_bc()
1488 /* FIXME: perform checkpoint-synchronisation */ in op_bc()
1494 disas_jdest(s, i2, is_imm, imm, o->in2); in op_bc()
1496 return help_branch(s, &c, is_imm, imm, o->in2); in op_bc()
1517 disas_jdest(s, i2, is_imm, imm, o->in2); in op_bct32()
1518 return help_branch(s, &c, is_imm, imm, o->in2); in op_bct32()
1539 return help_branch(s, &c, 1, imm, o->in2); in op_bcth()
1556 disas_jdest(s, i2, is_imm, imm, o->in2); in op_bct64()
1557 return help_branch(s, &c, is_imm, imm, o->in2); in op_bct64()
1569 c.cond = (s->insn->data ? TCG_COND_LE : TCG_COND_GT); in op_bx32()
1580 disas_jdest(s, i2, is_imm, imm, o->in2); in op_bx32()
1581 return help_branch(s, &c, is_imm, imm, o->in2); in op_bx32()
1592 c.cond = (s->insn->data ? TCG_COND_LE : TCG_COND_GT); in op_bx64()
1604 disas_jdest(s, i2, is_imm, imm, o->in2); in op_bx64()
1605 return help_branch(s, &c, is_imm, imm, o->in2); in op_bx64()
1615 if (s->insn->data) { in op_cj()
1619 c.u.s64.a = o->in1; in op_cj()
1620 c.u.s64.b = o->in2; in op_cj()
1622 o->out = NULL; in op_cj()
1623 disas_jdest(s, i4, is_imm, imm, o->out); in op_cj()
1624 if (!is_imm && !o->out) { in op_cj()
1626 o->out = get_address(s, 0, get_field(s, b4), in op_cj()
1630 return help_branch(s, &c, is_imm, imm, o->out); in op_cj()
1635 gen_helper_ceb(cc_op, tcg_env, o->in1, o->in2); in op_ceb()
1642 gen_helper_cdb(cc_op, tcg_env, o->in1, o->in2); in op_cdb()
1649 gen_helper_cxb(cc_op, tcg_env, o->in1_128, o->in2_128); in op_cxb()
1686 gen_helper_cfeb(o->out, tcg_env, o->in2, m34); in op_cfeb()
1698 gen_helper_cfdb(o->out, tcg_env, o->in2, m34); in op_cfdb()
1710 gen_helper_cfxb(o->out, tcg_env, o->in2_128, m34); in op_cfxb()
1722 gen_helper_cgeb(o->out, tcg_env, o->in2, m34); in op_cgeb()
1734 gen_helper_cgdb(o->out, tcg_env, o->in2, m34); in op_cgdb()
1746 gen_helper_cgxb(o->out, tcg_env, o->in2_128, m34); in op_cgxb()
1758 gen_helper_clfeb(o->out, tcg_env, o->in2, m34); in op_clfeb()
1770 gen_helper_clfdb(o->out, tcg_env, o->in2, m34); in op_clfdb()
1782 gen_helper_clfxb(o->out, tcg_env, o->in2_128, m34); in op_clfxb()
1794 gen_helper_clgeb(o->out, tcg_env, o->in2, m34); in op_clgeb()
1806 gen_helper_clgdb(o->out, tcg_env, o->in2, m34); in op_clgdb()
1818 gen_helper_clgxb(o->out, tcg_env, o->in2_128, m34); in op_clgxb()
1830 gen_helper_cegb(o->out, tcg_env, o->in2, m34); in op_cegb()
1841 gen_helper_cdgb(o->out, tcg_env, o->in2, m34); in op_cdgb()
1852 gen_helper_cxgb(o->out_128, tcg_env, o->in2, m34); in op_cxgb()
1863 gen_helper_celgb(o->out, tcg_env, o->in2, m34); in op_celgb()
1874 gen_helper_cdlgb(o->out, tcg_env, o->in2, m34); in op_cdlgb()
1885 gen_helper_cxlgb(o->out_128, tcg_env, o->in2, m34); in op_cxlgb()
1895 gen_helper_cksm(pair, tcg_env, o->in1, o->in2, regs[r2 + 1]); in op_cksm()
1897 tcg_gen_extr_i128_i64(o->out, len, pair); in op_cksm()
1920 tcg_gen_qemu_ld_tl(src, o->addr1, get_mem_index(s), mop); in op_clc()
1921 tcg_gen_qemu_ld_tl(cc_dst, o->in2, get_mem_index(s), mop); in op_clc()
1926 gen_helper_clc(cc_op, tcg_env, vl, o->addr1, o->in2); in op_clc()
1965 gen_helper_clcle(cc_op, tcg_env, t1, o->in2, t3); in op_clcle()
1984 gen_helper_clclu(cc_op, tcg_env, t1, o->in2, t3); in op_clclu()
1994 tcg_gen_extrl_i64_i32(t1, o->in1); in op_clm()
1995 gen_helper_clm(cc_op, tcg_env, t1, m3, o->in2); in op_clm()
2004 gen_helper_clst(pair, tcg_env, regs[0], o->in1, o->in2); in op_clst()
2005 tcg_gen_extr_i128_i64(o->in2, o->in1, pair); in op_clst()
2014 tcg_gen_andi_i64(t, o->in1, 0x8000000000000000ull); in op_cps()
2015 tcg_gen_andi_i64(o->out, o->in2, 0x7fffffffffffffffull); in op_cps()
2016 tcg_gen_or_i64(o->out, o->out, t); in op_cps()
2027 in2 = (zero-extended) R1 (expected value). */ in op_cs()
2030 tcg_gen_atomic_cmpxchg_i64(o->out, addr, o->in2, o->in1, in op_cs()
2031 get_mem_index(s), s->insn->data | MO_ALIGN); in op_cs()
2036 tcg_gen_setcond_i64(TCG_COND_NE, cc, o->in2, o->out); in op_cs()
2047 o->out_128 = tcg_temp_new_i128(); in op_cdsg()
2048 tcg_gen_concat_i64_i128(o->out_128, regs[r1 + 1], regs[r1]); in op_cdsg()
2051 tcg_gen_atomic_cmpxchg_i128(o->out_128, o->addr1, o->out_128, o->in2_128, in op_cdsg()
2058 tcg_gen_extr_i128_i64(cc_src, cc_dst, o->out_128); in op_cdsg()
2072 if (tb_cflags(s->base.tb) & CF_PARALLEL) { in op_csst()
2073 gen_helper_csst_parallel(cc_op, tcg_env, t_r3, o->addr1, o->in2); in op_csst()
2075 gen_helper_csst(cc_op, tcg_env, t_r3, o->addr1, o->in2); in op_csst()
2085 MemOp mop = s->insn->data; in op_csp()
2089 /* Note that in1 = R1 (zero-extended expected value), in op_csp()
2094 tcg_gen_andi_i64(addr, o->in2, -1ULL << (mop & MO_SIZE)); in op_csp()
2095 tcg_gen_atomic_cmpxchg_i64(old, addr, o->in1, o->out2, in op_csp()
2100 tcg_gen_setcond_i64(TCG_COND_NE, cc, o->in1, old); in op_csp()
2103 /* Write back the output now, so that it happens before the in op_csp()
2106 tcg_gen_deposit_i64(o->out, o->out, old, 0, 32); in op_csp()
2108 tcg_gen_mov_i64(o->out, old); in op_csp()
2114 tcg_gen_and_i64(cc, cc, o->in2); in op_csp()
2127 tcg_gen_qemu_ld_i64(t, o->addr1, get_mem_index(s), MO_TEUQ); in op_cvb()
2135 tcg_gen_qemu_ld_i128(t, o->addr1, get_mem_index(s), MO_TE | MO_128); in op_cvbg()
2136 gen_helper_cvbg(o->out, tcg_env, t); in op_cvbg()
2144 tcg_gen_extrl_i64_i32(t2, o->in1); in op_cvd()
2146 tcg_gen_qemu_st_i64(t1, o->in2, get_mem_index(s), MO_TEUQ); in op_cvd()
2153 gen_helper_cvdg(t, o->in1); in op_cvdg()
2154 tcg_gen_qemu_st_i128(t, o->in2, get_mem_index(s), MO_TE | MO_128); in op_cvdg()
2165 if (s->insn->data) { in op_ct()
2168 tcg_gen_brcond_i64(c, o->in1, o->in2, lab); in op_ct()
2197 switch (s->insn->data) { in op_cuXX()
2238 gen_helper_divs32(o->out, tcg_env, o->in1, o->in2); in op_divs32()
2239 tcg_gen_extr32_i64(o->out2, o->out, o->out); in op_divs32()
2245 gen_helper_divu32(o->out, tcg_env, o->in1, o->in2); in op_divu32()
2246 tcg_gen_extr32_i64(o->out2, o->out, o->out); in op_divu32()
2254 gen_helper_divs64(t, tcg_env, o->in1, o->in2); in op_divs64()
2255 tcg_gen_extr_i128_i64(o->out2, o->out, t); in op_divs64()
2263 gen_helper_divu64(t, tcg_env, o->out, o->out2, o->in2); in op_divu64()
2264 tcg_gen_extr_i128_i64(o->out2, o->out, t); in op_divu64()
2270 gen_helper_deb(o->out, tcg_env, o->in1, o->in2); in op_deb()
2276 gen_helper_ddb(o->out, tcg_env, o->in1, o->in2); in op_ddb()
2282 gen_helper_dxb(o->out_128, tcg_env, o->in1_128, o->in2_128); in op_dxb()
2289 tcg_gen_ld32u_i64(o->out, tcg_env, offsetof(CPUS390XState, aregs[r2])); in op_ear()
2296 tcg_gen_movi_i64(o->out, -1); in op_ecag()
2302 tcg_gen_ld32u_i64(o->out, tcg_env, offsetof(CPUS390XState, fpc)); in op_efpc()
2333 if (unlikely(s->ex_value)) { in op_ex()
2347 ilen = tcg_constant_i32(s->ilen); in op_ex()
2348 gen_helper_ex(tcg_env, ilen, v1, o->in2); in op_ex()
2360 gen_helper_fieb(o->out, tcg_env, o->in2, m34); in op_fieb()
2371 gen_helper_fidb(o->out, tcg_env, o->in2, m34); in op_fidb()
2382 gen_helper_fixb(o->out_128, tcg_env, o->in2_128, m34); in op_fixb()
2392 gen_op_update1_cc_i64(s, CC_OP_FLOGR, o->in2); in op_flogr()
2395 tcg_gen_clzi_i64(o->out, o->in2, 64); in op_flogr()
2400 tcg_gen_movi_i64(o->out2, 0x8000000000000000ull); in op_flogr()
2401 tcg_gen_shr_i64(o->out2, o->out2, o->out); in op_flogr()
2402 tcg_gen_andc_i64(o->out2, cc_dst, o->out2); in op_flogr()
2409 int pos, len, base = s->insn->data; in op_icm()
2415 /* Effectively a 32-bit load. */ in op_icm()
2416 tcg_gen_qemu_ld_i64(tmp, o->in2, get_mem_index(s), MO_TEUL); in op_icm()
2423 /* Effectively a 16-bit load. */ in op_icm()
2424 tcg_gen_qemu_ld_i64(tmp, o->in2, get_mem_index(s), MO_TEUW); in op_icm()
2432 /* Effectively an 8-bit load. */ in op_icm()
2433 tcg_gen_qemu_ld_i64(tmp, o->in2, get_mem_index(s), MO_UB); in op_icm()
2439 tcg_gen_deposit_i64(o->out, o->out, tmp, pos, len); in op_icm()
2440 ccm = ((1ull << len) - 1) << pos; in op_icm()
2445 tcg_gen_qemu_ld_i64(tmp, o->in2, get_mem_index(s), MO_UB); in op_icm()
2451 pos = base + 32 - 8; in op_icm()
2455 tcg_gen_qemu_ld_i64(tmp, o->in2, get_mem_index(s), MO_UB); in op_icm()
2456 tcg_gen_addi_i64(o->in2, o->in2, 1); in op_icm()
2457 tcg_gen_deposit_i64(o->out, o->out, tmp, pos, 8); in op_icm()
2461 pos -= 8; in op_icm()
2467 gen_op_update2_cc_i64(s, CC_OP_ICM, tmp, o->out); in op_icm()
2473 int shift = s->insn->data & 0xff; in op_insi()
2474 int size = s->insn->data >> 8; in op_insi()
2475 tcg_gen_deposit_i64(o->out, o->in1, o->in2, shift, size); in op_insi()
2489 tcg_gen_deposit_i64(o->out, o->out, t1, 24, 8); in op_ipm()
2503 gen_helper_idte(tcg_env, o->in1, o->in2, m4); in op_idte()
2516 gen_helper_ipte(tcg_env, o->in1, o->in2, m4); in op_ipte()
2522 gen_helper_iske(o->out, tcg_env, o->in2); in op_iske()
2534 switch (s->insn->data) { in op_msa()
2575 type = tcg_constant_i32(s->insn->data); in op_msa()
2583 gen_helper_keb(cc_op, tcg_env, o->in1, o->in2); in op_keb()
2590 gen_helper_kdb(cc_op, tcg_env, o->in1, o->in2); in op_kdb()
2597 gen_helper_kxb(cc_op, tcg_env, o->in1_128, o->in2_128); in op_kxb()
2606 tcg_gen_atomic_fetch_add_i64(o->in2, o->in2, o->in1, get_mem_index(s), in help_laa()
2607 s->insn->data | MO_ALIGN); in help_laa()
2611 tcg_gen_add2_i64(o->out, cc_src, o->in1, cc_src, o->in2, cc_src); in help_laa()
2613 tcg_gen_add_i64(o->out, o->in1, o->in2); in help_laa()
2632 tcg_gen_atomic_fetch_and_i64(o->in2, o->in2, o->in1, get_mem_index(s), in op_lan()
2633 s->insn->data | MO_ALIGN); in op_lan()
2635 tcg_gen_and_i64(o->out, o->in1, o->in2); in op_lan()
2643 tcg_gen_atomic_fetch_or_i64(o->in2, o->in2, o->in1, get_mem_index(s), in op_lao()
2644 s->insn->data | MO_ALIGN); in op_lao()
2646 tcg_gen_or_i64(o->out, o->in1, o->in2); in op_lao()
2654 tcg_gen_atomic_fetch_xor_i64(o->in2, o->in2, o->in1, get_mem_index(s), in op_lax()
2655 s->insn->data | MO_ALIGN); in op_lax()
2657 tcg_gen_xor_i64(o->out, o->in1, o->in2); in op_lax()
2663 gen_helper_ldeb(o->out, tcg_env, o->in2); in op_ldeb()
2674 gen_helper_ledb(o->out, tcg_env, o->in2, m34); in op_ledb()
2685 gen_helper_ldxb(o->out, tcg_env, o->in2_128, m34); in op_ldxb()
2696 gen_helper_lexb(o->out, tcg_env, o->in2_128, m34); in op_lexb()
2702 gen_helper_lxdb(o->out_128, tcg_env, o->in2); in op_lxdb()
2708 gen_helper_lxeb(o->out_128, tcg_env, o->in2); in op_lxeb()
2714 tcg_gen_shli_i64(o->out, o->in2, 32); in op_lde()
2720 tcg_gen_andi_i64(o->out, o->in2, 0x7fffffff); in op_llgt()
2726 tcg_gen_qemu_ld_i64(o->out, o->in2, get_mem_index(s), MO_SB); in op_ld8s()
2732 tcg_gen_qemu_ld_i64(o->out, o->in2, get_mem_index(s), MO_UB); in op_ld8u()
2738 tcg_gen_qemu_ld_i64(o->out, o->in2, get_mem_index(s), MO_TESW); in op_ld16s()
2744 tcg_gen_qemu_ld_i64(o->out, o->in2, get_mem_index(s), MO_TEUW); in op_ld16u()
2750 tcg_gen_qemu_ld_tl(o->out, o->in2, get_mem_index(s), in op_ld32s()
2751 MO_TESL | s->insn->data); in op_ld32s()
2757 tcg_gen_qemu_ld_tl(o->out, o->in2, get_mem_index(s), in op_ld32u()
2758 MO_TEUL | s->insn->data); in op_ld32u()
2764 tcg_gen_qemu_ld_i64(o->out, o->in2, get_mem_index(s), in op_ld64()
2765 MO_TEUQ | s->insn->data); in op_ld64()
2772 store_reg32_i64(get_field(s, r1), o->in2); in op_lat()
2774 tcg_gen_brcondi_i64(TCG_COND_NE, o->in2, 0, lab); in op_lat()
2783 tcg_gen_qemu_ld_i64(o->out, o->in2, get_mem_index(s), MO_TEUQ); in op_lgat()
2785 tcg_gen_brcondi_i64(TCG_COND_NE, o->out, 0, lab); in op_lgat()
2794 store_reg32h_i64(get_field(s, r1), o->in2); in op_lfhat()
2796 tcg_gen_brcondi_i64(TCG_COND_NE, o->in2, 0, lab); in op_lfhat()
2806 tcg_gen_qemu_ld_i64(o->out, o->in2, get_mem_index(s), MO_TEUL); in op_llgfat()
2808 tcg_gen_brcondi_i64(TCG_COND_NE, o->out, 0, lab); in op_llgfat()
2817 tcg_gen_andi_i64(o->out, o->in2, 0x7fffffff); in op_llgtat()
2819 tcg_gen_brcondi_i64(TCG_COND_NE, o->out, 0, lab); in op_llgtat()
2838 tcg_gen_movcond_i64(c.cond, o->out, c.u.s64.a, c.u.s64.b, in op_loc()
2839 o->in2, o->in1); in op_loc()
2850 tcg_gen_movcond_i64(TCG_COND_NE, o->out, t, z, o->in2, o->in1); in op_loc()
2862 gen_helper_lctl(tcg_env, r1, o->in2, r3); in op_lctl()
2864 s->exit_to_mainloop = true; in op_lctl()
2873 gen_helper_lctlg(tcg_env, r1, o->in2, r3); in op_lctlg()
2875 s->exit_to_mainloop = true; in op_lctlg()
2881 gen_helper_lra(o->out, tcg_env, o->out, o->in2); in op_lra()
2888 tcg_gen_st_i64(o->in2, tcg_env, offsetof(CPUS390XState, pp)); in op_lpp()
2904 tcg_gen_qemu_ld_i64(mask, o->in2, get_mem_index(s), MO_TEUQ | MO_ALIGN_8); in op_lpsw()
2920 tcg_gen_qemu_ld_i64(t1, o->in2, get_mem_index(s), in op_lpswe()
2922 tcg_gen_addi_i64(o->in2, o->in2, 8); in op_lpswe()
2923 tcg_gen_qemu_ld_i64(t2, o->in2, get_mem_index(s), MO_TEUQ); in op_lpswe()
2934 gen_helper_lam(tcg_env, r1, o->in2, r3); in op_lam()
2947 tcg_gen_qemu_ld_i64(t1, o->in2, get_mem_index(s), MO_TEUL); in op_lm32()
2955 tcg_gen_qemu_ld_i64(t1, o->in2, get_mem_index(s), MO_TEUL); in op_lm32()
2956 tcg_gen_addi_i64(t2, o->in2, 4 * ((r3 - r1) & 15)); in op_lm32()
2967 r3 = (r3 - 1) & 15; in op_lm32()
2971 tcg_gen_add_i64(o->in2, o->in2, t2); in op_lm32()
2972 tcg_gen_qemu_ld_i64(t1, o->in2, get_mem_index(s), MO_TEUL); in op_lm32()
2987 tcg_gen_qemu_ld_i64(t1, o->in2, get_mem_index(s), MO_TEUL); in op_lmh()
2995 tcg_gen_qemu_ld_i64(t1, o->in2, get_mem_index(s), MO_TEUL); in op_lmh()
2996 tcg_gen_addi_i64(t2, o->in2, 4 * ((r3 - r1) & 15)); in op_lmh()
3007 r3 = (r3 - 1) & 15; in op_lmh()
3011 tcg_gen_add_i64(o->in2, o->in2, t2); in op_lmh()
3012 tcg_gen_qemu_ld_i64(t1, o->in2, get_mem_index(s), MO_TEUL); in op_lmh()
3026 tcg_gen_qemu_ld_i64(regs[r1], o->in2, get_mem_index(s), MO_TEUQ); in op_lm64()
3034 tcg_gen_qemu_ld_i64(t1, o->in2, get_mem_index(s), MO_TEUQ); in op_lm64()
3035 tcg_gen_addi_i64(t2, o->in2, 8 * ((r3 - r1) & 15)); in op_lm64()
3045 r3 = (r3 - 1) & 15; in op_lm64()
3049 tcg_gen_add_i64(o->in2, o->in2, t1); in op_lm64()
3050 tcg_gen_qemu_ld_i64(regs[r1], o->in2, get_mem_index(s), MO_TEUQ); in op_lm64()
3058 MemOp mop = s->insn->data; in op_lpd()
3061 if (tb_cflags(s->base.tb) & CF_PARALLEL) { in op_lpd()
3071 tcg_gen_qemu_ld_i64(o->out, a1, get_mem_index(s), mop | MO_ALIGN); in op_lpd()
3072 tcg_gen_qemu_ld_i64(o->out2, a2, get_mem_index(s), mop | MO_ALIGN); in op_lpd()
3081 o->out_128 = tcg_temp_new_i128(); in op_lpq()
3082 tcg_gen_qemu_ld_i128(o->out_128, o->in2, get_mem_index(s), in op_lpq()
3090 tcg_gen_qemu_ld_tl(o->out, o->in2, MMU_REAL_IDX, s->insn->data); in op_lura()
3097 tcg_gen_andi_i64(o->out, o->in2, -256); in op_lzrb()
3110 tcg_gen_ori_i64(o->addr1, o->addr1, -block_size); in op_lcbb()
3111 tcg_gen_neg_i64(o->addr1, o->addr1); in op_lcbb()
3112 tcg_gen_movi_i64(o->out, 16); in op_lcbb()
3113 tcg_gen_umin_i64(o->out, o->out, o->addr1); in op_lcbb()
3114 gen_op_update1_cc_i64(s, CC_OP_LCBB, o->out); in op_lcbb()
3128 gen_helper_monitor_call(tcg_env, o->addr1, in op_mc()
3137 o->out = o->in2; in op_mov2()
3138 o->in2 = NULL; in op_mov2()
3148 o->out = o->in2; in op_mov2e()
3149 o->in2 = NULL; in op_mov2e()
3151 switch (s->base.tb->flags & FLAG_MASK_ASC) { in op_mov2e()
3176 o->out = o->in1; in op_movx()
3177 o->out2 = o->in2; in op_movx()
3178 o->in1 = NULL; in op_movx()
3179 o->in2 = NULL; in op_movx()
3187 gen_helper_mvc(tcg_env, l, o->addr1, o->in2); in op_mvc()
3193 gen_helper_mvcrl(tcg_env, regs[0], o->addr1, o->in2); in op_mvcrl()
3201 gen_helper_mvcin(tcg_env, l, o->addr1, o->in2); in op_mvcin()
3238 gen_helper_mvcle(cc_op, tcg_env, t1, o->in2, t3); in op_mvcle()
3257 gen_helper_mvclu(cc_op, tcg_env, t1, o->in2, t3); in op_mvclu()
3265 gen_helper_mvcos(cc_op, tcg_env, o->addr1, o->in2, regs[r3]); in op_mvcos()
3275 gen_helper_mvcp(cc_op, tcg_env, regs[r1], o->addr1, o->in2, regs[r3]); in op_mvcp()
3284 gen_helper_mvcs(cc_op, tcg_env, regs[r1], o->addr1, o->in2, regs[r3]); in op_mvcs()
3294 gen_helper_mvn(tcg_env, l, o->addr1, o->in2); in op_mvn()
3302 gen_helper_mvo(tcg_env, l, o->addr1, o->in2); in op_mvo()
3330 gen_helper_mvz(tcg_env, l, o->addr1, o->in2); in op_mvz()
3336 tcg_gen_mul_i64(o->out, o->in1, o->in2); in op_mul()
3342 tcg_gen_mulu2_i64(o->out2, o->out, o->in1, o->in2); in op_mul128()
3348 tcg_gen_muls2_i64(o->out2, o->out, o->in1, o->in2); in op_muls128()
3354 gen_helper_meeb(o->out, tcg_env, o->in1, o->in2); in op_meeb()
3360 gen_helper_mdeb(o->out, tcg_env, o->in1, o->in2); in op_mdeb()
3366 gen_helper_mdb(o->out, tcg_env, o->in1, o->in2); in op_mdb()
3372 gen_helper_mxb(o->out_128, tcg_env, o->in1_128, o->in2_128); in op_mxb()
3378 gen_helper_mxdb(o->out_128, tcg_env, o->in1, o->in2); in op_mxdb()
3385 gen_helper_maeb(o->out, tcg_env, o->in1, o->in2, r3); in op_maeb()
3392 gen_helper_madb(o->out, tcg_env, o->in1, o->in2, r3); in op_madb()
3399 gen_helper_mseb(o->out, tcg_env, o->in1, o->in2, r3); in op_mseb()
3406 gen_helper_msdb(o->out, tcg_env, o->in1, o->in2, r3); in op_msdb()
3415 tcg_gen_neg_i64(n, o->in2); in op_nabs()
3416 tcg_gen_movcond_i64(TCG_COND_GE, o->out, o->in2, z, n, o->in2); in op_nabs()
3422 tcg_gen_ori_i64(o->out, o->in2, 0x80000000ull); in op_nabsf32()
3428 tcg_gen_ori_i64(o->out, o->in2, 0x8000000000000000ull); in op_nabsf64()
3434 tcg_gen_ori_i64(o->out, o->in1, 0x8000000000000000ull); in op_nabsf128()
3435 tcg_gen_mov_i64(o->out2, o->in2); in op_nabsf128()
3443 gen_helper_nc(cc_op, tcg_env, l, o->addr1, o->in2); in op_nc()
3450 tcg_gen_neg_i64(o->out, o->in2); in op_neg()
3456 tcg_gen_xori_i64(o->out, o->in2, 0x80000000ull); in op_negf32()
3462 tcg_gen_xori_i64(o->out, o->in2, 0x8000000000000000ull); in op_negf64()
3468 tcg_gen_xori_i64(o->out, o->in1, 0x8000000000000000ull); in op_negf128()
3469 tcg_gen_mov_i64(o->out2, o->in2); in op_negf128()
3477 gen_helper_oc(cc_op, tcg_env, l, o->addr1, o->in2); in op_oc()
3484 tcg_gen_or_i64(o->out, o->in1, o->in2); in op_or()
3490 int shift = s->insn->data & 0xff; in op_ori()
3491 int size = s->insn->data >> 8; in op_ori()
3492 uint64_t mask = ((1ull << size) - 1) << shift; in op_ori()
3495 tcg_gen_shli_i64(t, o->in2, shift); in op_ori()
3496 tcg_gen_or_i64(o->out, o->in1, t); in op_ori()
3499 tcg_gen_andi_i64(cc_dst, o->out, mask); in op_ori()
3506 o->in1 = tcg_temp_new_i64(); in op_oi()
3509 tcg_gen_qemu_ld_tl(o->in1, o->addr1, get_mem_index(s), s->insn->data); in op_oi()
3512 tcg_gen_atomic_fetch_or_i64(o->in1, o->addr1, o->in2, get_mem_index(s), in op_oi()
3513 s->insn->data); in op_oi()
3517 tcg_gen_or_i64(o->out, o->in1, o->in2); in op_oi()
3520 tcg_gen_qemu_st_tl(o->out, o->addr1, get_mem_index(s), s->insn->data); in op_oi()
3529 gen_helper_pack(tcg_env, l, o->addr1, o->in2); in op_pack()
3544 gen_helper_pka(tcg_env, o->addr1, o->in2, l); in op_pka()
3559 gen_helper_pku(tcg_env, o->addr1, o->in2, l); in op_pku()
3568 tcg_gen_ctpop_i64(o->out, o->in2); in op_popcnt()
3570 gen_helper_popcnt(o->out, o->in2); in op_popcnt()
3593 switch (s->fields.op2) { in op_risbg()
3616 /* [0...i3---i4...63] */ in op_risbg()
3617 mask = (-1ull >> i3) & (-1ull << (63 - i4)); in op_risbg()
3619 /* [0---i4...i3---63] */ in op_risbg()
3620 mask = (-1ull >> i3) | (-1ull << (63 - i4)); in op_risbg()
3632 len = i4 - i3 + 1; in op_risbg()
3633 pos = 63 - i4; in op_risbg()
3638 tcg_gen_extract_i64(o->out, o->in2, 64 - rot, len); in op_risbg()
3646 rot = (rot - pos) & 63; in op_risbg()
3648 pos = -1; in op_risbg()
3652 tcg_gen_rotli_i64(o->in2, o->in2, rot); in op_risbg()
3657 tcg_gen_deposit_z_i64(o->out, o->in2, pos, len); in op_risbg()
3659 tcg_gen_deposit_i64(o->out, o->out, o->in2, pos, len); in op_risbg()
3662 tcg_gen_andi_i64(o->out, o->in2, mask); in op_risbg()
3664 tcg_gen_andi_i64(o->in2, o->in2, mask); in op_risbg()
3665 tcg_gen_andi_i64(o->out, o->out, imask); in op_risbg()
3666 tcg_gen_or_i64(o->out, o->out, o->in2); in op_risbg()
3679 /* If this is a test-only form, arrange to discard the result. */ in op_rosbg()
3681 tcg_debug_assert(o->out != NULL); in op_rosbg()
3682 orig_out = o->out; in op_rosbg()
3683 o->out = tcg_temp_new_i64(); in op_rosbg()
3684 tcg_gen_mov_i64(o->out, orig_out); in op_rosbg()
3701 tcg_gen_rotli_i64(o->in2, o->in2, i5); in op_rosbg()
3704 switch (s->fields.op2) { in op_rosbg()
3706 tcg_gen_ori_i64(o->in2, o->in2, ~mask); in op_rosbg()
3707 tcg_gen_and_i64(o->out, o->out, o->in2); in op_rosbg()
3710 tcg_gen_andi_i64(o->in2, o->in2, mask); in op_rosbg()
3711 tcg_gen_or_i64(o->out, o->out, o->in2); in op_rosbg()
3714 tcg_gen_andi_i64(o->in2, o->in2, mask); in op_rosbg()
3715 tcg_gen_xor_i64(o->out, o->out, o->in2); in op_rosbg()
3722 tcg_gen_andi_i64(cc_dst, o->out, mask); in op_rosbg()
3729 tcg_gen_bswap16_i64(o->out, o->in2, TCG_BSWAP_IZ | TCG_BSWAP_OZ); in op_rev16()
3735 tcg_gen_bswap32_i64(o->out, o->in2, TCG_BSWAP_IZ | TCG_BSWAP_OZ); in op_rev32()
3741 tcg_gen_bswap64_i64(o->out, o->in2); in op_rev64()
3750 tcg_gen_extrl_i64_i32(t1, o->in1); in op_rll32()
3751 tcg_gen_extrl_i64_i32(t2, o->in2); in op_rll32()
3753 tcg_gen_extu_i32_i64(o->out, to); in op_rll32()
3759 tcg_gen_rotl_i64(o->out, o->in1, o->in2); in op_rll64()
3766 gen_helper_rrbe(cc_op, tcg_env, o->in2); in op_rrbe()
3773 gen_helper_sacf(tcg_env, o->in2); in op_sacf()
3781 int sam = s->insn->data; in op_sam()
3793 mask = -1; in op_sam()
3800 if (s->base.pc_next & ~mask) { in op_sam()
3804 s->pc_tmp &= mask; in op_sam()
3816 tcg_gen_st32_i64(o->in2, tcg_env, offsetof(CPUS390XState, aregs[r1])); in op_sar()
3822 gen_helper_seb(o->out, tcg_env, o->in1, o->in2); in op_seb()
3828 gen_helper_sdb(o->out, tcg_env, o->in1, o->in2); in op_sdb()
3834 gen_helper_sxb(o->out_128, tcg_env, o->in1_128, o->in2_128); in op_sxb()
3840 gen_helper_sqeb(o->out, tcg_env, o->in2); in op_sqeb()
3846 gen_helper_sqdb(o->out, tcg_env, o->in2); in op_sqdb()
3852 gen_helper_sqxb(o->out_128, tcg_env, o->in2_128); in op_sqxb()
3859 gen_helper_servc(cc_op, tcg_env, o->in2, o->in1); in op_servc()
3869 gen_helper_sigp(cc_op, tcg_env, o->in2, r1, r3); in op_sigp()
3897 switch (s->insn->data) { in op_soc()
3920 uint64_t sign = 1ull << s->insn->data; in op_sla()
3921 if (s->insn->data == 31) { in op_sla()
3923 tcg_gen_shli_i64(t, o->in1, 32); in op_sla()
3925 t = o->in1; in op_sla()
3927 gen_op_update2_cc_i64(s, CC_OP_SLA, t, o->in2); in op_sla()
3928 tcg_gen_shl_i64(o->out, o->in1, o->in2); in op_sla()
3931 tcg_gen_andi_i64(o->out, o->out, ~sign); in op_sla()
3932 tcg_gen_andi_i64(o->in1, o->in1, sign); in op_sla()
3933 tcg_gen_or_i64(o->out, o->out, o->in1); in op_sla()
3939 tcg_gen_shl_i64(o->out, o->in1, o->in2); in op_sll()
3945 tcg_gen_sar_i64(o->out, o->in1, o->in2); in op_sra()
3951 tcg_gen_shr_i64(o->out, o->in1, o->in2); in op_srl()
3957 gen_helper_sfpc(tcg_env, o->in2); in op_sfpc()
3963 gen_helper_sfas(tcg_env, o->in2); in op_sfas()
3970 tcg_gen_andi_i64(o->addr1, o->addr1, 0x3ull); in op_srnm()
3971 gen_helper_srnm(tcg_env, o->addr1); in op_srnm()
3977 /* Bits 0-55 are are ignored. */ in op_srnmb()
3978 tcg_gen_andi_i64(o->addr1, o->addr1, 0xffull); in op_srnmb()
3979 gen_helper_srnm(tcg_env, o->addr1); in op_srnmb()
3987 /* Bits other than 61-63 are ignored. */ in op_srnmt()
3988 tcg_gen_andi_i64(o->addr1, o->addr1, 0x7ull); in op_srnmt()
3992 tcg_gen_deposit_i64(tmp, tmp, o->addr1, 4, 3); in op_srnmt()
3999 tcg_gen_extrl_i64_i32(cc_op, o->in1); in op_spm()
4003 tcg_gen_shri_i64(o->in1, o->in1, 24); in op_spm()
4004 tcg_gen_deposit_i64(psw_mask, psw_mask, o->in1, PSW_SHIFT_MASK_PM, 4); in op_spm()
4018 o->in1 = tcg_temp_new_i64(); in op_ectg()
4019 tcg_gen_addi_i64(o->in1, regs[b1], d1); in op_ectg()
4020 o->in2 = tcg_temp_new_i64(); in op_ectg()
4021 tcg_gen_addi_i64(o->in2, regs[b2], d2); in op_ectg()
4022 o->addr1 = tcg_temp_new_i64(); in op_ectg()
4023 gen_addi_and_wrap_i64(s, o->addr1, regs[r3], 0); in op_ectg()
4026 tcg_gen_qemu_ld_i64(regs[r3], o->addr1, get_mem_index(s), MO_TEUQ); in op_ectg()
4030 tcg_gen_sub_i64(regs[0], o->in1, tmp); in op_ectg()
4033 tcg_gen_mov_i64(regs[1], o->in2); in op_ectg()
4040 tcg_gen_shri_i64(o->in2, o->in2, 4); in op_spka()
4041 tcg_gen_deposit_i64(psw_mask, psw_mask, o->in2, PSW_SHIFT_KEY, 4); in op_spka()
4047 gen_helper_sske(tcg_env, o->in1, o->in2); in op_sske()
4064 tcg_gen_deposit_i64(psw_mask, psw_mask, o->in2, 56, 8); in op_ssm()
4069 s->exit_to_mainloop = true; in op_ssm()
4075 tcg_gen_ld32u_i64(o->out, tcg_env, offsetof(CPUS390XState, core_id)); in op_stap()
4082 gen_helper_stck(o->out, tcg_env); in op_stck()
4096 /* Shift the 64-bit value into its place as a zero-extended in op_stcke()
4097 104-bit value. Note that "bit positions 64-103 are always in op_stcke()
4098 non-zero so that they compare differently to STCK"; we set in op_stcke()
4104 tcg_gen_qemu_st_i64(c1, o->in2, get_mem_index(s), MO_TEUQ); in op_stcke()
4105 tcg_gen_addi_i64(o->in2, o->in2, 8); in op_stcke()
4106 tcg_gen_qemu_st_i64(c2, o->in2, get_mem_index(s), MO_TEUQ); in op_stcke()
4115 gen_helper_sck(cc_op, tcg_env, o->in2); in op_sck()
4122 gen_helper_sckc(tcg_env, o->in2); in op_sckc()
4134 gen_helper_stckc(o->out, tcg_env); in op_stckc()
4143 gen_helper_stctg(tcg_env, r1, o->in2, r3); in op_stctg()
4152 gen_helper_stctl(tcg_env, r1, o->in2, r3); in op_stctl()
4158 tcg_gen_ld_i64(o->out, tcg_env, offsetof(CPUS390XState, cpuid)); in op_stidp()
4164 gen_helper_spt(tcg_env, o->in2); in op_spt()
4176 gen_helper_stpt(o->out, tcg_env); in op_stpt()
4182 gen_helper_stsi(cc_op, tcg_env, o->in2, regs[0], regs[1]); in op_stsi()
4189 gen_helper_spx(tcg_env, o->in2); in op_spx()
4216 gen_helper_msch(tcg_env, regs[1], o->in2); in op_msch()
4243 gen_helper_schm(tcg_env, regs[1], regs[2], o->in2); in op_schm()
4262 gen_helper_ssch(tcg_env, regs[1], o->in2); in op_ssch()
4269 gen_helper_stsch(tcg_env, regs[1], o->in2); in op_stsch()
4276 gen_helper_stcrw(tcg_env, o->in2); in op_stcrw()
4283 gen_helper_tpi(cc_op, tcg_env, o->addr1); in op_tpi()
4290 gen_helper_tsch(tcg_env, regs[1], o->in2); in op_tsch()
4297 gen_helper_chsc(tcg_env, o->in2); in op_chsc()
4304 tcg_gen_ld_i64(o->out, tcg_env, offsetof(CPUS390XState, psa)); in op_stpx()
4305 tcg_gen_andi_i64(o->out, o->out, 0x7fffe000); in op_stpx()
4319 tcg_gen_qemu_st_i64(t, o->addr1, get_mem_index(s), MO_UB); in op_stnosm()
4321 if (s->fields.op == 0xac) { in op_stnosm()
4331 s->exit_to_mainloop = true; in op_stnosm()
4337 tcg_gen_qemu_st_tl(o->in1, o->in2, MMU_REAL_IDX, s->insn->data); in op_stura()
4339 if (s->base.tb->flags & FLAG_MASK_PER_STORE_REAL) { in op_stura()
4342 gen_helper_per_store_real(tcg_env, tcg_constant_i32(s->ilen)); in op_stura()
4351 gen_helper_stfle(cc_op, tcg_env, o->in2); in op_stfle()
4358 tcg_gen_qemu_st_i64(o->in1, o->in2, get_mem_index(s), MO_UB); in op_st8()
4364 tcg_gen_qemu_st_i64(o->in1, o->in2, get_mem_index(s), MO_TEUW); in op_st16()
4370 tcg_gen_qemu_st_tl(o->in1, o->in2, get_mem_index(s), in op_st32()
4371 MO_TEUL | s->insn->data); in op_st32()
4377 tcg_gen_qemu_st_i64(o->in1, o->in2, get_mem_index(s), in op_st64()
4378 MO_TEUQ | s->insn->data); in op_st64()
4387 gen_helper_stam(tcg_env, r1, o->in2, r3); in op_stam()
4394 int pos, base = s->insn->data; in op_stcm()
4400 /* Effectively a 32-bit store. */ in op_stcm()
4401 tcg_gen_shri_i64(tmp, o->in1, pos); in op_stcm()
4402 tcg_gen_qemu_st_i64(tmp, o->in2, get_mem_index(s), MO_TEUL); in op_stcm()
4408 /* Effectively a 16-bit store. */ in op_stcm()
4409 tcg_gen_shri_i64(tmp, o->in1, pos); in op_stcm()
4410 tcg_gen_qemu_st_i64(tmp, o->in2, get_mem_index(s), MO_TEUW); in op_stcm()
4417 /* Effectively an 8-bit store. */ in op_stcm()
4418 tcg_gen_shri_i64(tmp, o->in1, pos); in op_stcm()
4419 tcg_gen_qemu_st_i64(tmp, o->in2, get_mem_index(s), MO_UB); in op_stcm()
4424 pos = base + 32 - 8; in op_stcm()
4427 tcg_gen_shri_i64(tmp, o->in1, pos); in op_stcm()
4428 tcg_gen_qemu_st_i64(tmp, o->in2, get_mem_index(s), MO_UB); in op_stcm()
4429 tcg_gen_addi_i64(o->in2, o->in2, 1); in op_stcm()
4432 pos -= 8; in op_stcm()
4443 int size = s->insn->data; in op_stm()
4447 tcg_gen_qemu_st_i64(regs[r1], o->in2, get_mem_index(s), in op_stm()
4452 tcg_gen_add_i64(o->in2, o->in2, tsize); in op_stm()
4469 tcg_gen_qemu_st_i64(t, o->in2, get_mem_index(s), MO_TEUL); in op_stmh()
4473 tcg_gen_add_i64(o->in2, o->in2, t4); in op_stmh()
4483 tcg_gen_concat_i64_i128(t16, o->out2, o->out); in op_stpq()
4484 tcg_gen_qemu_st_i128(t16, o->in2, get_mem_index(s), in op_stpq()
4511 tcg_gen_sub_i64(o->out, o->in1, o->in2); in op_sub()
4518 tcg_gen_sub2_i64(o->out, cc_src, o->in1, cc_src, o->in2, cc_src); in op_subu64()
4522 /* Compute borrow (0, -1) into cc_src. */
4525 switch (s->cc_op) { in compute_borrow()
4527 /* The borrow value is already in cc_src (0,-1). */ in compute_borrow()
4538 /* Convert carry (1,0) to borrow (0,-1). */ in compute_borrow()
4548 /* Borrow is {0, -1}, so add to subtract. */ in op_subb32()
4549 tcg_gen_add_i64(o->out, o->in1, cc_src); in op_subb32()
4550 tcg_gen_sub_i64(o->out, o->out, o->in2); in op_subb32()
4559 * Borrow is {0, -1}, so add to subtract; replicate the in op_subb64()
4560 * borrow input to produce 128-bit -1 for the addition. in op_subb64()
4563 tcg_gen_add2_i64(o->out, cc_src, o->in1, zero, cc_src, cc_src); in op_subb64()
4564 tcg_gen_sub2_i64(o->out, cc_src, o->out, cc_src, o->in2, zero); in op_subb64()
4579 t = tcg_constant_i32(s->ilen); in op_svc()
4590 cc |= (s->base.tb->flags & FLAG_MASK_64) ? 2 : 0; in op_tam()
4591 cc |= (s->base.tb->flags & FLAG_MASK_32) ? 1 : 0; in op_tam()
4598 gen_helper_tceb(cc_op, tcg_env, o->in1, o->in2); in op_tceb()
4605 gen_helper_tcdb(cc_op, tcg_env, o->in1, o->in2); in op_tcdb()
4612 gen_helper_tcxb(cc_op, tcg_env, o->in1_128, o->in2); in op_tcxb()
4621 gen_helper_testblock(cc_op, tcg_env, o->in2); in op_testblock()
4628 gen_helper_tprot(cc_op, tcg_env, o->addr1, o->in2); in op_tprot()
4639 gen_helper_tp(cc_op, tcg_env, o->addr1, l1); in op_tp()
4648 gen_helper_tr(tcg_env, l, o->addr1, o->in2); in op_tr()
4657 gen_helper_tre(pair, tcg_env, o->out, o->out2, o->in2); in op_tre()
4658 tcg_gen_extr_i128_i64(o->out2, o->out, pair); in op_tre()
4667 gen_helper_trt(cc_op, tcg_env, l, o->addr1, o->in2); in op_trt()
4676 gen_helper_trtr(cc_op, tcg_env, l, o->addr1, o->in2); in op_trtr()
4685 TCGv_i32 sizes = tcg_constant_i32(s->insn->opc & 3); in op_trXX()
4693 tcg_gen_movi_i32(tst, -1); in op_trXX()
4696 if (s->insn->opc & 3) { in op_trXX()
4713 tcg_gen_atomic_xchg_i32(t1, o->in2, ff, get_mem_index(s), MO_UB); in op_ts()
4723 gen_helper_unpk(tcg_env, l, o->addr1, o->in2); in op_unpk()
4738 gen_helper_unpka(cc_op, tcg_env, o->addr1, l, o->in2); in op_unpka()
4754 gen_helper_unpku(cc_op, tcg_env, o->addr1, l, o->in2); in op_unpku()
4769 o->addr1 = get_address(s, 0, b1, d1); in op_xc()
4773 o->in2 = tcg_constant_i64(0); in op_xc()
4777 tcg_gen_qemu_st_i64(o->in2, o->addr1, get_mem_index(s), MO_UQ); in op_xc()
4778 l -= 8; in op_xc()
4780 tcg_gen_addi_i64(o->addr1, o->addr1, 8); in op_xc()
4784 tcg_gen_qemu_st_i64(o->in2, o->addr1, get_mem_index(s), MO_UL); in op_xc()
4785 l -= 4; in op_xc()
4787 tcg_gen_addi_i64(o->addr1, o->addr1, 4); in op_xc()
4791 tcg_gen_qemu_st_i64(o->in2, o->addr1, get_mem_index(s), MO_UW); in op_xc()
4792 l -= 2; in op_xc()
4794 tcg_gen_addi_i64(o->addr1, o->addr1, 2); in op_xc()
4798 tcg_gen_qemu_st_i64(o->in2, o->addr1, get_mem_index(s), MO_UB); in op_xc()
4805 o->in2 = get_address(s, 0, b2, d2); in op_xc()
4807 gen_helper_xc(cc_op, tcg_env, t32, o->addr1, o->in2); in op_xc()
4814 tcg_gen_xor_i64(o->out, o->in1, o->in2); in op_xor()
4820 int shift = s->insn->data & 0xff; in op_xori()
4821 int size = s->insn->data >> 8; in op_xori()
4822 uint64_t mask = ((1ull << size) - 1) << shift; in op_xori()
4825 tcg_gen_shli_i64(t, o->in2, shift); in op_xori()
4826 tcg_gen_xor_i64(o->out, o->in1, t); in op_xori()
4829 tcg_gen_andi_i64(cc_dst, o->out, mask); in op_xori()
4836 o->in1 = tcg_temp_new_i64(); in op_xi()
4839 tcg_gen_qemu_ld_tl(o->in1, o->addr1, get_mem_index(s), s->insn->data); in op_xi()
4842 tcg_gen_atomic_fetch_xor_i64(o->in1, o->addr1, o->in2, get_mem_index(s), in op_xi()
4843 s->insn->data); in op_xi()
4847 tcg_gen_xor_i64(o->out, o->in1, o->in2); in op_xi()
4850 tcg_gen_qemu_st_tl(o->out, o->addr1, get_mem_index(s), s->insn->data); in op_xi()
4857 o->out = tcg_constant_i64(0); in op_zero()
4863 o->out = tcg_constant_i64(0); in op_zero2()
4864 o->out2 = o->out; in op_zero2()
4903 gen_helper_stpcifc(tcg_env, r1, o->addr1, ar); in op_stpcifc()
4910 gen_helper_sic(tcg_env, o->in1, o->in2); in op_sic()
4930 gen_helper_pcistb(tcg_env, r1, r3, o->addr1, ar); in op_pcistb()
4940 gen_helper_mpcifc(tcg_env, r1, o->addr1, ar); in op_mpcifc()
4955 gen_op_update1_cc_i64(s, CC_OP_ABS_32, o->out); in cout_abs32()
4960 gen_op_update1_cc_i64(s, CC_OP_ABS_64, o->out); in cout_abs64()
4965 gen_op_update3_cc_i64(s, CC_OP_ADD_32, o->in1, o->in2, o->out); in cout_adds32()
4970 gen_op_update3_cc_i64(s, CC_OP_ADD_64, o->in1, o->in2, o->out); in cout_adds64()
4975 tcg_gen_shri_i64(cc_src, o->out, 32); in cout_addu32()
4976 tcg_gen_ext32u_i64(cc_dst, o->out); in cout_addu32()
4982 gen_op_update2_cc_i64(s, CC_OP_ADDU, cc_src, o->out); in cout_addu64()
4987 gen_op_update2_cc_i64(s, CC_OP_LTGT_32, o->in1, o->in2); in cout_cmps32()
4992 gen_op_update2_cc_i64(s, CC_OP_LTGT_64, o->in1, o->in2); in cout_cmps64()
4997 gen_op_update2_cc_i64(s, CC_OP_LTUGTU_32, o->in1, o->in2); in cout_cmpu32()
5002 gen_op_update2_cc_i64(s, CC_OP_LTUGTU_64, o->in1, o->in2); in cout_cmpu64()
5007 gen_op_update1_cc_i64(s, CC_OP_NZ_F32, o->out); in cout_f32()
5012 gen_op_update1_cc_i64(s, CC_OP_NZ_F64, o->out); in cout_f64()
5017 gen_op_update2_cc_i64(s, CC_OP_NZ_F128, o->out, o->out2); in cout_f128()
5022 gen_op_update1_cc_i64(s, CC_OP_NABS_32, o->out); in cout_nabs32()
5027 gen_op_update1_cc_i64(s, CC_OP_NABS_64, o->out); in cout_nabs64()
5032 gen_op_update1_cc_i64(s, CC_OP_COMP_32, o->out); in cout_neg32()
5037 gen_op_update1_cc_i64(s, CC_OP_COMP_64, o->out); in cout_neg64()
5042 tcg_gen_ext32u_i64(cc_dst, o->out); in cout_nz32()
5048 gen_op_update1_cc_i64(s, CC_OP_NZ, o->out); in cout_nz64()
5053 gen_op_update1_cc_i64(s, CC_OP_LTGT0_32, o->out); in cout_s32()
5058 gen_op_update1_cc_i64(s, CC_OP_LTGT0_64, o->out); in cout_s64()
5063 gen_op_update3_cc_i64(s, CC_OP_SUB_32, o->in1, o->in2, o->out); in cout_subs32()
5068 gen_op_update3_cc_i64(s, CC_OP_SUB_64, o->in1, o->in2, o->out); in cout_subs64()
5073 tcg_gen_sari_i64(cc_src, o->out, 32); in cout_subu32()
5074 tcg_gen_ext32u_i64(cc_dst, o->out); in cout_subu32()
5080 gen_op_update2_cc_i64(s, CC_OP_SUBU, cc_src, o->out); in cout_subu64()
5085 gen_op_update2_cc_i64(s, CC_OP_TM_32, o->in1, o->in2); in cout_tm32()
5090 gen_op_update2_cc_i64(s, CC_OP_TM_64, o->in1, o->in2); in cout_tm64()
5095 gen_op_update1_cc_i64(s, CC_OP_MULS_32, o->out); in cout_muls32()
5101 gen_op_update2_cc_i64(s, CC_OP_MULS_64, o->out, o->out2); in cout_muls64()
5106 with the TCG register to which we will write. Used in combination with
5108 some cases we can write to a TCG global. */
5112 o->out = tcg_temp_new_i64(); in prep_new()
5118 o->out = tcg_temp_new_i64(); in prep_new_P()
5119 o->out2 = tcg_temp_new_i64(); in prep_new_P()
5125 o->out_128 = tcg_temp_new_i128(); in prep_new_x()
5131 o->out = regs[get_field(s, r1)]; in prep_r1()
5138 o->out = regs[r1]; in prep_r1_P()
5139 o->out2 = regs[r1 + 1]; in prep_r1_P()
5144 /* The "Write OUTput" generators. These generally perform some non-trivial
5151 store_reg(get_field(s, r1), o->out); in wout_r1()
5157 store_reg(get_field(s, r1), o->out2); in wout_out2_r1()
5164 tcg_gen_deposit_i64(regs[r1], regs[r1], o->out, 0, 8); in wout_r1_8()
5171 tcg_gen_deposit_i64(regs[r1], regs[r1], o->out, 0, 16); in wout_r1_16()
5177 store_reg32_i64(get_field(s, r1), o->out); in wout_r1_32()
5183 store_reg32h_i64(get_field(s, r1), o->out); in wout_r1_32h()
5190 store_reg32_i64(r1, o->out); in wout_r1_P32()
5191 store_reg32_i64(r1 + 1, o->out2); in wout_r1_P32()
5199 store_reg32_i64(r1 + 1, o->out); in wout_r1_D32()
5200 tcg_gen_shri_i64(t, o->out, 32); in wout_r1_D32()
5208 tcg_gen_extr_i128_i64(regs[r1 + 1], regs[r1], o->out_128); in wout_r1_D64()
5215 store_reg32_i64(r3, o->out); in wout_r3_P32()
5216 store_reg32_i64(r3 + 1, o->out2); in wout_r3_P32()
5223 store_reg(r3, o->out); in wout_r3_P64()
5224 store_reg(r3 + 1, o->out2); in wout_r3_P64()
5230 store_freg32_i64(get_field(s, r1), o->out); in wout_e1()
5236 store_freg(get_field(s, r1), o->out); in wout_f1()
5245 tcg_debug_assert(o->out == NULL); in wout_x1()
5246 o->out = tcg_temp_new_i64(); in wout_x1()
5247 o->out2 = tcg_temp_new_i64(); in wout_x1()
5249 tcg_gen_extr_i128_i64(o->out2, o->out, o->out_128); in wout_x1()
5250 store_freg(f1, o->out); in wout_x1()
5251 store_freg(f1 + 2, o->out2); in wout_x1()
5258 store_freg(f1, o->out); in wout_x1_P()
5259 store_freg(f1 + 2, o->out2); in wout_x1_P()
5266 store_reg32_i64(get_field(s, r1), o->out); in wout_cond_r1r2_32()
5274 store_freg32_i64(get_field(s, r1), o->out); in wout_cond_e1e2()
5281 tcg_gen_qemu_st_i64(o->out, o->addr1, get_mem_index(s), MO_UB); in wout_m1_8()
5287 tcg_gen_qemu_st_i64(o->out, o->addr1, get_mem_index(s), MO_TEUW); in wout_m1_16()
5294 tcg_gen_qemu_st_tl(o->out, o->addr1, get_mem_index(s), MO_TEUW | MO_ALIGN); in wout_m1_16a()
5301 tcg_gen_qemu_st_i64(o->out, o->addr1, get_mem_index(s), MO_TEUL); in wout_m1_32()
5308 tcg_gen_qemu_st_tl(o->out, o->addr1, get_mem_index(s), MO_TEUL | MO_ALIGN); in wout_m1_32a()
5315 tcg_gen_qemu_st_i64(o->out, o->addr1, get_mem_index(s), MO_TEUQ); in wout_m1_64()
5322 tcg_gen_qemu_st_i64(o->out, o->addr1, get_mem_index(s), MO_TEUQ | MO_ALIGN); in wout_m1_64a()
5329 tcg_gen_qemu_st_i64(o->out, o->in2, get_mem_index(s), MO_TEUL); in wout_m2_32()
5335 store_reg(get_field(s, r1), o->in2); in wout_in2_r1()
5341 store_reg32_i64(get_field(s, r1), o->in2); in wout_in2_r1_32()
5350 o->in1 = load_reg(get_field(s, r1)); in in1_r1()
5356 o->in1 = regs[get_field(s, r1)]; in in1_r1_o()
5362 o->in1 = tcg_temp_new_i64(); in in1_r1_32s()
5363 tcg_gen_ext32s_i64(o->in1, regs[get_field(s, r1)]); in in1_r1_32s()
5369 o->in1 = tcg_temp_new_i64(); in in1_r1_32u()
5370 tcg_gen_ext32u_i64(o->in1, regs[get_field(s, r1)]); in in1_r1_32u()
5376 o->in1 = tcg_temp_new_i64(); in in1_r1_sr32()
5377 tcg_gen_shri_i64(o->in1, regs[get_field(s, r1)], 32); in in1_r1_sr32()
5383 o->in1 = load_reg(get_field(s, r1) + 1); in in1_r1p1()
5389 o->in1 = regs[get_field(s, r1) + 1]; in in1_r1p1_o()
5395 o->in1 = tcg_temp_new_i64(); in in1_r1p1_32s()
5396 tcg_gen_ext32s_i64(o->in1, regs[get_field(s, r1) + 1]); in in1_r1p1_32s()
5402 o->in1 = tcg_temp_new_i64(); in in1_r1p1_32u()
5403 tcg_gen_ext32u_i64(o->in1, regs[get_field(s, r1) + 1]); in in1_r1p1_32u()
5410 o->in1 = tcg_temp_new_i64(); in in1_r1_D32()
5411 tcg_gen_concat32_i64(o->in1, regs[r1 + 1], regs[r1]); in in1_r1_D32()
5417 o->in1 = load_reg(get_field(s, r2)); in in1_r2()
5423 o->in1 = tcg_temp_new_i64(); in in1_r2_sr32()
5424 tcg_gen_shri_i64(o->in1, regs[get_field(s, r2)], 32); in in1_r2_sr32()
5430 o->in1 = tcg_temp_new_i64(); in in1_r2_32u()
5431 tcg_gen_ext32u_i64(o->in1, regs[get_field(s, r2)]); in in1_r2_32u()
5437 o->in1 = load_reg(get_field(s, r3)); in in1_r3()
5443 o->in1 = regs[get_field(s, r3)]; in in1_r3_o()
5449 o->in1 = tcg_temp_new_i64(); in in1_r3_32s()
5450 tcg_gen_ext32s_i64(o->in1, regs[get_field(s, r3)]); in in1_r3_32s()
5456 o->in1 = tcg_temp_new_i64(); in in1_r3_32u()
5457 tcg_gen_ext32u_i64(o->in1, regs[get_field(s, r3)]); in in1_r3_32u()
5464 o->in1 = tcg_temp_new_i64(); in in1_r3_D32()
5465 tcg_gen_concat32_i64(o->in1, regs[r3 + 1], regs[r3]); in in1_r3_D32()
5471 o->in1 = tcg_temp_new_i64(); in in1_r3_sr32()
5472 tcg_gen_shri_i64(o->in1, regs[get_field(s, r3)], 32); in in1_r3_sr32()
5478 o->in1 = load_freg32_i64(get_field(s, r1)); in in1_e1()
5484 o->in1 = load_freg(get_field(s, r1)); in in1_f1()
5490 o->in1_128 = load_freg_128(get_field(s, r1)); in in1_x1()
5494 /* Load the high double word of an extended (128-bit) format FP number */
5497 o->in1 = load_freg(get_field(s, r2)); in in1_x2h()
5503 o->in1 = load_freg(get_field(s, r3)); in in1_f3()
5509 o->addr1 = get_address(s, 0, get_field(s, b1), get_field(s, d1)); in in1_la1()
5516 o->addr1 = get_address(s, x2, get_field(s, b2), get_field(s, d2)); in in1_la2()
5523 o->in1 = tcg_temp_new_i64(); in in1_m1_8u()
5524 tcg_gen_qemu_ld_i64(o->in1, o->addr1, get_mem_index(s), MO_UB); in in1_m1_8u()
5531 o->in1 = tcg_temp_new_i64(); in in1_m1_16s()
5532 tcg_gen_qemu_ld_i64(o->in1, o->addr1, get_mem_index(s), MO_TESW); in in1_m1_16s()
5539 o->in1 = tcg_temp_new_i64(); in in1_m1_16u()
5540 tcg_gen_qemu_ld_i64(o->in1, o->addr1, get_mem_index(s), MO_TEUW); in in1_m1_16u()
5547 o->in1 = tcg_temp_new_i64(); in in1_m1_32s()
5548 tcg_gen_qemu_ld_i64(o->in1, o->addr1, get_mem_index(s), MO_TESL); in in1_m1_32s()
5555 o->in1 = tcg_temp_new_i64(); in in1_m1_32u()
5556 tcg_gen_qemu_ld_i64(o->in1, o->addr1, get_mem_index(s), MO_TEUL); in in1_m1_32u()
5563 o->in1 = tcg_temp_new_i64(); in in1_m1_64()
5564 tcg_gen_qemu_ld_i64(o->in1, o->addr1, get_mem_index(s), MO_TEUQ); in in1_m1_64()
5573 o->in2 = regs[get_field(s, r1)]; in in2_r1_o()
5579 o->in2 = tcg_temp_new_i64(); in in2_r1_16u()
5580 tcg_gen_ext16u_i64(o->in2, regs[get_field(s, r1)]); in in2_r1_16u()
5586 o->in2 = tcg_temp_new_i64(); in in2_r1_32u()
5587 tcg_gen_ext32u_i64(o->in2, regs[get_field(s, r1)]); in in2_r1_32u()
5594 o->in2 = tcg_temp_new_i64(); in in2_r1_D32()
5595 tcg_gen_concat32_i64(o->in2, regs[r1 + 1], regs[r1]); in in2_r1_D32()
5601 o->in2 = load_reg(get_field(s, r2)); in in2_r2()
5607 o->in2 = regs[get_field(s, r2)]; in in2_r2_o()
5615 o->in2 = load_reg(r2); in in2_r2_nz()
5622 o->in2 = tcg_temp_new_i64(); in in2_r2_8s()
5623 tcg_gen_ext8s_i64(o->in2, regs[get_field(s, r2)]); in in2_r2_8s()
5629 o->in2 = tcg_temp_new_i64(); in in2_r2_8u()
5630 tcg_gen_ext8u_i64(o->in2, regs[get_field(s, r2)]); in in2_r2_8u()
5636 o->in2 = tcg_temp_new_i64(); in in2_r2_16s()
5637 tcg_gen_ext16s_i64(o->in2, regs[get_field(s, r2)]); in in2_r2_16s()
5643 o->in2 = tcg_temp_new_i64(); in in2_r2_16u()
5644 tcg_gen_ext16u_i64(o->in2, regs[get_field(s, r2)]); in in2_r2_16u()
5650 o->in2 = load_reg(get_field(s, r3)); in in2_r3()
5657 o->in2_128 = tcg_temp_new_i128(); in in2_r3_D64()
5658 tcg_gen_concat_i64_i128(o->in2_128, regs[r3 + 1], regs[r3]); in in2_r3_D64()
5664 o->in2 = tcg_temp_new_i64(); in in2_r3_sr32()
5665 tcg_gen_shri_i64(o->in2, regs[get_field(s, r3)], 32); in in2_r3_sr32()
5671 o->in2 = tcg_temp_new_i64(); in in2_r3_32u()
5672 tcg_gen_ext32u_i64(o->in2, regs[get_field(s, r3)]); in in2_r3_32u()
5678 o->in2 = tcg_temp_new_i64(); in in2_r2_32s()
5679 tcg_gen_ext32s_i64(o->in2, regs[get_field(s, r2)]); in in2_r2_32s()
5685 o->in2 = tcg_temp_new_i64(); in in2_r2_32u()
5686 tcg_gen_ext32u_i64(o->in2, regs[get_field(s, r2)]); in in2_r2_32u()
5692 o->in2 = tcg_temp_new_i64(); in in2_r2_sr32()
5693 tcg_gen_shri_i64(o->in2, regs[get_field(s, r2)], 32); in in2_r2_sr32()
5699 o->in2 = load_freg32_i64(get_field(s, r2)); in in2_e2()
5705 o->in2 = load_freg(get_field(s, r2)); in in2_f2()
5711 o->in2_128 = load_freg_128(get_field(s, r2)); in in2_x2()
5715 /* Load the low double word of an extended (128-bit) format FP number */
5718 o->in2 = load_freg(get_field(s, r2) + 2); in in2_x2l()
5727 o->in2 = tcg_temp_new_i64(); in in2_ra2()
5728 gen_addi_and_wrap_i64(s, o->in2, regs[r2], 0); in in2_ra2()
5741 o->in2 = get_address(s, x2, get_field(s, b2), get_field(s, d2)); in in2_a2()
5753 ri2 = tcg_constant_i64(s->base.pc_next + (int64_t)imm * 2); in gen_ri2()
5761 o->in2 = gen_ri2(s); in in2_ri2()
5771 o->in2 = tcg_constant_i64(d2 & 0x3f); in in2_sh()
5773 o->in2 = get_address(s, 0, b2, d2); in in2_sh()
5774 tcg_gen_andi_i64(o->in2, o->in2, 0x3f); in in2_sh()
5782 tcg_gen_qemu_ld_i64(o->in2, o->in2, get_mem_index(s), MO_UB); in in2_m2_8u()
5789 tcg_gen_qemu_ld_i64(o->in2, o->in2, get_mem_index(s), MO_TESW); in in2_m2_16s()
5796 tcg_gen_qemu_ld_i64(o->in2, o->in2, get_mem_index(s), MO_TEUW); in in2_m2_16u()
5803 tcg_gen_qemu_ld_i64(o->in2, o->in2, get_mem_index(s), MO_TESL); in in2_m2_32s()
5810 tcg_gen_qemu_ld_i64(o->in2, o->in2, get_mem_index(s), MO_TEUL); in in2_m2_32u()
5818 tcg_gen_qemu_ld_tl(o->in2, o->in2, get_mem_index(s), MO_TEUL | MO_ALIGN); in in2_m2_32ua()
5826 tcg_gen_qemu_ld_i64(o->in2, o->in2, get_mem_index(s), MO_TEUQ); in in2_m2_64()
5833 tcg_gen_qemu_ld_i64(o->in2, o->in2, get_mem_index(s), MO_TEUQ); in in2_m2_64w()
5834 gen_addi_and_wrap_i64(s, o->in2, o->in2, 0); in in2_m2_64w()
5842 tcg_gen_qemu_ld_i64(o->in2, o->in2, get_mem_index(s), MO_TEUQ | MO_ALIGN); in in2_m2_64a()
5849 o->in2 = tcg_temp_new_i64(); in in2_mri2_16s()
5850 tcg_gen_qemu_ld_i64(o->in2, gen_ri2(s), get_mem_index(s), MO_TESW); in in2_mri2_16s()
5856 o->in2 = tcg_temp_new_i64(); in in2_mri2_16u()
5857 tcg_gen_qemu_ld_i64(o->in2, gen_ri2(s), get_mem_index(s), MO_TEUW); in in2_mri2_16u()
5863 o->in2 = tcg_temp_new_i64(); in in2_mri2_32s()
5864 tcg_gen_qemu_ld_tl(o->in2, gen_ri2(s), get_mem_index(s), in in2_mri2_32s()
5871 o->in2 = tcg_temp_new_i64(); in in2_mri2_32u()
5872 tcg_gen_qemu_ld_tl(o->in2, gen_ri2(s), get_mem_index(s), in in2_mri2_32u()
5879 o->in2 = tcg_temp_new_i64(); in in2_mri2_64()
5880 tcg_gen_qemu_ld_i64(o->in2, gen_ri2(s), get_mem_index(s), in in2_mri2_64()
5887 o->in2 = tcg_constant_i64(get_field(s, i2)); in in2_i2()
5893 o->in2 = tcg_constant_i64((uint8_t)get_field(s, i2)); in in2_i2_8u()
5899 o->in2 = tcg_constant_i64((uint16_t)get_field(s, i2)); in in2_i2_16u()
5905 o->in2 = tcg_constant_i64((uint32_t)get_field(s, i2)); in in2_i2_32u()
5912 o->in2 = tcg_constant_i64(i2 << s->insn->data); in in2_i2_16u_shl()
5919 o->in2 = tcg_constant_i64(i2 << s->insn->data); in in2_i2_32u_shl()
5926 o->in2 = tcg_constant_i64(s->fields.raw_insn); in in2_insn()
5934 statement so that (1) we get compile-time notice of cut-paste errors
5936 search tree, rather than us having to post-process the table. */
5950 #include "insn-data.h.inc"
5987 #define FAC_DFPR S390_FEAT_FLOATING_POINT_SUPPORT_ENH /* DFP-rounding */
5988 #define FAC_DO S390_FEAT_STFLE_45 /* distinct-operands */
5992 #define FAC_FPSSH S390_FEAT_FLOATING_POINT_SUPPORT_ENH /* FPS-sign-handling */
5993 #define FAC_FPRGR S390_FEAT_FLOATING_POINT_SUPPORT_ENH /* FPR-GR-transfer */
5996 #define FAC_HW S390_FEAT_STFLE_45 /* high-word */
5997 #define FAC_IEEEE_SIM S390_FEAT_FLOATING_POINT_SUPPORT_ENH /* IEEE-exception-simulation */
5998 #define FAC_MIE S390_FEAT_STFLE_49 /* misc-instruction-extensions */
5999 #define FAC_LAT S390_FEAT_STFLE_49 /* load-and-trap */
6006 #define FAC_ILA S390_FEAT_STFLE_45 /* interlocked-access-facility 1 */
6008 #define FAC_LPP S390_FEAT_SET_PROGRAM_PARAMETERS /* load-program-parameter */
6011 #define FAC_EH S390_FEAT_STFLE_49 /* execution-hint */
6012 #define FAC_PPA S390_FEAT_STFLE_49 /* processor-assist */
6013 #define FAC_LZRB S390_FEAT_STFLE_53 /* load-and-zero-rightmost-byte */
6015 #define FAC_MSA S390_FEAT_MSA /* message-security-assist facility */
6016 #define FAC_MSA3 S390_FEAT_MSA_EXT_3 /* msa-extension-3 facility */
6017 #define FAC_MSA4 S390_FEAT_MSA_EXT_4 /* msa-extension-4 facility */
6018 #define FAC_MSA5 S390_FEAT_MSA_EXT_5 /* msa-extension-5 facility */
6019 #define FAC_MSA8 S390_FEAT_MSA_EXT_8 /* msa-extension-8 facility */
6026 #define FAC_MIE2 S390_FEAT_MISC_INSTRUCTION_EXT2 /* miscellaneous-instruction-extensions fac…
6027 #define FAC_MIE3 S390_FEAT_MISC_INSTRUCTION_EXT3 /* miscellaneous-instruction-extensions fac…
6030 #include "insn-data.h.inc"
6040 #include "insn-data.h.inc" in lookup_opc()
6051 /* Extract a field from the insn. The INSN should be left-aligned in
6052 the uint64_t so that we can more easily utilize the big-bit-endian
6059 if (f->size == 0) { in extract_field()
6064 r = (insn << f->beg) >> (64 - f->size); in extract_field()
6066 /* Sign-extend, or un-swap the field as necessary. */ in extract_field()
6067 switch (f->type) { in extract_field()
6071 assert(f->size <= 32); in extract_field()
6072 m = 1u << (f->size - 1); in extract_field()
6073 r = (r ^ m) - m; in extract_field()
6079 g_assert(f->size == 4); in extract_field()
6080 switch (f->beg) { in extract_field()
6082 r |= extract64(insn, 63 - 36, 1) << 4; in extract_field()
6085 r |= extract64(insn, 63 - 37, 1) << 4; in extract_field()
6088 r |= extract64(insn, 63 - 38, 1) << 4; in extract_field()
6091 r |= extract64(insn, 63 - 39, 1) << 4; in extract_field()
6105 assert(((o->presentC >> f->indexC) & 1) == 0); in extract_field()
6106 o->presentC |= 1 << f->indexC; in extract_field()
6107 o->presentO |= 1 << f->indexO; in extract_field()
6109 o->c[f->indexC] = r; in extract_field()
6117 uint64_t insn, pc = s->base.pc_next; in extract_insn()
6121 if (unlikely(s->ex_value)) { in extract_insn()
6129 insn = s->ex_value & 0xffffffffffff0000ull; in extract_insn()
6130 ilen = s->ex_value & 0xf; in extract_insn()
6135 translator_fake_ld(&s->base, &be_insn, get_ilen(op)); in extract_insn()
6154 s->pc_tmp = s->base.pc_next + ilen; in extract_insn()
6155 s->ilen = ilen; in extract_insn()
6200 memset(&s->fields, 0, sizeof(s->fields)); in extract_insn()
6201 s->fields.raw_insn = insn; in extract_insn()
6202 s->fields.op = op; in extract_insn()
6203 s->fields.op2 = op2; in extract_insn()
6207 s->insn = info; in extract_insn()
6211 DisasFormat fmt = info->fmt; in extract_insn()
6215 extract_field(&s->fields, &format_info[fmt].op[i], insn); in extract_insn()
6243 tcg_set_insn_start_param(s->base.insn_start, 2, s->ilen); in translate_one()
6248 s->fields.op, s->fields.op2); in translate_one()
6255 if (s->base.tb->flags & FLAG_MASK_PER_IFETCH) { in translate_one()
6256 /* With ifetch set, psw_addr and cc_op are always up-to-date. */ in translate_one()
6257 gen_helper_per_ifetch(tcg_env, tcg_constant_i32(s->ilen)); in translate_one()
6262 if (insn->flags) { in translate_one()
6264 if ((s->base.tb->flags & FLAG_MASK_PSTATE) && (insn->flags & IF_PRIV)) { in translate_one()
6271 if (!(s->base.tb->flags & FLAG_MASK_AFP)) { in translate_one()
6274 if ((insn->flags & IF_AFP1) && is_afp_reg(get_field(s, r1))) { in translate_one()
6277 if ((insn->flags & IF_AFP2) && is_afp_reg(get_field(s, r2))) { in translate_one()
6280 if ((insn->flags & IF_AFP3) && is_afp_reg(get_field(s, r3))) { in translate_one()
6283 if (insn->flags & IF_BFP) { in translate_one()
6286 if (insn->flags & IF_DFP) { in translate_one()
6289 if (insn->flags & IF_VEC) { in translate_one()
6300 if (insn->flags & IF_VEC) { in translate_one()
6301 if (!((s->base.tb->flags & FLAG_MASK_VECTOR))) { in translate_one()
6309 if (unlikely(insn->flags & IF_IO)) { in translate_one()
6310 icount = translator_io_start(&s->base); in translate_one()
6315 if (insn->spec) { in translate_one()
6316 if ((insn->spec & SPEC_r1_even && get_field(s, r1) & 1) || in translate_one()
6317 (insn->spec & SPEC_r2_even && get_field(s, r2) & 1) || in translate_one()
6318 (insn->spec & SPEC_r3_even && get_field(s, r3) & 1) || in translate_one()
6319 (insn->spec & SPEC_r1_f128 && !is_fp_pair(get_field(s, r1))) || in translate_one()
6320 (insn->spec & SPEC_r2_f128 && !is_fp_pair(get_field(s, r2)))) { in translate_one()
6328 if (insn->help_in1) { in translate_one()
6329 insn->help_in1(s, &o); in translate_one()
6331 if (insn->help_in2) { in translate_one()
6332 insn->help_in2(s, &o); in translate_one()
6334 if (insn->help_prep) { in translate_one()
6335 insn->help_prep(s, &o); in translate_one()
6337 if (insn->help_op) { in translate_one()
6338 ret = insn->help_op(s, &o); in translate_one()
6343 if (insn->help_wout) { in translate_one()
6344 insn->help_wout(s, &o); in translate_one()
6346 if (insn->help_cout) { in translate_one()
6347 insn->help_cout(s, &o); in translate_one()
6356 if (s->base.tb->flags & FLAG_MASK_PER_IFETCH) { in translate_one()
6359 s->base.is_jmp = DISAS_PC_CC_UPDATED; in translate_one()
6362 tcg_gen_movi_i64(psw_addr, s->pc_tmp); in translate_one()
6374 s->base.pc_next = s->pc_tmp; in translate_one()
6382 /* 31-bit mode */ in s390x_tr_init_disas_context()
6383 if (!(dc->base.tb->flags & FLAG_MASK_64)) { in s390x_tr_init_disas_context()
6384 dc->base.pc_first &= 0x7fffffff; in s390x_tr_init_disas_context()
6385 dc->base.pc_next = dc->base.pc_first; in s390x_tr_init_disas_context()
6388 dc->cc_op = CC_OP_DYNAMIC; in s390x_tr_init_disas_context()
6389 dc->ex_value = dc->base.tb->cs_base; in s390x_tr_init_disas_context()
6390 dc->exit_to_mainloop = dc->ex_value; in s390x_tr_init_disas_context()
6402 tcg_gen_insn_start(dc->base.pc_next, dc->cc_op, 0); in s390x_tr_insn_start()
6408 uint64_t insn = translator_lduw(env, &s->base, pc); in get_next_pc()
6418 dc->base.is_jmp = translate_one(env, dc); in s390x_tr_translate_insn()
6419 if (dc->base.is_jmp == DISAS_NEXT) { in s390x_tr_translate_insn()
6420 if (dc->ex_value || in s390x_tr_translate_insn()
6421 !translator_is_same_page(dcbase, dc->base.pc_next) || in s390x_tr_translate_insn()
6422 !translator_is_same_page(dcbase, get_next_pc(env, dc, dc->base.pc_next))) { in s390x_tr_translate_insn()
6423 dc->base.is_jmp = DISAS_TOO_MANY; in s390x_tr_translate_insn()
6432 switch (dc->base.is_jmp) { in s390x_tr_tb_stop()
6445 if (dc->exit_to_mainloop) { in s390x_tr_tb_stop()
6461 if (unlikely(dc->ex_value)) { in s390x_tr_disas_log()
6464 target_disas(logfile, cs, &dc->base); in s390x_tr_disas_log()
6494 env->psw.addr = data[0]; in s390x_restore_state_to_opc()
6496 /* Update the CC opcode if it is not already up-to-date. */ in s390x_restore_state_to_opc()
6498 env->cc_op = cc_op; in s390x_restore_state_to_opc()
6502 env->int_pgm_ilen = data[2]; in s390x_restore_state_to_opc()