Lines Matching refs:a
429 static bool trans_MOV_rm(DisasContext *ctx, arg_MOV_rm *a) in trans_MOV_rm() argument
433 tcg_gen_addi_i32(mem, cpu_regs[a->rd], a->dsp << a->sz); in trans_MOV_rm()
434 rx_gen_st(a->sz, cpu_regs[a->rs], mem); in trans_MOV_rm()
439 static bool trans_MOV_mr(DisasContext *ctx, arg_MOV_mr *a) in trans_MOV_mr() argument
443 tcg_gen_addi_i32(mem, cpu_regs[a->rs], a->dsp << a->sz); in trans_MOV_mr()
444 rx_gen_ld(a->sz, cpu_regs[a->rd], mem); in trans_MOV_mr()
451 static bool trans_MOV_ir(DisasContext *ctx, arg_MOV_ir *a) in trans_MOV_ir() argument
453 tcg_gen_movi_i32(cpu_regs[a->rd], a->imm); in trans_MOV_ir()
459 static bool trans_MOV_im(DisasContext *ctx, arg_MOV_im *a) in trans_MOV_im() argument
462 imm = tcg_constant_i32(a->imm); in trans_MOV_im()
464 tcg_gen_addi_i32(mem, cpu_regs[a->rd], a->dsp << a->sz); in trans_MOV_im()
465 rx_gen_st(a->sz, imm, mem); in trans_MOV_im()
470 static bool trans_MOV_ar(DisasContext *ctx, arg_MOV_ar *a) in trans_MOV_ar() argument
474 rx_gen_regindex(ctx, mem, a->sz, a->ri, a->rb); in trans_MOV_ar()
475 rx_gen_ld(a->sz, cpu_regs[a->rd], mem); in trans_MOV_ar()
480 static bool trans_MOV_ra(DisasContext *ctx, arg_MOV_ra *a) in trans_MOV_ra() argument
484 rx_gen_regindex(ctx, mem, a->sz, a->ri, a->rb); in trans_MOV_ra()
485 rx_gen_st(a->sz, cpu_regs[a->rs], mem); in trans_MOV_ra()
493 static bool trans_MOV_mm(DisasContext *ctx, arg_MOV_mm *a) in trans_MOV_mm() argument
497 if (a->lds == 3 && a->ldd == 3) { in trans_MOV_mm()
499 tcg_gen_ext_i32(cpu_regs[a->rd], cpu_regs[a->rs], a->sz | MO_SIGN); in trans_MOV_mm()
504 if (a->lds == 3) { in trans_MOV_mm()
506 addr = rx_index_addr(ctx, mem, a->ldd, a->sz, a->rs); in trans_MOV_mm()
507 rx_gen_st(a->sz, cpu_regs[a->rd], addr); in trans_MOV_mm()
508 } else if (a->ldd == 3) { in trans_MOV_mm()
510 addr = rx_index_addr(ctx, mem, a->lds, a->sz, a->rs); in trans_MOV_mm()
511 rx_gen_ld(a->sz, cpu_regs[a->rd], addr); in trans_MOV_mm()
515 addr = rx_index_addr(ctx, mem, a->lds, a->sz, a->rs); in trans_MOV_mm()
516 rx_gen_ld(a->sz, tmp, addr); in trans_MOV_mm()
517 addr = rx_index_addr(ctx, mem, a->ldd, a->sz, a->rd); in trans_MOV_mm()
518 rx_gen_st(a->sz, tmp, addr); in trans_MOV_mm()
525 static bool trans_MOV_rp(DisasContext *ctx, arg_MOV_rp *a) in trans_MOV_rp() argument
529 tcg_gen_mov_i32(val, cpu_regs[a->rs]); in trans_MOV_rp()
530 if (a->ad == 1) { in trans_MOV_rp()
531 tcg_gen_subi_i32(cpu_regs[a->rd], cpu_regs[a->rd], 1 << a->sz); in trans_MOV_rp()
533 rx_gen_st(a->sz, val, cpu_regs[a->rd]); in trans_MOV_rp()
534 if (a->ad == 0) { in trans_MOV_rp()
535 tcg_gen_addi_i32(cpu_regs[a->rd], cpu_regs[a->rd], 1 << a->sz); in trans_MOV_rp()
542 static bool trans_MOV_pr(DisasContext *ctx, arg_MOV_pr *a) in trans_MOV_pr() argument
546 if (a->ad == 1) { in trans_MOV_pr()
547 tcg_gen_subi_i32(cpu_regs[a->rd], cpu_regs[a->rd], 1 << a->sz); in trans_MOV_pr()
549 rx_gen_ld(a->sz, val, cpu_regs[a->rd]); in trans_MOV_pr()
550 if (a->ad == 0) { in trans_MOV_pr()
551 tcg_gen_addi_i32(cpu_regs[a->rd], cpu_regs[a->rd], 1 << a->sz); in trans_MOV_pr()
553 tcg_gen_mov_i32(cpu_regs[a->rs], val); in trans_MOV_pr()
559 static bool trans_MOVU_mr(DisasContext *ctx, arg_MOVU_mr *a) in trans_MOVU_mr() argument
563 tcg_gen_addi_i32(mem, cpu_regs[a->rs], a->dsp << a->sz); in trans_MOVU_mr()
564 rx_gen_ldu(a->sz, cpu_regs[a->rd], mem); in trans_MOVU_mr()
569 static bool trans_MOVU_rr(DisasContext *ctx, arg_MOVU_rr *a) in trans_MOVU_rr() argument
571 tcg_gen_ext_i32(cpu_regs[a->rd], cpu_regs[a->rs], a->sz); in trans_MOVU_rr()
576 static bool trans_MOVU_ar(DisasContext *ctx, arg_MOVU_ar *a) in trans_MOVU_ar() argument
580 rx_gen_regindex(ctx, mem, a->sz, a->ri, a->rb); in trans_MOVU_ar()
581 rx_gen_ldu(a->sz, cpu_regs[a->rd], mem); in trans_MOVU_ar()
587 static bool trans_MOVU_pr(DisasContext *ctx, arg_MOVU_pr *a) in trans_MOVU_pr() argument
591 if (a->ad == 1) { in trans_MOVU_pr()
592 tcg_gen_subi_i32(cpu_regs[a->rd], cpu_regs[a->rd], 1 << a->sz); in trans_MOVU_pr()
594 rx_gen_ldu(a->sz, val, cpu_regs[a->rd]); in trans_MOVU_pr()
595 if (a->ad == 0) { in trans_MOVU_pr()
596 tcg_gen_addi_i32(cpu_regs[a->rd], cpu_regs[a->rd], 1 << a->sz); in trans_MOVU_pr()
598 tcg_gen_mov_i32(cpu_regs[a->rs], val); in trans_MOVU_pr()
604 static bool trans_POP(DisasContext *ctx, arg_POP *a) in trans_POP() argument
609 mov_a.rs = a->rd; in trans_POP()
617 static bool trans_POPC(DisasContext *ctx, arg_POPC *a) in trans_POPC() argument
622 move_to_cr(ctx, val, a->cr); in trans_POPC()
627 static bool trans_POPM(DisasContext *ctx, arg_POPM *a) in trans_POPM() argument
630 if (a->rd == 0 || a->rd >= a->rd2) { in trans_POPM()
632 "Invalid register ranges r%d-r%d", a->rd, a->rd2); in trans_POPM()
634 r = a->rd; in trans_POPM()
635 while (r <= a->rd2 && r < 16) { in trans_POPM()
643 static bool trans_PUSH_r(DisasContext *ctx, arg_PUSH_r *a) in trans_PUSH_r() argument
647 tcg_gen_mov_i32(val, cpu_regs[a->rs]); in trans_PUSH_r()
649 rx_gen_st(a->sz, val, cpu_sp); in trans_PUSH_r()
654 static bool trans_PUSH_m(DisasContext *ctx, arg_PUSH_m *a) in trans_PUSH_m() argument
659 addr = rx_index_addr(ctx, mem, a->ld, a->sz, a->rs); in trans_PUSH_m()
660 rx_gen_ld(a->sz, val, addr); in trans_PUSH_m()
662 rx_gen_st(a->sz, val, cpu_sp); in trans_PUSH_m()
667 static bool trans_PUSHC(DisasContext *ctx, arg_PUSHC *a) in trans_PUSHC() argument
671 move_from_cr(ctx, val, a->cr, ctx->pc); in trans_PUSHC()
677 static bool trans_PUSHM(DisasContext *ctx, arg_PUSHM *a) in trans_PUSHM() argument
681 if (a->rs == 0 || a->rs >= a->rs2) { in trans_PUSHM()
683 "Invalid register ranges r%d-r%d", a->rs, a->rs2); in trans_PUSHM()
685 r = a->rs2; in trans_PUSHM()
686 while (r >= a->rs && r >= 0) { in trans_PUSHM()
693 static bool trans_XCHG_rr(DisasContext *ctx, arg_XCHG_rr *a) in trans_XCHG_rr() argument
697 tcg_gen_mov_i32(tmp, cpu_regs[a->rs]); in trans_XCHG_rr()
698 tcg_gen_mov_i32(cpu_regs[a->rs], cpu_regs[a->rd]); in trans_XCHG_rr()
699 tcg_gen_mov_i32(cpu_regs[a->rd], tmp); in trans_XCHG_rr()
704 static bool trans_XCHG_mr(DisasContext *ctx, arg_XCHG_mr *a) in trans_XCHG_mr() argument
708 switch (a->mi) { in trans_XCHG_mr()
712 addr = rx_index_addr(ctx, mem, a->ld, a->mi, a->rs); in trans_XCHG_mr()
716 addr = rx_index_addr(ctx, mem, a->ld, 4 - a->mi, a->rs); in trans_XCHG_mr()
721 tcg_gen_atomic_xchg_i32(cpu_regs[a->rd], addr, cpu_regs[a->rd], in trans_XCHG_mr()
722 0, mi_to_mop(a->mi)); in trans_XCHG_mr()
737 static bool trans_STZ(DisasContext *ctx, arg_STZ *a) in trans_STZ() argument
739 stcond(TCG_COND_EQ, a->rd, a->imm); in trans_STZ()
744 static bool trans_STNZ(DisasContext *ctx, arg_STNZ *a) in trans_STNZ() argument
746 stcond(TCG_COND_NE, a->rd, a->imm); in trans_STNZ()
752 static bool trans_SCCnd(DisasContext *ctx, arg_SCCnd *a) in trans_SCCnd() argument
757 psw_cond(&dc, a->cd); in trans_SCCnd()
758 if (a->ld < 3) { in trans_SCCnd()
762 addr = rx_index_addr(ctx, mem, a->sz, a->ld, a->rd); in trans_SCCnd()
763 rx_gen_st(a->sz, val, addr); in trans_SCCnd()
765 tcg_gen_setcondi_i32(dc.cond, cpu_regs[a->rd], dc.value, 0); in trans_SCCnd()
771 static bool trans_RTSD_i(DisasContext *ctx, arg_RTSD_i *a) in trans_RTSD_i() argument
773 tcg_gen_addi_i32(cpu_sp, cpu_sp, a->imm << 2); in trans_RTSD_i()
780 static bool trans_RTSD_irr(DisasContext *ctx, arg_RTSD_irr *a) in trans_RTSD_irr() argument
785 if (a->rd2 >= a->rd) { in trans_RTSD_irr()
786 adj = a->imm - (a->rd2 - a->rd + 1); in trans_RTSD_irr()
788 adj = a->imm - (15 - a->rd + 1); in trans_RTSD_irr()
792 dst = a->rd; in trans_RTSD_irr()
793 while (dst <= a->rd2 && dst < 16) { in trans_RTSD_irr()
838 static bool trans_AND_ir(DisasContext *ctx, arg_AND_ir *a) in trans_AND_ir() argument
840 rx_gen_op_irr(rx_and, a->rd, a->rd, a->imm); in trans_AND_ir()
846 static bool trans_AND_mr(DisasContext *ctx, arg_AND_mr *a) in trans_AND_mr() argument
848 rx_gen_op_mr(rx_and, ctx, a->rd, a->rs, a->ld, a->mi); in trans_AND_mr()
853 static bool trans_AND_rrr(DisasContext *ctx, arg_AND_rrr *a) in trans_AND_rrr() argument
855 rx_gen_op_rrr(rx_and, a->rd, a->rs, a->rs2); in trans_AND_rrr()
868 static bool trans_OR_ir(DisasContext *ctx, arg_OR_ir *a) in trans_OR_ir() argument
870 rx_gen_op_irr(rx_or, a->rd, a->rd, a->imm); in trans_OR_ir()
876 static bool trans_OR_mr(DisasContext *ctx, arg_OR_mr *a) in trans_OR_mr() argument
878 rx_gen_op_mr(rx_or, ctx, a->rd, a->rs, a->ld, a->mi); in trans_OR_mr()
883 static bool trans_OR_rrr(DisasContext *ctx, arg_OR_rrr *a) in trans_OR_rrr() argument
885 rx_gen_op_rrr(rx_or, a->rd, a->rs, a->rs2); in trans_OR_rrr()
897 static bool trans_XOR_ir(DisasContext *ctx, arg_XOR_ir *a) in trans_XOR_ir() argument
899 rx_gen_op_irr(rx_xor, a->rd, a->rd, a->imm); in trans_XOR_ir()
905 static bool trans_XOR_mr(DisasContext *ctx, arg_XOR_mr *a) in trans_XOR_mr() argument
907 rx_gen_op_mr(rx_xor, ctx, a->rd, a->rs, a->ld, a->mi); in trans_XOR_mr()
918 static bool trans_TST_ir(DisasContext *ctx, arg_TST_ir *a) in trans_TST_ir() argument
920 rx_gen_op_irr(rx_tst, a->rd, a->rd, a->imm); in trans_TST_ir()
926 static bool trans_TST_mr(DisasContext *ctx, arg_TST_mr *a) in trans_TST_mr() argument
928 rx_gen_op_mr(rx_tst, ctx, a->rd, a->rs, a->ld, a->mi); in trans_TST_mr()
941 static bool trans_NOT_rr(DisasContext *ctx, arg_NOT_rr *a) in trans_NOT_rr() argument
943 rx_gen_op_rr(rx_not, a->rd, a->rs); in trans_NOT_rr()
959 static bool trans_NEG_rr(DisasContext *ctx, arg_NEG_rr *a) in trans_NEG_rr() argument
961 rx_gen_op_rr(rx_neg, a->rd, a->rs); in trans_NEG_rr()
979 static bool trans_ADC_ir(DisasContext *ctx, arg_ADC_ir *a) in trans_ADC_ir() argument
981 rx_gen_op_irr(rx_adc, a->rd, a->rd, a->imm); in trans_ADC_ir()
986 static bool trans_ADC_rr(DisasContext *ctx, arg_ADC_rr *a) in trans_ADC_rr() argument
988 rx_gen_op_rrr(rx_adc, a->rd, a->rd, a->rs); in trans_ADC_rr()
993 static bool trans_ADC_mr(DisasContext *ctx, arg_ADC_mr *a) in trans_ADC_mr() argument
996 if (a->mi != 2) { in trans_ADC_mr()
999 rx_gen_op_mr(rx_adc, ctx, a->rd, a->rs, a->ld, a->mi); in trans_ADC_mr()
1017 static bool trans_ADD_irr(DisasContext *ctx, arg_ADD_irr *a) in trans_ADD_irr() argument
1019 rx_gen_op_irr(rx_add, a->rd, a->rs2, a->imm); in trans_ADD_irr()
1025 static bool trans_ADD_mr(DisasContext *ctx, arg_ADD_mr *a) in trans_ADD_mr() argument
1027 rx_gen_op_mr(rx_add, ctx, a->rd, a->rs, a->ld, a->mi); in trans_ADD_mr()
1032 static bool trans_ADD_rrr(DisasContext *ctx, arg_ADD_rrr *a) in trans_ADD_rrr() argument
1034 rx_gen_op_rrr(rx_add, a->rd, a->rs, a->rs2); in trans_ADD_rrr()
1071 static bool trans_CMP_ir(DisasContext *ctx, arg_CMP_ir *a) in trans_CMP_ir() argument
1073 rx_gen_op_irr(rx_cmp, 0, a->rs2, a->imm); in trans_CMP_ir()
1079 static bool trans_CMP_mr(DisasContext *ctx, arg_CMP_mr *a) in trans_CMP_mr() argument
1081 rx_gen_op_mr(rx_cmp, ctx, a->rd, a->rs, a->ld, a->mi); in trans_CMP_mr()
1086 static bool trans_SUB_ir(DisasContext *ctx, arg_SUB_ir *a) in trans_SUB_ir() argument
1088 rx_gen_op_irr(rx_sub, a->rd, a->rd, a->imm); in trans_SUB_ir()
1094 static bool trans_SUB_mr(DisasContext *ctx, arg_SUB_mr *a) in trans_SUB_mr() argument
1096 rx_gen_op_mr(rx_sub, ctx, a->rd, a->rs, a->ld, a->mi); in trans_SUB_mr()
1101 static bool trans_SUB_rrr(DisasContext *ctx, arg_SUB_rrr *a) in trans_SUB_rrr() argument
1103 rx_gen_op_rrr(rx_sub, a->rd, a->rs2, a->rs); in trans_SUB_rrr()
1108 static bool trans_SBB_rr(DisasContext *ctx, arg_SBB_rr *a) in trans_SBB_rr() argument
1110 rx_gen_op_rrr(rx_sbb, a->rd, a->rd, a->rs); in trans_SBB_rr()
1115 static bool trans_SBB_mr(DisasContext *ctx, arg_SBB_mr *a) in trans_SBB_mr() argument
1118 if (a->mi != 2) { in trans_SBB_mr()
1121 rx_gen_op_mr(rx_sbb, ctx, a->rd, a->rs, a->ld, a->mi); in trans_SBB_mr()
1127 static bool trans_ABS_rr(DisasContext *ctx, arg_ABS_rr *a) in trans_ABS_rr() argument
1129 rx_gen_op_rr(tcg_gen_abs_i32, a->rd, a->rs); in trans_ABS_rr()
1134 static bool trans_MAX_ir(DisasContext *ctx, arg_MAX_ir *a) in trans_MAX_ir() argument
1136 rx_gen_op_irr(tcg_gen_smax_i32, a->rd, a->rd, a->imm); in trans_MAX_ir()
1142 static bool trans_MAX_mr(DisasContext *ctx, arg_MAX_mr *a) in trans_MAX_mr() argument
1144 rx_gen_op_mr(tcg_gen_smax_i32, ctx, a->rd, a->rs, a->ld, a->mi); in trans_MAX_mr()
1149 static bool trans_MIN_ir(DisasContext *ctx, arg_MIN_ir *a) in trans_MIN_ir() argument
1151 rx_gen_op_irr(tcg_gen_smin_i32, a->rd, a->rd, a->imm); in trans_MIN_ir()
1157 static bool trans_MIN_mr(DisasContext *ctx, arg_MIN_mr *a) in trans_MIN_mr() argument
1159 rx_gen_op_mr(tcg_gen_smin_i32, ctx, a->rd, a->rs, a->ld, a->mi); in trans_MIN_mr()
1165 static bool trans_MUL_ir(DisasContext *ctx, arg_MUL_ir *a) in trans_MUL_ir() argument
1167 rx_gen_op_irr(tcg_gen_mul_i32, a->rd, a->rd, a->imm); in trans_MUL_ir()
1173 static bool trans_MUL_mr(DisasContext *ctx, arg_MUL_mr *a) in trans_MUL_mr() argument
1175 rx_gen_op_mr(tcg_gen_mul_i32, ctx, a->rd, a->rs, a->ld, a->mi); in trans_MUL_mr()
1180 static bool trans_MUL_rrr(DisasContext *ctx, arg_MUL_rrr *a) in trans_MUL_rrr() argument
1182 rx_gen_op_rrr(tcg_gen_mul_i32, a->rd, a->rs, a->rs2); in trans_MUL_rrr()
1187 static bool trans_EMUL_ir(DisasContext *ctx, arg_EMUL_ir *a) in trans_EMUL_ir() argument
1189 TCGv imm = tcg_constant_i32(a->imm); in trans_EMUL_ir()
1190 if (a->rd > 14) { in trans_EMUL_ir()
1191 qemu_log_mask(LOG_GUEST_ERROR, "rd too large %d", a->rd); in trans_EMUL_ir()
1193 tcg_gen_muls2_i32(cpu_regs[a->rd], cpu_regs[(a->rd + 1) & 15], in trans_EMUL_ir()
1194 cpu_regs[a->rd], imm); in trans_EMUL_ir()
1200 static bool trans_EMUL_mr(DisasContext *ctx, arg_EMUL_mr *a) in trans_EMUL_mr() argument
1203 if (a->rd > 14) { in trans_EMUL_mr()
1204 qemu_log_mask(LOG_GUEST_ERROR, "rd too large %d", a->rd); in trans_EMUL_mr()
1207 val = rx_load_source(ctx, mem, a->ld, a->mi, a->rs); in trans_EMUL_mr()
1208 tcg_gen_muls2_i32(cpu_regs[a->rd], cpu_regs[(a->rd + 1) & 15], in trans_EMUL_mr()
1209 cpu_regs[a->rd], val); in trans_EMUL_mr()
1214 static bool trans_EMULU_ir(DisasContext *ctx, arg_EMULU_ir *a) in trans_EMULU_ir() argument
1216 TCGv imm = tcg_constant_i32(a->imm); in trans_EMULU_ir()
1217 if (a->rd > 14) { in trans_EMULU_ir()
1218 qemu_log_mask(LOG_GUEST_ERROR, "rd too large %d", a->rd); in trans_EMULU_ir()
1220 tcg_gen_mulu2_i32(cpu_regs[a->rd], cpu_regs[(a->rd + 1) & 15], in trans_EMULU_ir()
1221 cpu_regs[a->rd], imm); in trans_EMULU_ir()
1227 static bool trans_EMULU_mr(DisasContext *ctx, arg_EMULU_mr *a) in trans_EMULU_mr() argument
1230 if (a->rd > 14) { in trans_EMULU_mr()
1231 qemu_log_mask(LOG_GUEST_ERROR, "rd too large %d", a->rd); in trans_EMULU_mr()
1234 val = rx_load_source(ctx, mem, a->ld, a->mi, a->rs); in trans_EMULU_mr()
1235 tcg_gen_mulu2_i32(cpu_regs[a->rd], cpu_regs[(a->rd + 1) & 15], in trans_EMULU_mr()
1236 cpu_regs[a->rd], val); in trans_EMULU_mr()
1251 static bool trans_DIV_ir(DisasContext *ctx, arg_DIV_ir *a) in trans_DIV_ir() argument
1253 rx_gen_op_irr(rx_div, a->rd, a->rd, a->imm); in trans_DIV_ir()
1259 static bool trans_DIV_mr(DisasContext *ctx, arg_DIV_mr *a) in trans_DIV_mr() argument
1261 rx_gen_op_mr(rx_div, ctx, a->rd, a->rs, a->ld, a->mi); in trans_DIV_mr()
1266 static bool trans_DIVU_ir(DisasContext *ctx, arg_DIVU_ir *a) in trans_DIVU_ir() argument
1268 rx_gen_op_irr(rx_divu, a->rd, a->rd, a->imm); in trans_DIVU_ir()
1274 static bool trans_DIVU_mr(DisasContext *ctx, arg_DIVU_mr *a) in trans_DIVU_mr() argument
1276 rx_gen_op_mr(rx_divu, ctx, a->rd, a->rs, a->ld, a->mi); in trans_DIVU_mr()
1283 static bool trans_SHLL_irr(DisasContext *ctx, arg_SHLL_irr *a) in trans_SHLL_irr() argument
1287 if (a->imm) { in trans_SHLL_irr()
1288 tcg_gen_sari_i32(cpu_psw_c, cpu_regs[a->rs2], 32 - a->imm); in trans_SHLL_irr()
1289 tcg_gen_shli_i32(cpu_regs[a->rd], cpu_regs[a->rs2], a->imm); in trans_SHLL_irr()
1295 tcg_gen_mov_i32(cpu_regs[a->rd], cpu_regs[a->rs2]); in trans_SHLL_irr()
1299 tcg_gen_mov_i32(cpu_psw_z, cpu_regs[a->rd]); in trans_SHLL_irr()
1300 tcg_gen_mov_i32(cpu_psw_s, cpu_regs[a->rd]); in trans_SHLL_irr()
1305 static bool trans_SHLL_rr(DisasContext *ctx, arg_SHLL_rr *a) in trans_SHLL_rr() argument
1313 tcg_gen_brcondi_i32(TCG_COND_EQ, cpu_regs[a->rs], 0, noshift); in trans_SHLL_rr()
1316 tcg_gen_andi_i32(tmp, cpu_regs[a->rs], 31); in trans_SHLL_rr()
1318 tcg_gen_sar_i32(cpu_psw_c, cpu_regs[a->rd], count); in trans_SHLL_rr()
1319 tcg_gen_shl_i32(cpu_regs[a->rd], cpu_regs[a->rd], tmp); in trans_SHLL_rr()
1331 tcg_gen_mov_i32(cpu_psw_z, cpu_regs[a->rd]); in trans_SHLL_rr()
1332 tcg_gen_mov_i32(cpu_psw_s, cpu_regs[a->rd]); in trans_SHLL_rr()
1390 static bool trans_SHAR_irr(DisasContext *ctx, arg_SHAR_irr *a) in trans_SHAR_irr() argument
1392 shiftr_imm(a->rd, a->rs2, a->imm, 1); in trans_SHAR_irr()
1397 static bool trans_SHAR_rr(DisasContext *ctx, arg_SHAR_rr *a) in trans_SHAR_rr() argument
1399 shiftr_reg(a->rd, a->rs, 1); in trans_SHAR_rr()
1405 static bool trans_SHLR_irr(DisasContext *ctx, arg_SHLR_irr *a) in trans_SHLR_irr() argument
1407 shiftr_imm(a->rd, a->rs2, a->imm, 0); in trans_SHLR_irr()
1412 static bool trans_SHLR_rr(DisasContext *ctx, arg_SHLR_rr *a) in trans_SHLR_rr() argument
1414 shiftr_reg(a->rd, a->rs, 0); in trans_SHLR_rr()
1419 static bool trans_ROLC(DisasContext *ctx, arg_ROLC *a) in trans_ROLC() argument
1423 tcg_gen_shri_i32(tmp, cpu_regs[a->rd], 31); in trans_ROLC()
1424 tcg_gen_shli_i32(cpu_regs[a->rd], cpu_regs[a->rd], 1); in trans_ROLC()
1425 tcg_gen_or_i32(cpu_regs[a->rd], cpu_regs[a->rd], cpu_psw_c); in trans_ROLC()
1427 tcg_gen_mov_i32(cpu_psw_z, cpu_regs[a->rd]); in trans_ROLC()
1428 tcg_gen_mov_i32(cpu_psw_s, cpu_regs[a->rd]); in trans_ROLC()
1433 static bool trans_RORC(DisasContext *ctx, arg_RORC *a) in trans_RORC() argument
1437 tcg_gen_andi_i32(tmp, cpu_regs[a->rd], 0x00000001); in trans_RORC()
1438 tcg_gen_shri_i32(cpu_regs[a->rd], cpu_regs[a->rd], 1); in trans_RORC()
1440 tcg_gen_or_i32(cpu_regs[a->rd], cpu_regs[a->rd], cpu_psw_c); in trans_RORC()
1442 tcg_gen_mov_i32(cpu_psw_z, cpu_regs[a->rd]); in trans_RORC()
1443 tcg_gen_mov_i32(cpu_psw_s, cpu_regs[a->rd]); in trans_RORC()
1474 static bool trans_ROTL_ir(DisasContext *ctx, arg_ROTL_ir *a) in trans_ROTL_ir() argument
1476 rx_rot(ROT_IMM, ROTL, a->rd, a->imm); in trans_ROTL_ir()
1481 static bool trans_ROTL_rr(DisasContext *ctx, arg_ROTL_rr *a) in trans_ROTL_rr() argument
1483 rx_rot(ROT_REG, ROTL, a->rd, a->rs); in trans_ROTL_rr()
1488 static bool trans_ROTR_ir(DisasContext *ctx, arg_ROTR_ir *a) in trans_ROTR_ir() argument
1490 rx_rot(ROT_IMM, ROTR, a->rd, a->imm); in trans_ROTR_ir()
1495 static bool trans_ROTR_rr(DisasContext *ctx, arg_ROTR_rr *a) in trans_ROTR_rr() argument
1497 rx_rot(ROT_REG, ROTR, a->rd, a->rs); in trans_ROTR_rr()
1502 static bool trans_REVL(DisasContext *ctx, arg_REVL *a) in trans_REVL() argument
1504 tcg_gen_bswap32_i32(cpu_regs[a->rd], cpu_regs[a->rs]); in trans_REVL()
1509 static bool trans_REVW(DisasContext *ctx, arg_REVW *a) in trans_REVW() argument
1513 tcg_gen_andi_i32(tmp, cpu_regs[a->rs], 0x00ff00ff); in trans_REVW()
1515 tcg_gen_shri_i32(cpu_regs[a->rd], cpu_regs[a->rs], 8); in trans_REVW()
1516 tcg_gen_andi_i32(cpu_regs[a->rd], cpu_regs[a->rd], 0x00ff00ff); in trans_REVW()
1517 tcg_gen_or_i32(cpu_regs[a->rd], cpu_regs[a->rd], tmp); in trans_REVW()
1560 static bool trans_BCnd(DisasContext *ctx, arg_BCnd *a) in trans_BCnd() argument
1562 rx_bcnd_main(ctx, a->cd, a->dsp); in trans_BCnd()
1570 static bool trans_BRA(DisasContext *ctx, arg_BRA *a) in trans_BRA() argument
1572 rx_bcnd_main(ctx, 14, a->dsp); in trans_BRA()
1577 static bool trans_BRA_l(DisasContext *ctx, arg_BRA_l *a) in trans_BRA_l() argument
1579 tcg_gen_addi_i32(cpu_pc, cpu_regs[a->rd], ctx->pc); in trans_BRA_l()
1591 static bool trans_JMP(DisasContext *ctx, arg_JMP *a) in trans_JMP() argument
1593 tcg_gen_mov_i32(cpu_pc, cpu_regs[a->rs]); in trans_JMP()
1599 static bool trans_JSR(DisasContext *ctx, arg_JSR *a) in trans_JSR() argument
1602 tcg_gen_mov_i32(cpu_pc, cpu_regs[a->rs]); in trans_JSR()
1609 static bool trans_BSR(DisasContext *ctx, arg_BSR *a) in trans_BSR() argument
1612 rx_bcnd_main(ctx, 14, a->dsp); in trans_BSR()
1617 static bool trans_BSR_l(DisasContext *ctx, arg_BSR_l *a) in trans_BSR_l() argument
1620 tcg_gen_addi_i32(cpu_pc, cpu_regs[a->rd], ctx->pc); in trans_BSR_l()
1626 static bool trans_RTS(DisasContext *ctx, arg_RTS *a) in trans_RTS() argument
1634 static bool trans_NOP(DisasContext *ctx, arg_NOP *a) in trans_NOP() argument
1640 static bool trans_SCMPU(DisasContext *ctx, arg_SCMPU *a) in trans_SCMPU() argument
1647 static bool trans_SMOVU(DisasContext *ctx, arg_SMOVU *a) in trans_SMOVU() argument
1654 static bool trans_SMOVF(DisasContext *ctx, arg_SMOVF *a) in trans_SMOVF() argument
1661 static bool trans_SMOVB(DisasContext *ctx, arg_SMOVB *a) in trans_SMOVB() argument
1669 TCGv size = tcg_constant_i32(a->sz); \
1674 static bool trans_SUNTIL(DisasContext *ctx, arg_SUNTIL *a) in trans_SUNTIL() argument
1681 static bool trans_SWHILE(DisasContext *ctx, arg_SWHILE *a) in trans_SWHILE() argument
1687 static bool trans_SSTR(DisasContext *ctx, arg_SSTR *a) in trans_SSTR() argument
1694 static bool trans_RMPA(DisasContext *ctx, arg_RMPA *a) in trans_RMPA() argument
1727 static bool trans_MULHI(DisasContext *ctx, arg_MULHI *a) in trans_MULHI() argument
1729 rx_mul64hi(cpu_acc, a->rs, a->rs2); in trans_MULHI()
1734 static bool trans_MULLO(DisasContext *ctx, arg_MULLO *a) in trans_MULLO() argument
1736 rx_mul64lo(cpu_acc, a->rs, a->rs2); in trans_MULLO()
1741 static bool trans_MACHI(DisasContext *ctx, arg_MACHI *a) in trans_MACHI() argument
1745 rx_mul64hi(tmp, a->rs, a->rs2); in trans_MACHI()
1751 static bool trans_MACLO(DisasContext *ctx, arg_MACLO *a) in trans_MACLO() argument
1755 rx_mul64lo(tmp, a->rs, a->rs2); in trans_MACLO()
1761 static bool trans_MVFACHI(DisasContext *ctx, arg_MVFACHI *a) in trans_MVFACHI() argument
1763 tcg_gen_extrh_i64_i32(cpu_regs[a->rd], cpu_acc); in trans_MVFACHI()
1768 static bool trans_MVFACMI(DisasContext *ctx, arg_MVFACMI *a) in trans_MVFACMI() argument
1773 tcg_gen_extrl_i64_i32(cpu_regs[a->rd], rd64); in trans_MVFACMI()
1778 static bool trans_MVTACHI(DisasContext *ctx, arg_MVTACHI *a) in trans_MVTACHI() argument
1782 tcg_gen_extu_i32_i64(rs64, cpu_regs[a->rs]); in trans_MVTACHI()
1788 static bool trans_MVTACLO(DisasContext *ctx, arg_MVTACLO *a) in trans_MVTACLO() argument
1792 tcg_gen_extu_i32_i64(rs64, cpu_regs[a->rs]); in trans_MVTACLO()
1798 static bool trans_RACW(DisasContext *ctx, arg_RACW *a) in trans_RACW() argument
1800 TCGv imm = tcg_constant_i32(a->imm + 1); in trans_RACW()
1806 static bool trans_SAT(DisasContext *ctx, arg_SAT *a) in trans_SAT() argument
1815 tcg_gen_movcond_i32(TCG_COND_LT, cpu_regs[a->rd], in trans_SAT()
1816 cpu_psw_o, z, tmp, cpu_regs[a->rd]); in trans_SAT()
1821 static bool trans_SATR(DisasContext *ctx, arg_SATR *a) in trans_SATR() argument
1827 #define cat3(a, b, c) a##b##c argument
1830 cat3(arg_, name, _ir) * a) \
1833 gen_helper_##op(cpu_regs[a->rd], tcg_env, \
1834 cpu_regs[a->rd], imm); \
1838 cat3(arg_, name, _mr) * a) \
1842 val = rx_load_source(ctx, mem, a->ld, MO_32, a->rs); \
1843 gen_helper_##op(cpu_regs[a->rd], tcg_env, \
1844 cpu_regs[a->rd], val); \
1849 static bool trans_##name(DisasContext *ctx, arg_##name * a) \
1853 val = rx_load_source(ctx, mem, a->ld, MO_32, a->rs); \
1854 gen_helper_##op(cpu_regs[a->rd], tcg_env, val); \
1864 static bool trans_FCMP_ir(DisasContext *ctx, arg_FCMP_ir * a) in FOP()
1867 gen_helper_fcmp(tcg_env, cpu_regs[a->rd], imm); in FOP()
1873 static bool trans_FCMP_mr(DisasContext *ctx, arg_FCMP_mr *a) in trans_FCMP_mr() argument
1877 val = rx_load_source(ctx, mem, a->ld, MO_32, a->rs); in trans_FCMP_mr()
1878 gen_helper_fcmp(tcg_env, cpu_regs[a->rd], val); in trans_FCMP_mr()
1887 static bool trans_ITOF(DisasContext *ctx, arg_ITOF * a) in FCONVOP()
1891 val = rx_load_source(ctx, mem, a->ld, a->mi, a->rs); in FCONVOP()
1892 gen_helper_itof(cpu_regs[a->rd], tcg_env, val); in FCONVOP()
1959 cat3(arg_, name, _im) * a) \
1963 mask = tcg_constant_i32(1 << a->imm); \
1964 addr = rx_index_addr(ctx, mem, a->ld, MO_8, a->rs); \
1969 cat3(arg_, name, _ir) * a) \
1972 mask = tcg_constant_i32(1 << a->imm); \
1973 cat3(rx_, op, r)(cpu_regs[a->rd], mask); \
1977 cat3(arg_, name, _rr) * a) \
1982 tcg_gen_andi_i32(b, cpu_regs[a->rs], 31); \
1984 cat3(rx_, op, r)(cpu_regs[a->rd], mask); \
1988 cat3(arg_, name, _rm) * a) \
1993 tcg_gen_andi_i32(b, cpu_regs[a->rd], 7); \
1996 addr = rx_index_addr(ctx, mem, a->ld, MO_8, a->rs); \
2019 static bool trans_BMCnd_im(DisasContext *ctx, arg_BMCnd_im *a) in trans_BMCnd_im() argument
2024 addr = rx_index_addr(ctx, mem, a->ld, MO_8, a->rd); in trans_BMCnd_im()
2026 bmcnd_op(val, a->cd, a->imm); in trans_BMCnd_im()
2032 static bool trans_BMCnd_ir(DisasContext *ctx, arg_BMCnd_ir *a) in trans_BMCnd_ir() argument
2034 bmcnd_op(cpu_regs[a->rd], a->cd, a->imm); in trans_BMCnd_ir()
2089 static bool trans_CLRPSW(DisasContext *ctx, arg_CLRPSW *a) in trans_CLRPSW() argument
2091 clrsetpsw(ctx, a->cb, 0); in trans_CLRPSW()
2096 static bool trans_SETPSW(DisasContext *ctx, arg_SETPSW *a) in trans_SETPSW() argument
2098 clrsetpsw(ctx, a->cb, 1); in trans_SETPSW()
2103 static bool trans_MVTIPL(DisasContext *ctx, arg_MVTIPL *a) in trans_MVTIPL() argument
2106 tcg_gen_movi_i32(cpu_psw_ipl, a->imm); in trans_MVTIPL()
2113 static bool trans_MVTC_i(DisasContext *ctx, arg_MVTC_i *a) in trans_MVTC_i() argument
2117 imm = tcg_constant_i32(a->imm); in trans_MVTC_i()
2118 move_to_cr(ctx, imm, a->cr); in trans_MVTC_i()
2123 static bool trans_MVTC_r(DisasContext *ctx, arg_MVTC_r *a) in trans_MVTC_r() argument
2125 move_to_cr(ctx, cpu_regs[a->rs], a->cr); in trans_MVTC_r()
2130 static bool trans_MVFC(DisasContext *ctx, arg_MVFC *a) in trans_MVFC() argument
2132 move_from_cr(ctx, cpu_regs[a->rd], a->cr, ctx->pc); in trans_MVFC()
2137 static bool trans_RTFI(DisasContext *ctx, arg_RTFI *a) in trans_RTFI() argument
2151 static bool trans_RTE(DisasContext *ctx, arg_RTE *a) in trans_RTE() argument
2165 static bool trans_BRK(DisasContext *ctx, arg_BRK *a) in trans_BRK() argument
2174 static bool trans_INT(DisasContext *ctx, arg_INT *a) in trans_INT() argument
2178 tcg_debug_assert(a->imm < 0x100); in trans_INT()
2179 vec = tcg_constant_i32(a->imm); in trans_INT()
2187 static bool trans_WAIT(DisasContext *ctx, arg_WAIT *a) in trans_WAIT() argument