Lines Matching +full:rs +full:-
23 &jreg rs
24 &rr rd rs
26 &rrr rd rs rs2
28 &rm rd rs ld mi
29 &mi rs ld mi imm
30 &mr rs ld mi rs2
43 @b2_rds .... .... .... rd:4 &rr rs=%b2_r_0
49 @b2_rd_ld_ub .... .. ld:2 rs:4 rd:4 &rm mi=4
50 @b2_ld_imm3 .... .. ld:2 rs:4 . imm:3 &mi mi=4
61 @b3_rd_rs .... .... .... .... rs:4 rd:4 &rr
62 @b3_rs_rd .... .... .... .... rd:4 rs:4 &rr
65 @b3_rd_ld .... .... mi:2 .... ld:2 rs:4 rd:4 &rm
66 @b3_rd_ld_ub .... .... .... .. ld:2 rs:4 rd:4 &rm mi=4
67 @b3_rd_ld_ul .... .... .... .. ld:2 rs:4 rd:4 &rm mi=2
68 @b3_rd_rs_rs2 .... .... .... rd:4 rs:4 rs2:4 &rrr
73 @b3_ld_rd_rs .... .... .... .. ld:2 rs:4 rd:4 &rm mi=0
82 @b4_rd_ldmi .... .... mi:2 .... ld:2 .... .... rs:4 rd:4 &rm
88 # ABS rs, rd
93 # ADC rs, rd
95 # ADC dsp[rs].l, rd
101 # ADD #imm, rs, rd
103 # ADD dsp[rs].ub, rd
104 # ADD rs, rd
106 # ADD dsp[rs], rd
108 # ADD rs, rs2, rd
115 # AND dsp[rs].ub, rd
116 # AND rs, rd
118 # AND dsp[rs], rd
120 # AND rs, rs2, rd
125 # BCLR #imm, rs
127 # BCLR rs, rd
128 # BCLR rs, dsp[rd]
149 BNOT_im 1111 1100 111 imm:3 ld:2 rs:4 1111
160 # BNOT rs, rd
161 # BNOT rs, dsp[rd]
173 # BRA.l rs
182 # BSET rs, rd
183 # BSET rs, dsp[rd]
193 # BSR.l rs
200 # BSET rs, rd
201 # BSET rs, dsp[rd]
216 # CMP dsp[rs].ub, rs2
217 # CMP rs, rs2
219 # CMP dsp[rs], rs2
224 # DIV dsp[rs].ub, rd
225 # DIV rs, rd
227 # DIV dsp[rs], rd
232 # DIVU dsp[rs].ub, rd
233 # DIVU rs, rd
235 # DIVU dsp[rs], rd
240 # EMUL dsp[rs].ub, rd
241 # EMUL rs, rd
243 # EMUL dsp[rs], rd
248 # EMULU dsp[rs].ub, rd
249 # EMULU rs, rd
251 # EMULU dsp[rs], rd
256 # FADD rs, rd
257 # FADD dsp[rs], rd
262 # FCMP rs, rd
263 # FCMP dsp[rs], rd
268 # FDIV rs, rd
269 # FDIV dsp[rs], rd
274 # FMUL rs, rd
275 # FMUL dsp[rs], rd
280 # FSUB rs, rd
281 # FSUB dsp[rs], rd
284 # FTOI rs, rd
285 # FTOI dsp[rs], rd
291 # ITOF dsp[rs].ub, rd
292 # ITOF rs, rd
294 # ITOF dsp[rs], rd
297 # JMP rs
298 JMP 0111 1111 0000 rs:4 &jreg
299 # JSR rs
300 JSR 0111 1111 0001 rs:4 &jreg
302 # MACHI rs, rs2
303 MACHI 1111 1101 0000 0100 rs:4 rs2:4
304 # MACLO rs, rs2
305 MACLO 1111 1101 0000 0101 rs:4 rs2:4
309 # MAX dsp[rs].ub, rd
310 # MAX rs, rd
312 # MAX dsp[rs], rd
317 # MIN dsp[rs].ub, rd
318 # MIN rs, rd
320 # MIN dsp[rs], rd
323 # MOV.b rs, dsp5[rd]
324 MOV_rm 1000 0 .... rd:3 . rs:3 dsp=%b2_dsp5_3 sz=0
325 # MOV.w rs, dsp5[rd]
326 MOV_rm 1001 0 .... rd:3 . rs:3 dsp=%b2_dsp5_3 sz=1
327 # MOV.l rs, dsp5[rd]
328 MOV_rm 1010 0 .... rd:3 . rs:3 dsp=%b2_dsp5_3 sz=2
329 # MOV.b dsp5[rs], rd
330 MOV_mr 1000 1 .... rs:3 . rd:3 dsp=%b2_dsp5_3 sz=0
331 # MOV.w dsp5[rs], rd
332 MOV_mr 1001 1 .... rs:3 . rd:3 dsp=%b2_dsp5_3 sz=1
333 # MOV.l dsp5[rs], rd
334 MOV_mr 1010 1 .... rs:3 . rd:3 dsp=%b2_dsp5_3 sz=2
356 # MOV.<bwl> rs, [ri,rb]
357 MOV_ra 1111 1110 00 sz:2 ri:4 rb:4 rs:4
359 # MOV.b rs, rd
360 # MOV.b rs, dsp[rd]
361 # MOV.b dsp[rs], rd
362 # MOV.b dsp[rs], dsp[rd]
363 MOV_mm 1100 ldd:2 lds:2 rs:4 rd:4 sz=0
364 # MOV.w rs, rd
365 # MOV.w rs, dsp[rd]
366 # MOV.w dsp[rs], rd
367 # MOV.w dsp[rs], dsp[rd]
368 MOV_mm 1101 ldd:2 lds:2 rs:4 rd:4 sz=1
369 # MOV.l rs, rd
370 # MOV.l rs, dsp[rd]
371 # MOV.l dsp[rs], rd
372 # MOV.l dsp[rs], dsp[rd]
373 MOV_mm 1110 ldd:2 lds:2 rs:4 rd:4 sz=2
374 # MOV.l rs, [rd+]
375 # MOV.l rs, [-rd]
376 MOV_rp 1111 1101 0010 0 ad:1 sz:2 rd:4 rs:4
377 # MOV.l [rs+], rd
378 # MOV.l [-rs], rd
379 MOV_pr 1111 1101 0010 1 ad:1 sz:2 rd:4 rs:4
381 # MOVU.<bw> dsp5[rs], rd
382 MOVU_mr 1011 sz:1 ... . rs:3 . rd:3 dsp=%b2_dsp5_3
383 # MOVU.<bw> [rs], rd
384 MOVU_mr 0101 1 sz:1 00 rs:4 rd:4 dsp=0
385 # MOVU.<bw> dsp8[rs], rd
386 MOVU_mr 0101 1 sz:1 01 rs:4 rd:4 dsp:8
387 # MOVU.<bw> dsp16[rs], rd
388 MOVU_mr 0101 1 sz:1 10 rs:4 rd:4 .... .... .... .... dsp=%b4_dsp_16
389 # MOVU.<bw> rs, rd
390 MOVU_rr 0101 1 sz:1 11 rs:4 rd:4
393 # MOVU.<bw> [rs+], rd
394 MOVU_pr 1111 1101 0011 1 ad:1 0 sz:1 rd:4 rs:4
400 # MUL dsp[rs].ub, rd
401 # MUL rs, rd
403 # MUL dsp[rs], rd
405 # MOV rs, rs2, rd
408 # MULHI rs, rs2
409 MULHI 1111 1101 0000 0000 rs:4 rs2:4
410 # MULLO rs, rs2
411 MULLO 1111 1101 0000 0001 rs:4 rs2:4
421 # MVTACHI rs
422 MVTACHI 1111 1101 0001 0111 0000 rs:4
423 # MVTACLO rs
424 MVTACLO 1111 1101 0001 0111 0001 rs:4
428 # MVTC rs, cr
429 MVTC_r 1111 1101 0110 1000 rs:4 cr:4
436 # NEG rs, rd
443 # NOT rs, rd
450 # OR dsp[rs].ub, rd
451 # OR rs, rd
453 # OR dsp[rs], rd
455 # OR rs, rs2, rd
460 # POP rd-rd2
464 # PUSH.<bwl> rs
467 PUSH_r 0111 1110 10 sz:2 rs:4
469 # PUSH.<bwl> dsp[rs]
470 PUSH_m 1111 01 ld:2 rs:4 10 sz:2
473 # PUSHM rs-rs2
474 PUSHM 0110 1110 rs:4 rs2:4
479 # REVL rs,rd
481 # REVW rs,rd
498 # ROTL rs, rd
506 # ROUND rs,rd
507 # ROUND dsp[rs],rd
518 # RTSD #imm, rd-rd2
526 # SBB rs, rd
528 # SBB dsp[rs].l, rd
541 # SHAR #imm, rs, rd
543 # SHAR rs, rd
548 # SHLL #imm, rs, rd
550 # SHLL rs, rd
555 # SHLR #imm, rs, rd
557 # SHLR rs, rd
574 # SUB dsp[rs].ub, rd
575 # SUB rs, rd
577 # SUB dsp[rs], rd
579 # SUB rs, rs2, rd
598 # TST dsp[rs].ub, rd
599 # TST rs, rd
601 # TST dsp[rs], rd
606 # XCHG rs, rd
607 # XCHG dsp[rs].ub, rd
612 # XCHG dsp[rs], rd
617 # XOR dsp[rs].ub, rd
618 # XOR rs, rd
620 # XOR dsp[rs], rd