2  * RISC-V timer helper implementation.
28     CPURISCVState *env = &cpu->env;  in riscv_vstimer_cb()
29     env->vstime_irq = 1;  in riscv_vstimer_cb()
36     riscv_cpu_update_mip(&cpu->env, MIP_STIP, BOOL_TO_MASK(1));  in riscv_stimer_cb()
48     RISCVAclintMTimerState *mtimer = env->rdtime_fn_arg;  in riscv_timer_write_timecmp()
52     if (!riscv_cpu_cfg(env)->ext_sstc || !env->rdtime_fn ||  in riscv_timer_write_timecmp()
53         !env->rdtime_fn_arg || !get_field(env->menvcfg, MENVCFG_STCE)) {  in riscv_timer_write_timecmp()
59         (!riscv_has_ext(env, RVH) || !get_field(env->henvcfg, HENVCFG_STCE))) {  in riscv_timer_write_timecmp()
64     timebase_freq = mtimer->timebase_freq;  in riscv_timer_write_timecmp()
65     rtc_r = env->rdtime_fn(env->rdtime_fn_arg) + delta;  in riscv_timer_write_timecmp()
73             env->vstime_irq = 1;  in riscv_timer_write_timecmp()
83         env->vstime_irq = 0;  in riscv_timer_write_timecmp()
91      * "A supervisor timer interrupt becomes pending - as reflected in  in riscv_timer_write_timecmp()
92      * the STIP bit in the mip and sip registers - whenever time contains  in riscv_timer_write_timecmp()
97      * than time - typically as a result of writing stimecmp."  in riscv_timer_write_timecmp()
99      * When timecmp = UINT64_MAX, the time CSR will eventually reach  in riscv_timer_write_timecmp()
100      * timecmp value but on next timer tick the time CSR will wrap-around  in riscv_timer_write_timecmp()
103      * become 1 when time = timecmp = UINT64_MAX and next timer tick  in riscv_timer_write_timecmp()
104      * it will become 0 again because time = 0 < timecmp = UINT64_MAX.  in riscv_timer_write_timecmp()
106      * Based on above, we don't re-start the QEMU timer when timecmp  in riscv_timer_write_timecmp()
115     diff = timecmp - rtc_r;  in riscv_timer_write_timecmp()
144  * When disabling xenvcfg.STCE, the S/VS Timer may be disabled at the same time.
152     /* Disable S-mode Timer IRQ and HW-based STIP */  in riscv_timer_disable_timecmp()
153     if ((timer_irq == MIP_STIP) && !get_field(env->menvcfg, MENVCFG_STCE)) {  in riscv_timer_disable_timecmp()
159     /* Disable VS-mode Timer IRQ and HW-based VSTIP */  in riscv_timer_disable_timecmp()
161         (!get_field(env->menvcfg, MENVCFG_STCE) ||  in riscv_timer_disable_timecmp()
162          !get_field(env->henvcfg, HENVCFG_STCE))) {  in riscv_timer_disable_timecmp()
163         env->vstime_irq = 0;  in riscv_timer_disable_timecmp()
170 /* Enable or disable S/VS-mode Timer when xenvcfg.STCE is changed */
174         riscv_timer_write_timecmp(env, env->vstimer, env->vstimecmp,  in riscv_timer_stce_changed()
175                                   env->htimedelta, MIP_VSTIP);  in riscv_timer_stce_changed()
177         riscv_timer_disable_timecmp(env, env->vstimer, MIP_VSTIP);  in riscv_timer_stce_changed()
182             riscv_timer_write_timecmp(env, env->stimer, env->stimecmp, 0, MIP_STIP);  in riscv_timer_stce_changed()
184             riscv_timer_disable_timecmp(env, env->stimer, MIP_STIP);  in riscv_timer_stce_changed()
197     env = &cpu->env;  in riscv_timer_init()
198     env->stimer = timer_new_ns(QEMU_CLOCK_VIRTUAL, &riscv_stimer_cb, cpu);  in riscv_timer_init()
199     env->stimecmp = 0;  in riscv_timer_init()
201     env->vstimer = timer_new_ns(QEMU_CLOCK_VIRTUAL, &riscv_vstimer_cb, cpu);  in riscv_timer_init()
202     env->vstimecmp = 0;  in riscv_timer_init()