Lines Matching full:cpu
2 * riscv TCG cpu class initialization
22 #include "tcg-cpu.h"
23 #include "cpu.h"
33 #include "accel/accel-cpu-target.h"
34 #include "accel/tcg/cpu-ops.h"
73 static void riscv_cpu_write_misa_bit(RISCVCPU *cpu, uint32_t bit, in riscv_cpu_write_misa_bit() argument
76 CPURISCVState *env = &cpu->env; in riscv_cpu_write_misa_bit()
104 RISCVCPU *cpu = env_archcpu(env); in riscv_get_tb_cpu_state() local
109 if (cpu->cfg.ext_zve32x) { in riscv_get_tb_cpu_state()
122 uint32_t vlmax = vext_get_vlmax(cpu->cfg.vlenb, vsew, lmul); in riscv_get_tb_cpu_state()
180 if (cpu->cfg.debug && !icount_enabled()) { in riscv_get_tb_cpu_state()
202 RISCVCPU *cpu = RISCV_CPU(cs); in riscv_cpu_synchronize_from_tb() local
203 CPURISCVState *env = &cpu->env; in riscv_cpu_synchronize_from_tb()
220 RISCVCPU *cpu = RISCV_CPU(cs); in riscv_restore_state_to_opc() local
221 CPURISCVState *env = &cpu->env; in riscv_restore_state_to_opc()
339 static void riscv_cpu_enable_named_feat(RISCVCPU *cpu, uint32_t feat_offset) in riscv_cpu_enable_named_feat() argument
347 cpu->cfg.cbom_blocksize = 64; in riscv_cpu_enable_named_feat()
348 cpu->cfg.cbop_blocksize = 64; in riscv_cpu_enable_named_feat()
349 cpu->cfg.cboz_blocksize = 64; in riscv_cpu_enable_named_feat()
353 riscv_cpu_write_misa_bit(cpu, RVH, true); in riscv_cpu_enable_named_feat()
357 cpu->cfg.ext_smstateen = true; in riscv_cpu_enable_named_feat()
382 static void cpu_cfg_ext_auto_update(RISCVCPU *cpu, uint32_t ext_offset, in cpu_cfg_ext_auto_update() argument
385 CPURISCVState *env = &cpu->env; in cpu_cfg_ext_auto_update()
386 bool prev_val = isa_ext_is_enabled(cpu, ext_offset); in cpu_cfg_ext_auto_update()
405 isa_ext_update_enabled(cpu, ext_offset, value); in cpu_cfg_ext_auto_update()
451 static void riscv_cpu_disable_priv_spec_isa_exts(RISCVCPU *cpu) in riscv_cpu_disable_priv_spec_isa_exts() argument
453 CPURISCVState *env = &cpu->env; in riscv_cpu_disable_priv_spec_isa_exts()
458 if (isa_ext_is_enabled(cpu, edata->ext_enable_offset) && in riscv_cpu_disable_priv_spec_isa_exts()
470 * cpu.debug = true is marked as 'sdtrig', priv spec 1.12. in riscv_cpu_disable_priv_spec_isa_exts()
478 isa_ext_update_enabled(cpu, edata->ext_enable_offset, false); in riscv_cpu_disable_priv_spec_isa_exts()
501 static void riscv_cpu_update_named_features(RISCVCPU *cpu) in riscv_cpu_update_named_features() argument
503 if (cpu->env.priv_ver >= PRIV_VERSION_1_11_0) { in riscv_cpu_update_named_features()
504 cpu->cfg.has_priv_1_11 = true; in riscv_cpu_update_named_features()
507 if (cpu->env.priv_ver >= PRIV_VERSION_1_12_0) { in riscv_cpu_update_named_features()
508 cpu->cfg.has_priv_1_12 = true; in riscv_cpu_update_named_features()
511 if (cpu->env.priv_ver >= PRIV_VERSION_1_13_0) { in riscv_cpu_update_named_features()
512 cpu->cfg.has_priv_1_13 = true; in riscv_cpu_update_named_features()
515 cpu->cfg.ext_zic64b = cpu->cfg.cbom_blocksize == 64 && in riscv_cpu_update_named_features()
516 cpu->cfg.cbop_blocksize == 64 && in riscv_cpu_update_named_features()
517 cpu->cfg.cboz_blocksize == 64; in riscv_cpu_update_named_features()
519 cpu->cfg.ext_ssstateen = cpu->cfg.ext_smstateen; in riscv_cpu_update_named_features()
521 cpu->cfg.ext_sha = riscv_has_ext(&cpu->env, RVH) && in riscv_cpu_update_named_features()
522 cpu->cfg.ext_ssstateen; in riscv_cpu_update_named_features()
524 cpu->cfg.ext_ziccrse = cpu->cfg.has_priv_1_11; in riscv_cpu_update_named_features()
527 static void riscv_cpu_validate_g(RISCVCPU *cpu) in riscv_cpu_validate_g() argument
536 if (riscv_has_ext(&cpu->env, bit)) { in riscv_cpu_validate_g()
541 riscv_cpu_write_misa_bit(cpu, bit, true); in riscv_cpu_validate_g()
550 if (!cpu->cfg.ext_zicsr) { in riscv_cpu_validate_g()
552 cpu->cfg.ext_zicsr = true; in riscv_cpu_validate_g()
558 if (!cpu->cfg.ext_zifencei) { in riscv_cpu_validate_g()
560 cpu->cfg.ext_zifencei = true; in riscv_cpu_validate_g()
567 static void riscv_cpu_validate_b(RISCVCPU *cpu) in riscv_cpu_validate_b() argument
571 if (!cpu->cfg.ext_zba) { in riscv_cpu_validate_b()
573 cpu->cfg.ext_zba = true; in riscv_cpu_validate_b()
579 if (!cpu->cfg.ext_zbb) { in riscv_cpu_validate_b()
581 cpu->cfg.ext_zbb = true; in riscv_cpu_validate_b()
587 if (!cpu->cfg.ext_zbs) { in riscv_cpu_validate_b()
589 cpu->cfg.ext_zbs = true; in riscv_cpu_validate_b()
598 * cpu->cfg accordingly.
600 void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp) in riscv_cpu_validate_set_extensions() argument
602 RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(cpu); in riscv_cpu_validate_set_extensions()
603 CPURISCVState *env = &cpu->env; in riscv_cpu_validate_set_extensions()
607 riscv_cpu_validate_g(cpu); in riscv_cpu_validate_set_extensions()
611 riscv_cpu_validate_b(cpu); in riscv_cpu_validate_set_extensions()
643 if (riscv_has_ext(env, RVF) && !cpu->cfg.ext_zicsr) { in riscv_cpu_validate_set_extensions()
648 if ((cpu->cfg.ext_zacas) && !riscv_has_ext(env, RVA)) { in riscv_cpu_validate_set_extensions()
653 if ((cpu->cfg.ext_zawrs) && !riscv_has_ext(env, RVA)) { in riscv_cpu_validate_set_extensions()
658 if (cpu->cfg.ext_zfa && !riscv_has_ext(env, RVF)) { in riscv_cpu_validate_set_extensions()
663 if (cpu->cfg.ext_zfhmin && !riscv_has_ext(env, RVF)) { in riscv_cpu_validate_set_extensions()
668 if (cpu->cfg.ext_zfbfmin && !riscv_has_ext(env, RVF)) { in riscv_cpu_validate_set_extensions()
678 if (cpu->cfg.ext_zve32x) { in riscv_cpu_validate_set_extensions()
679 riscv_cpu_validate_v(env, &cpu->cfg, &local_err); in riscv_cpu_validate_set_extensions()
687 if (cpu->cfg.ext_zve64d) { in riscv_cpu_validate_set_extensions()
695 if (cpu->cfg.ext_zve32f) { in riscv_cpu_validate_set_extensions()
702 if (cpu->cfg.ext_zvfhmin && !cpu->cfg.ext_zve32f) { in riscv_cpu_validate_set_extensions()
707 if (cpu->cfg.ext_zvfh && !cpu->cfg.ext_zfhmin) { in riscv_cpu_validate_set_extensions()
712 if (cpu->cfg.ext_zvfbfmin && !cpu->cfg.ext_zve32f) { in riscv_cpu_validate_set_extensions()
717 if (cpu->cfg.ext_zvfbfwma && !cpu->cfg.ext_zvfbfmin) { in riscv_cpu_validate_set_extensions()
722 if ((cpu->cfg.ext_zdinx || cpu->cfg.ext_zhinxmin) && !cpu->cfg.ext_zfinx) { in riscv_cpu_validate_set_extensions()
727 if (cpu->cfg.ext_zfinx) { in riscv_cpu_validate_set_extensions()
728 if (!cpu->cfg.ext_zicsr) { in riscv_cpu_validate_set_extensions()
739 if (cpu->cfg.ext_zcmop && !cpu->cfg.ext_zca) { in riscv_cpu_validate_set_extensions()
744 if (mcc->def->misa_mxl_max != MXL_RV32 && cpu->cfg.ext_zcf) { in riscv_cpu_validate_set_extensions()
749 if (!riscv_has_ext(env, RVF) && cpu->cfg.ext_zcf) { in riscv_cpu_validate_set_extensions()
754 if (!riscv_has_ext(env, RVD) && cpu->cfg.ext_zcd) { in riscv_cpu_validate_set_extensions()
759 if ((cpu->cfg.ext_zcf || cpu->cfg.ext_zcd || cpu->cfg.ext_zcb || in riscv_cpu_validate_set_extensions()
760 cpu->cfg.ext_zcmp || cpu->cfg.ext_zcmt) && !cpu->cfg.ext_zca) { in riscv_cpu_validate_set_extensions()
766 if (cpu->cfg.ext_zcd && (cpu->cfg.ext_zcmp || cpu->cfg.ext_zcmt)) { in riscv_cpu_validate_set_extensions()
772 if (cpu->cfg.ext_zcmt && !cpu->cfg.ext_zicsr) { in riscv_cpu_validate_set_extensions()
777 if ((cpu->cfg.ext_zvbb || cpu->cfg.ext_zvkb || cpu->cfg.ext_zvkg || in riscv_cpu_validate_set_extensions()
778 cpu->cfg.ext_zvkned || cpu->cfg.ext_zvknha || cpu->cfg.ext_zvksed || in riscv_cpu_validate_set_extensions()
779 cpu->cfg.ext_zvksh) && !cpu->cfg.ext_zve32x) { in riscv_cpu_validate_set_extensions()
785 if ((cpu->cfg.ext_zvbc || cpu->cfg.ext_zvknhb) && !cpu->cfg.ext_zve64x) { in riscv_cpu_validate_set_extensions()
792 if (cpu->cfg.ext_zicntr && !cpu->cfg.ext_zicsr) { in riscv_cpu_validate_set_extensions()
797 cpu->cfg.ext_zicntr = false; in riscv_cpu_validate_set_extensions()
800 if (cpu->cfg.ext_zihpm && !cpu->cfg.ext_zicsr) { in riscv_cpu_validate_set_extensions()
805 cpu->cfg.ext_zihpm = false; in riscv_cpu_validate_set_extensions()
808 if (cpu->cfg.ext_zicfiss) { in riscv_cpu_validate_set_extensions()
809 if (!cpu->cfg.ext_zicsr) { in riscv_cpu_validate_set_extensions()
821 if (!cpu->cfg.ext_zimop) { in riscv_cpu_validate_set_extensions()
825 if (cpu->cfg.ext_zca && !cpu->cfg.ext_zcmop) { in riscv_cpu_validate_set_extensions()
831 if (!cpu->cfg.ext_zihpm) { in riscv_cpu_validate_set_extensions()
832 cpu->cfg.pmu_mask = 0; in riscv_cpu_validate_set_extensions()
833 cpu->pmu_avail_ctrs = 0; in riscv_cpu_validate_set_extensions()
836 if (cpu->cfg.ext_zicfilp && !cpu->cfg.ext_zicsr) { in riscv_cpu_validate_set_extensions()
841 if (mcc->def->misa_mxl_max == MXL_RV32 && cpu->cfg.ext_svukte) { in riscv_cpu_validate_set_extensions()
846 if ((cpu->cfg.ext_smctr || cpu->cfg.ext_ssctr) && in riscv_cpu_validate_set_extensions()
847 (!riscv_has_ext(env, RVS) || !cpu->cfg.ext_sscsrind)) { in riscv_cpu_validate_set_extensions()
853 cpu->cfg.ext_smctr = false; in riscv_cpu_validate_set_extensions()
854 cpu->cfg.ext_ssctr = false; in riscv_cpu_validate_set_extensions()
857 if (cpu->cfg.ext_svrsw60t59b && in riscv_cpu_validate_set_extensions()
858 (!cpu->cfg.mmu || mcc->def->misa_mxl_max == MXL_RV32)) { in riscv_cpu_validate_set_extensions()
867 riscv_cpu_disable_priv_spec_isa_exts(cpu); in riscv_cpu_validate_set_extensions()
871 static bool riscv_cpu_validate_profile_satp(RISCVCPU *cpu, in riscv_cpu_validate_profile_satp() argument
875 int satp_max = cpu->cfg.max_satp_mode; in riscv_cpu_validate_profile_satp()
880 bool is_32bit = riscv_cpu_is_32bit(cpu); in riscv_cpu_validate_profile_satp()
896 static void riscv_cpu_check_parent_profile(RISCVCPU *cpu, in riscv_cpu_check_parent_profile() argument
907 static void riscv_cpu_validate_profile(RISCVCPU *cpu, in riscv_cpu_validate_profile() argument
910 CPURISCVState *env = &cpu->env; in riscv_cpu_validate_profile()
918 profile_impl = riscv_cpu_validate_profile_satp(cpu, profile, in riscv_cpu_validate_profile()
942 if (!riscv_has_ext(&cpu->env, bit)) { in riscv_cpu_validate_profile()
955 if (!isa_ext_is_enabled(cpu, ext_offset)) { in riscv_cpu_validate_profile()
967 riscv_cpu_check_parent_profile(cpu, profile, profile->u_parent); in riscv_cpu_validate_profile()
968 riscv_cpu_check_parent_profile(cpu, profile, profile->s_parent); in riscv_cpu_validate_profile()
971 static void riscv_cpu_validate_profiles(RISCVCPU *cpu) in riscv_cpu_validate_profiles() argument
974 riscv_cpu_validate_profile(cpu, riscv_profiles[i]); in riscv_cpu_validate_profiles()
1011 static void cpu_enable_implied_rule(RISCVCPU *cpu, in cpu_enable_implied_rule() argument
1014 CPURISCVState *env = &cpu->env; in cpu_enable_implied_rule()
1020 enabled = test_bit(cpu->env.mhartid, rule->enabled); in cpu_enable_implied_rule()
1042 cpu_enable_implied_rule(cpu, ir); in cpu_enable_implied_rule()
1051 cpu_cfg_ext_auto_update(cpu, rule->implied_multi_exts[i], true); in cpu_enable_implied_rule()
1058 cpu_enable_implied_rule(cpu, ir); in cpu_enable_implied_rule()
1063 bitmap_set(rule->enabled, cpu->env.mhartid, 1); in cpu_enable_implied_rule()
1069 static void cpu_enable_zc_implied_rules(RISCVCPU *cpu) in cpu_enable_zc_implied_rules() argument
1071 RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(cpu); in cpu_enable_zc_implied_rules()
1072 CPURISCVState *env = &cpu->env; in cpu_enable_zc_implied_rules()
1074 if (cpu->cfg.ext_zce) { in cpu_enable_zc_implied_rules()
1075 cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zca), true); in cpu_enable_zc_implied_rules()
1076 cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcb), true); in cpu_enable_zc_implied_rules()
1077 cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcmp), true); in cpu_enable_zc_implied_rules()
1078 cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcmt), true); in cpu_enable_zc_implied_rules()
1081 cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcf), true); in cpu_enable_zc_implied_rules()
1087 cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zca), true); in cpu_enable_zc_implied_rules()
1090 cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcf), true); in cpu_enable_zc_implied_rules()
1094 cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcd), true); in cpu_enable_zc_implied_rules()
1099 static void riscv_cpu_enable_implied_rules(RISCVCPU *cpu) in riscv_cpu_enable_implied_rules() argument
1105 cpu_enable_zc_implied_rules(cpu); in riscv_cpu_enable_implied_rules()
1109 if (riscv_has_ext(&cpu->env, rule->ext)) { in riscv_cpu_enable_implied_rules()
1110 cpu_enable_implied_rule(cpu, rule); in riscv_cpu_enable_implied_rules()
1116 if (isa_ext_is_enabled(cpu, rule->ext)) { in riscv_cpu_enable_implied_rules()
1117 cpu_enable_implied_rule(cpu, rule); in riscv_cpu_enable_implied_rules()
1122 void riscv_tcg_cpu_finalize_features(RISCVCPU *cpu, Error **errp) in riscv_tcg_cpu_finalize_features() argument
1124 CPURISCVState *env = &cpu->env; in riscv_tcg_cpu_finalize_features()
1128 riscv_cpu_enable_implied_rules(cpu); in riscv_tcg_cpu_finalize_features()
1136 riscv_cpu_update_named_features(cpu); in riscv_tcg_cpu_finalize_features()
1137 riscv_cpu_validate_profiles(cpu); in riscv_tcg_cpu_finalize_features()
1139 if (cpu->cfg.ext_smepmp && !cpu->cfg.pmp) { in riscv_tcg_cpu_finalize_features()
1148 riscv_cpu_validate_set_extensions(cpu, &local_err); in riscv_tcg_cpu_finalize_features()
1154 if (cpu->cfg.pmu_mask) { in riscv_tcg_cpu_finalize_features()
1155 riscv_pmu_init(cpu, &local_err); in riscv_tcg_cpu_finalize_features()
1161 if (cpu->cfg.ext_sscofpmf) { in riscv_tcg_cpu_finalize_features()
1162 cpu->pmu_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, in riscv_tcg_cpu_finalize_features()
1163 riscv_pmu_timer_cb, cpu); in riscv_tcg_cpu_finalize_features()
1169 void riscv_tcg_cpu_finalize_dynamic_decoder(RISCVCPU *cpu) in riscv_tcg_cpu_finalize_dynamic_decoder() argument
1175 decoder_table[i].guard_func(&cpu->cfg)) { in riscv_tcg_cpu_finalize_dynamic_decoder()
1181 cpu->decoders = dynamic_decoders; in riscv_tcg_cpu_finalize_dynamic_decoder()
1184 bool riscv_cpu_tcg_compatible(RISCVCPU *cpu) in riscv_cpu_tcg_compatible() argument
1186 return object_dynamic_cast(OBJECT(cpu), TYPE_RISCV_CPU_HOST) == NULL; in riscv_cpu_tcg_compatible()
1194 static void riscv_cpu_set_profile(RISCVCPU *cpu, in riscv_cpu_set_profile() argument
1201 riscv_cpu_set_profile(cpu, profile->u_parent, enabled); in riscv_cpu_set_profile()
1205 riscv_cpu_set_profile(cpu, profile->s_parent, enabled); in riscv_cpu_set_profile()
1211 cpu->env.priv_ver = profile->priv_spec; in riscv_cpu_set_profile()
1215 object_property_set_bool(OBJECT(cpu), "mmu", true, NULL); in riscv_cpu_set_profile()
1217 riscv_cpu_is_32bit(cpu)); in riscv_cpu_set_profile()
1218 object_property_set_bool(OBJECT(cpu), satp_prop, true, NULL); in riscv_cpu_set_profile()
1239 riscv_cpu_write_misa_bit(cpu, bit, profile->enabled); in riscv_cpu_set_profile()
1247 riscv_cpu_enable_named_feat(cpu, ext_offset); in riscv_cpu_set_profile()
1250 cpu_bump_multi_ext_priv_ver(&cpu->env, ext_offset); in riscv_cpu_set_profile()
1254 isa_ext_update_enabled(cpu, ext_offset, profile->enabled); in riscv_cpu_set_profile()
1267 RISCVCPU *cpu = RISCV_CPU(cs); in riscv_tcg_cpu_realize() local
1269 if (!riscv_cpu_tcg_compatible(cpu)) { in riscv_tcg_cpu_realize()
1270 g_autofree char *name = riscv_cpu_get_name(cpu); in riscv_tcg_cpu_realize()
1271 error_setg(errp, "'%s' CPU is not compatible with TCG acceleration", in riscv_tcg_cpu_realize()
1277 RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(cpu); in riscv_tcg_cpu_realize()
1287 CPURISCVState *env = &cpu->env; in riscv_tcg_cpu_realize()
1289 tcg_cflags_set(CPU(cs), CF_PCREL); in riscv_tcg_cpu_realize()
1291 if (cpu->cfg.ext_sstc) { in riscv_tcg_cpu_realize()
1292 riscv_timer_init(cpu); in riscv_tcg_cpu_realize()
1314 RISCVCPU *cpu = RISCV_CPU(obj); in cpu_set_misa_ext_cfg() local
1315 CPURISCVState *env = &cpu->env; in cpu_set_misa_ext_cfg()
1333 g_autofree char *cpuname = riscv_cpu_get_name(cpu); in cpu_set_misa_ext_cfg()
1334 error_setg(errp, "'%s' CPU does not allow enabling extensions", in cpu_set_misa_ext_cfg()
1348 riscv_cpu_write_misa_bit(cpu, misa_bit, value); in cpu_set_misa_ext_cfg()
1356 RISCVCPU *cpu = RISCV_CPU(obj); in cpu_get_misa_ext_cfg() local
1357 CPURISCVState *env = &cpu->env; in cpu_get_misa_ext_cfg()
1422 RISCVCPU *cpu = RISCV_CPU(obj); in cpu_set_profile() local
1431 if (cpu->env.misa_mxl != MXL_RV64) { in cpu_set_profile()
1443 riscv_cpu_set_profile(cpu, profile, value); in cpu_set_profile()
1479 RISCVCPU *cpu = RISCV_CPU(obj); in cpu_set_multi_ext_cfg() local
1489 prev_val = isa_ext_is_enabled(cpu, multi_ext_cfg->offset); in cpu_set_multi_ext_cfg()
1496 g_autofree char *cpuname = riscv_cpu_get_name(cpu); in cpu_set_multi_ext_cfg()
1497 error_setg(errp, "'%s' CPU does not allow enabling extensions", in cpu_set_multi_ext_cfg()
1503 cpu_bump_multi_ext_priv_ver(&cpu->env, multi_ext_cfg->offset); in cpu_set_multi_ext_cfg()
1506 isa_ext_update_enabled(cpu, multi_ext_cfg->offset, value); in cpu_set_multi_ext_cfg()
1554 * Add CPU properties with user-facing flags.
1575 * The 'max' type CPU will have all possible ratified
1580 RISCVCPU *cpu = RISCV_CPU(obj); in riscv_init_max_cpu_extensions() local
1581 CPURISCVState *env = &cpu->env; in riscv_init_max_cpu_extensions()
1588 isa_ext_update_enabled(cpu, prop->offset, true); in riscv_init_max_cpu_extensions()
1595 cpu->cfg.ext_svade = false; in riscv_init_max_cpu_extensions()
1601 isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zfinx), false); in riscv_init_max_cpu_extensions()
1602 isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zdinx), false); in riscv_init_max_cpu_extensions()
1603 isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zhinx), false); in riscv_init_max_cpu_extensions()
1604 isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zhinxmin), false); in riscv_init_max_cpu_extensions()
1606 isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zce), false); in riscv_init_max_cpu_extensions()
1607 isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zcmp), false); in riscv_init_max_cpu_extensions()
1608 isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zcmt), false); in riscv_init_max_cpu_extensions()
1611 isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zcf), false); in riscv_init_max_cpu_extensions()
1613 isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_svrsw60t59b), false); in riscv_init_max_cpu_extensions()
1620 if (cpu->cfg.ext_smrnmi) { in riscv_init_max_cpu_extensions()
1621 isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_smrnmi), false); in riscv_init_max_cpu_extensions()
1629 if (cpu->cfg.ext_smdbltrp) { in riscv_init_max_cpu_extensions()
1630 isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_smdbltrp), false); in riscv_init_max_cpu_extensions()
1641 RISCVCPU *cpu = RISCV_CPU(cs); in riscv_tcg_cpu_instance_init() local
1642 Object *obj = OBJECT(cpu); in riscv_tcg_cpu_instance_init()