riscv/tcg/tcg-cpu.c

872                                             RISCVCPUProfile *profile,
878     if (profile->satp_mode > satp_max) {
881             const char *req_satp = satp_mode_str(profile->satp_mode, is_32bit);
884             warn_report("Profile %s requires satp mode %s, "
885                         "but satp mode %s was set", profile->name,
897                                            RISCVCPUProfile *profile,
900     if (!profile->present || !parent) {
904     profile->present = parent->present;
908                                        RISCVCPUProfile *profile)
911     const char *warn_msg = "Profile %s mandates disabled extension %s";
912     bool send_warn = profile->user_set && profile->enabled;
917     if (profile->satp_mode != RISCV_PROFILE_ATTR_UNUSED) {
918         profile_impl = riscv_cpu_validate_profile_satp(cpu, profile,
923     if (profile->priv_spec != RISCV_PROFILE_ATTR_UNUSED &&
924         profile->priv_spec > env->priv_ver) {
928             warn_report("Profile %s requires priv spec %s, "
929                         "but priv ver %s was set", profile->name,
930                         cpu_priv_ver_to_str(profile->priv_spec),
938         if (!(profile->misa_ext & bit)) {
946                 warn_report(warn_msg, profile->name,
952     for (i = 0; profile->ext_offsets[i] != RISCV_PROFILE_EXT_LIST_END; i++) {
953         int ext_offset = profile->ext_offsets[i];
959                 warn_report(warn_msg, profile->name,
965     profile->present = profile_impl;
967     riscv_cpu_check_parent_profile(cpu, profile, profile->u_parent);
968     riscv_cpu_check_parent_profile(cpu, profile, profile->s_parent);
1195                                   RISCVCPUProfile *profile,
1200     if (profile->u_parent != NULL) {
1201         riscv_cpu_set_profile(cpu, profile->u_parent, enabled);
1204     if (profile->s_parent != NULL) {
1205         riscv_cpu_set_profile(cpu, profile->s_parent, enabled);
1208     profile->enabled = enabled;
1210     if (profile->enabled) {
1211         cpu->env.priv_ver = profile->priv_spec;
1214         if (profile->satp_mode != RISCV_PROFILE_ATTR_UNUSED) {
1216             const char *satp_prop = satp_mode_str(profile->satp_mode,
1226         if  (!(profile->misa_ext & bit)) {
1230         if (bit == RVI && !profile->enabled) {
1238         cpu_misa_ext_add_user_opt(bit, profile->enabled);
1239         riscv_cpu_write_misa_bit(cpu, bit, profile->enabled);
1242     for (i = 0; profile->ext_offsets[i] != RISCV_PROFILE_EXT_LIST_END; i++) {
1243         ext_offset = profile->ext_offsets[i];
1245         if (profile->enabled) {
1253         cpu_cfg_ext_add_user_opt(ext_offset, profile->enabled);
1254         isa_ext_update_enabled(cpu, ext_offset, profile->enabled);
1421     RISCVCPUProfile *profile = opaque;
1426         error_setg(errp, "Profile %s is not available for vendor CPUs",
1427                    profile->name);
1432         error_setg(errp, "Profile %s only available for 64 bit CPUs",
1433                    profile->name);
1441     profile->user_set = true;
1443     riscv_cpu_set_profile(cpu, profile, value);
1449     RISCVCPUProfile *profile = opaque;
1450     bool value = profile->enabled;
1458         RISCVCPUProfile *profile = riscv_profiles[i];
1460         object_property_add(cpu_obj, profile->name, "bool",
1462                             NULL, (void *)profile);
1465          * CPUs might enable a profile right from the start.
1469         if (profile->enabled) {
1470             riscv_cpu_set_profile(RISCV_CPU(cpu_obj), profile, true);