Lines Matching full:cpu
2 * riscv TCG cpu class initialization
22 #include "tcg-cpu.h"
23 #include "cpu.h"
33 #include "accel/accel-cpu-target.h"
34 #include "accel/tcg/cpu-ops.h"
73 static void riscv_cpu_write_misa_bit(RISCVCPU *cpu, uint32_t bit, in riscv_cpu_write_misa_bit() argument
76 CPURISCVState *env = &cpu->env; in riscv_cpu_write_misa_bit()
104 RISCVCPU *cpu = env_archcpu(env); in riscv_get_tb_cpu_state() local
109 if (cpu->cfg.ext_zve32x) { in riscv_get_tb_cpu_state()
122 uint32_t vlmax = vext_get_vlmax(cpu->cfg.vlenb, vsew, lmul); in riscv_get_tb_cpu_state()
180 if (cpu->cfg.debug && !icount_enabled()) { in riscv_get_tb_cpu_state()
202 RISCVCPU *cpu = RISCV_CPU(cs); in riscv_cpu_synchronize_from_tb() local
203 CPURISCVState *env = &cpu->env; in riscv_cpu_synchronize_from_tb()
220 RISCVCPU *cpu = RISCV_CPU(cs); in riscv_restore_state_to_opc() local
221 CPURISCVState *env = &cpu->env; in riscv_restore_state_to_opc()
339 static void riscv_cpu_enable_named_feat(RISCVCPU *cpu, uint32_t feat_offset) in riscv_cpu_enable_named_feat() argument
347 cpu->cfg.cbom_blocksize = 64; in riscv_cpu_enable_named_feat()
348 cpu->cfg.cbop_blocksize = 64; in riscv_cpu_enable_named_feat()
349 cpu->cfg.cboz_blocksize = 64; in riscv_cpu_enable_named_feat()
353 riscv_cpu_write_misa_bit(cpu, RVH, true); in riscv_cpu_enable_named_feat()
357 cpu->cfg.ext_smstateen = true; in riscv_cpu_enable_named_feat()
382 static void cpu_cfg_ext_auto_update(RISCVCPU *cpu, uint32_t ext_offset, in cpu_cfg_ext_auto_update() argument
385 CPURISCVState *env = &cpu->env; in cpu_cfg_ext_auto_update()
386 bool prev_val = isa_ext_is_enabled(cpu, ext_offset); in cpu_cfg_ext_auto_update()
405 isa_ext_update_enabled(cpu, ext_offset, value); in cpu_cfg_ext_auto_update()
436 static void riscv_cpu_disable_priv_spec_isa_exts(RISCVCPU *cpu) in riscv_cpu_disable_priv_spec_isa_exts() argument
438 CPURISCVState *env = &cpu->env; in riscv_cpu_disable_priv_spec_isa_exts()
443 if (isa_ext_is_enabled(cpu, edata->ext_enable_offset) && in riscv_cpu_disable_priv_spec_isa_exts()
455 * cpu.debug = true is marked as 'sdtrig', priv spec 1.12. in riscv_cpu_disable_priv_spec_isa_exts()
463 isa_ext_update_enabled(cpu, edata->ext_enable_offset, false); in riscv_cpu_disable_priv_spec_isa_exts()
486 static void riscv_cpu_update_named_features(RISCVCPU *cpu) in riscv_cpu_update_named_features() argument
488 if (cpu->env.priv_ver >= PRIV_VERSION_1_11_0) { in riscv_cpu_update_named_features()
489 cpu->cfg.has_priv_1_11 = true; in riscv_cpu_update_named_features()
492 if (cpu->env.priv_ver >= PRIV_VERSION_1_12_0) { in riscv_cpu_update_named_features()
493 cpu->cfg.has_priv_1_12 = true; in riscv_cpu_update_named_features()
496 if (cpu->env.priv_ver >= PRIV_VERSION_1_13_0) { in riscv_cpu_update_named_features()
497 cpu->cfg.has_priv_1_13 = true; in riscv_cpu_update_named_features()
500 cpu->cfg.ext_zic64b = cpu->cfg.cbom_blocksize == 64 && in riscv_cpu_update_named_features()
501 cpu->cfg.cbop_blocksize == 64 && in riscv_cpu_update_named_features()
502 cpu->cfg.cboz_blocksize == 64; in riscv_cpu_update_named_features()
504 cpu->cfg.ext_ssstateen = cpu->cfg.ext_smstateen; in riscv_cpu_update_named_features()
506 cpu->cfg.ext_sha = riscv_has_ext(&cpu->env, RVH) && in riscv_cpu_update_named_features()
507 cpu->cfg.ext_ssstateen; in riscv_cpu_update_named_features()
509 cpu->cfg.ext_ziccrse = cpu->cfg.has_priv_1_11; in riscv_cpu_update_named_features()
512 static void riscv_cpu_validate_g(RISCVCPU *cpu) in riscv_cpu_validate_g() argument
521 if (riscv_has_ext(&cpu->env, bit)) { in riscv_cpu_validate_g()
526 riscv_cpu_write_misa_bit(cpu, bit, true); in riscv_cpu_validate_g()
535 if (!cpu->cfg.ext_zicsr) { in riscv_cpu_validate_g()
537 cpu->cfg.ext_zicsr = true; in riscv_cpu_validate_g()
543 if (!cpu->cfg.ext_zifencei) { in riscv_cpu_validate_g()
545 cpu->cfg.ext_zifencei = true; in riscv_cpu_validate_g()
552 static void riscv_cpu_validate_b(RISCVCPU *cpu) in riscv_cpu_validate_b() argument
556 if (!cpu->cfg.ext_zba) { in riscv_cpu_validate_b()
558 cpu->cfg.ext_zba = true; in riscv_cpu_validate_b()
564 if (!cpu->cfg.ext_zbb) { in riscv_cpu_validate_b()
566 cpu->cfg.ext_zbb = true; in riscv_cpu_validate_b()
572 if (!cpu->cfg.ext_zbs) { in riscv_cpu_validate_b()
574 cpu->cfg.ext_zbs = true; in riscv_cpu_validate_b()
583 * cpu->cfg accordingly.
585 void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp) in riscv_cpu_validate_set_extensions() argument
587 RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(cpu); in riscv_cpu_validate_set_extensions()
588 CPURISCVState *env = &cpu->env; in riscv_cpu_validate_set_extensions()
592 riscv_cpu_validate_g(cpu); in riscv_cpu_validate_set_extensions()
596 riscv_cpu_validate_b(cpu); in riscv_cpu_validate_set_extensions()
628 if (riscv_has_ext(env, RVF) && !cpu->cfg.ext_zicsr) { in riscv_cpu_validate_set_extensions()
633 if ((cpu->cfg.ext_zacas) && !riscv_has_ext(env, RVA)) { in riscv_cpu_validate_set_extensions()
638 if ((cpu->cfg.ext_zawrs) && !riscv_has_ext(env, RVA)) { in riscv_cpu_validate_set_extensions()
643 if (cpu->cfg.ext_zfa && !riscv_has_ext(env, RVF)) { in riscv_cpu_validate_set_extensions()
648 if (cpu->cfg.ext_zfhmin && !riscv_has_ext(env, RVF)) { in riscv_cpu_validate_set_extensions()
653 if (cpu->cfg.ext_zfbfmin && !riscv_has_ext(env, RVF)) { in riscv_cpu_validate_set_extensions()
664 riscv_cpu_validate_v(env, &cpu->cfg, &local_err); in riscv_cpu_validate_set_extensions()
672 if (cpu->cfg.ext_zve64d) { in riscv_cpu_validate_set_extensions()
680 if (cpu->cfg.ext_zve32f) { in riscv_cpu_validate_set_extensions()
687 if (cpu->cfg.ext_zvfhmin && !cpu->cfg.ext_zve32f) { in riscv_cpu_validate_set_extensions()
692 if (cpu->cfg.ext_zvfh && !cpu->cfg.ext_zfhmin) { in riscv_cpu_validate_set_extensions()
697 if (cpu->cfg.ext_zvfbfmin && !cpu->cfg.ext_zve32f) { in riscv_cpu_validate_set_extensions()
702 if (cpu->cfg.ext_zvfbfwma && !cpu->cfg.ext_zvfbfmin) { in riscv_cpu_validate_set_extensions()
707 if ((cpu->cfg.ext_zdinx || cpu->cfg.ext_zhinxmin) && !cpu->cfg.ext_zfinx) { in riscv_cpu_validate_set_extensions()
712 if (cpu->cfg.ext_zfinx) { in riscv_cpu_validate_set_extensions()
713 if (!cpu->cfg.ext_zicsr) { in riscv_cpu_validate_set_extensions()
724 if (cpu->cfg.ext_zcmop && !cpu->cfg.ext_zca) { in riscv_cpu_validate_set_extensions()
729 if (mcc->def->misa_mxl_max != MXL_RV32 && cpu->cfg.ext_zcf) { in riscv_cpu_validate_set_extensions()
734 if (!riscv_has_ext(env, RVF) && cpu->cfg.ext_zcf) { in riscv_cpu_validate_set_extensions()
739 if (!riscv_has_ext(env, RVD) && cpu->cfg.ext_zcd) { in riscv_cpu_validate_set_extensions()
744 if ((cpu->cfg.ext_zcf || cpu->cfg.ext_zcd || cpu->cfg.ext_zcb || in riscv_cpu_validate_set_extensions()
745 cpu->cfg.ext_zcmp || cpu->cfg.ext_zcmt) && !cpu->cfg.ext_zca) { in riscv_cpu_validate_set_extensions()
751 if (cpu->cfg.ext_zcd && (cpu->cfg.ext_zcmp || cpu->cfg.ext_zcmt)) { in riscv_cpu_validate_set_extensions()
757 if (cpu->cfg.ext_zcmt && !cpu->cfg.ext_zicsr) { in riscv_cpu_validate_set_extensions()
762 if ((cpu->cfg.ext_zvbb || cpu->cfg.ext_zvkb || cpu->cfg.ext_zvkg || in riscv_cpu_validate_set_extensions()
763 cpu->cfg.ext_zvkned || cpu->cfg.ext_zvknha || cpu->cfg.ext_zvksed || in riscv_cpu_validate_set_extensions()
764 cpu->cfg.ext_zvksh) && !cpu->cfg.ext_zve32x) { in riscv_cpu_validate_set_extensions()
770 if ((cpu->cfg.ext_zvbc || cpu->cfg.ext_zvknhb) && !cpu->cfg.ext_zve64x) { in riscv_cpu_validate_set_extensions()
777 if (cpu->cfg.ext_zicntr && !cpu->cfg.ext_zicsr) { in riscv_cpu_validate_set_extensions()
782 cpu->cfg.ext_zicntr = false; in riscv_cpu_validate_set_extensions()
785 if (cpu->cfg.ext_zihpm && !cpu->cfg.ext_zicsr) { in riscv_cpu_validate_set_extensions()
790 cpu->cfg.ext_zihpm = false; in riscv_cpu_validate_set_extensions()
793 if (cpu->cfg.ext_zicfiss) { in riscv_cpu_validate_set_extensions()
794 if (!cpu->cfg.ext_zicsr) { in riscv_cpu_validate_set_extensions()
806 if (!cpu->cfg.ext_zimop) { in riscv_cpu_validate_set_extensions()
810 if (cpu->cfg.ext_zca && !cpu->cfg.ext_zcmop) { in riscv_cpu_validate_set_extensions()
816 if (!cpu->cfg.ext_zihpm) { in riscv_cpu_validate_set_extensions()
817 cpu->cfg.pmu_mask = 0; in riscv_cpu_validate_set_extensions()
818 cpu->pmu_avail_ctrs = 0; in riscv_cpu_validate_set_extensions()
821 if (cpu->cfg.ext_zicfilp && !cpu->cfg.ext_zicsr) { in riscv_cpu_validate_set_extensions()
826 if (mcc->def->misa_mxl_max == MXL_RV32 && cpu->cfg.ext_svukte) { in riscv_cpu_validate_set_extensions()
831 if ((cpu->cfg.ext_smctr || cpu->cfg.ext_ssctr) && in riscv_cpu_validate_set_extensions()
832 (!riscv_has_ext(env, RVS) || !cpu->cfg.ext_sscsrind)) { in riscv_cpu_validate_set_extensions()
838 cpu->cfg.ext_smctr = false; in riscv_cpu_validate_set_extensions()
839 cpu->cfg.ext_ssctr = false; in riscv_cpu_validate_set_extensions()
842 if (cpu->cfg.ext_svrsw60t59b && in riscv_cpu_validate_set_extensions()
843 (!cpu->cfg.mmu || mcc->def->misa_mxl_max == MXL_RV32)) { in riscv_cpu_validate_set_extensions()
852 riscv_cpu_disable_priv_spec_isa_exts(cpu); in riscv_cpu_validate_set_extensions()
856 static bool riscv_cpu_validate_profile_satp(RISCVCPU *cpu, in riscv_cpu_validate_profile_satp() argument
860 int satp_max = cpu->cfg.max_satp_mode; in riscv_cpu_validate_profile_satp()
865 bool is_32bit = riscv_cpu_is_32bit(cpu); in riscv_cpu_validate_profile_satp()
881 static void riscv_cpu_check_parent_profile(RISCVCPU *cpu, in riscv_cpu_check_parent_profile() argument
892 static void riscv_cpu_validate_profile(RISCVCPU *cpu, in riscv_cpu_validate_profile() argument
895 CPURISCVState *env = &cpu->env; in riscv_cpu_validate_profile()
903 profile_impl = riscv_cpu_validate_profile_satp(cpu, profile, in riscv_cpu_validate_profile()
927 if (!riscv_has_ext(&cpu->env, bit)) { in riscv_cpu_validate_profile()
940 if (!isa_ext_is_enabled(cpu, ext_offset)) { in riscv_cpu_validate_profile()
952 riscv_cpu_check_parent_profile(cpu, profile, profile->u_parent); in riscv_cpu_validate_profile()
953 riscv_cpu_check_parent_profile(cpu, profile, profile->s_parent); in riscv_cpu_validate_profile()
956 static void riscv_cpu_validate_profiles(RISCVCPU *cpu) in riscv_cpu_validate_profiles() argument
959 riscv_cpu_validate_profile(cpu, riscv_profiles[i]); in riscv_cpu_validate_profiles()
996 static void cpu_enable_implied_rule(RISCVCPU *cpu, in cpu_enable_implied_rule() argument
999 CPURISCVState *env = &cpu->env; in cpu_enable_implied_rule()
1005 enabled = test_bit(cpu->env.mhartid, rule->enabled); in cpu_enable_implied_rule()
1027 cpu_enable_implied_rule(cpu, ir); in cpu_enable_implied_rule()
1036 cpu_cfg_ext_auto_update(cpu, rule->implied_multi_exts[i], true); in cpu_enable_implied_rule()
1043 cpu_enable_implied_rule(cpu, ir); in cpu_enable_implied_rule()
1048 bitmap_set(rule->enabled, cpu->env.mhartid, 1); in cpu_enable_implied_rule()
1054 static void cpu_enable_zc_implied_rules(RISCVCPU *cpu) in cpu_enable_zc_implied_rules() argument
1056 RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(cpu); in cpu_enable_zc_implied_rules()
1057 CPURISCVState *env = &cpu->env; in cpu_enable_zc_implied_rules()
1059 if (cpu->cfg.ext_zce) { in cpu_enable_zc_implied_rules()
1060 cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zca), true); in cpu_enable_zc_implied_rules()
1061 cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcb), true); in cpu_enable_zc_implied_rules()
1062 cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcmp), true); in cpu_enable_zc_implied_rules()
1063 cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcmt), true); in cpu_enable_zc_implied_rules()
1066 cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcf), true); in cpu_enable_zc_implied_rules()
1072 cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zca), true); in cpu_enable_zc_implied_rules()
1075 cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcf), true); in cpu_enable_zc_implied_rules()
1079 cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcd), true); in cpu_enable_zc_implied_rules()
1084 static void riscv_cpu_enable_implied_rules(RISCVCPU *cpu) in riscv_cpu_enable_implied_rules() argument
1090 cpu_enable_zc_implied_rules(cpu); in riscv_cpu_enable_implied_rules()
1094 if (riscv_has_ext(&cpu->env, rule->ext)) { in riscv_cpu_enable_implied_rules()
1095 cpu_enable_implied_rule(cpu, rule); in riscv_cpu_enable_implied_rules()
1101 if (isa_ext_is_enabled(cpu, rule->ext)) { in riscv_cpu_enable_implied_rules()
1102 cpu_enable_implied_rule(cpu, rule); in riscv_cpu_enable_implied_rules()
1107 void riscv_tcg_cpu_finalize_features(RISCVCPU *cpu, Error **errp) in riscv_tcg_cpu_finalize_features() argument
1109 CPURISCVState *env = &cpu->env; in riscv_tcg_cpu_finalize_features()
1113 riscv_cpu_enable_implied_rules(cpu); in riscv_tcg_cpu_finalize_features()
1121 riscv_cpu_update_named_features(cpu); in riscv_tcg_cpu_finalize_features()
1122 riscv_cpu_validate_profiles(cpu); in riscv_tcg_cpu_finalize_features()
1124 if (cpu->cfg.ext_smepmp && !cpu->cfg.pmp) { in riscv_tcg_cpu_finalize_features()
1133 riscv_cpu_validate_set_extensions(cpu, &local_err); in riscv_tcg_cpu_finalize_features()
1139 if (cpu->cfg.pmu_mask) { in riscv_tcg_cpu_finalize_features()
1140 riscv_pmu_init(cpu, &local_err); in riscv_tcg_cpu_finalize_features()
1146 if (cpu->cfg.ext_sscofpmf) { in riscv_tcg_cpu_finalize_features()
1147 cpu->pmu_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, in riscv_tcg_cpu_finalize_features()
1148 riscv_pmu_timer_cb, cpu); in riscv_tcg_cpu_finalize_features()
1154 void riscv_tcg_cpu_finalize_dynamic_decoder(RISCVCPU *cpu) in riscv_tcg_cpu_finalize_dynamic_decoder() argument
1160 decoder_table[i].guard_func(&cpu->cfg)) { in riscv_tcg_cpu_finalize_dynamic_decoder()
1166 cpu->decoders = dynamic_decoders; in riscv_tcg_cpu_finalize_dynamic_decoder()
1169 bool riscv_cpu_tcg_compatible(RISCVCPU *cpu) in riscv_cpu_tcg_compatible() argument
1171 return object_dynamic_cast(OBJECT(cpu), TYPE_RISCV_CPU_HOST) == NULL; in riscv_cpu_tcg_compatible()
1179 static void riscv_cpu_set_profile(RISCVCPU *cpu, in riscv_cpu_set_profile() argument
1186 riscv_cpu_set_profile(cpu, profile->u_parent, enabled); in riscv_cpu_set_profile()
1190 riscv_cpu_set_profile(cpu, profile->s_parent, enabled); in riscv_cpu_set_profile()
1196 cpu->env.priv_ver = profile->priv_spec; in riscv_cpu_set_profile()
1200 object_property_set_bool(OBJECT(cpu), "mmu", true, NULL); in riscv_cpu_set_profile()
1202 riscv_cpu_is_32bit(cpu)); in riscv_cpu_set_profile()
1203 object_property_set_bool(OBJECT(cpu), satp_prop, true, NULL); in riscv_cpu_set_profile()
1224 riscv_cpu_write_misa_bit(cpu, bit, profile->enabled); in riscv_cpu_set_profile()
1232 riscv_cpu_enable_named_feat(cpu, ext_offset); in riscv_cpu_set_profile()
1235 cpu_bump_multi_ext_priv_ver(&cpu->env, ext_offset); in riscv_cpu_set_profile()
1239 isa_ext_update_enabled(cpu, ext_offset, profile->enabled); in riscv_cpu_set_profile()
1252 RISCVCPU *cpu = RISCV_CPU(cs); in riscv_tcg_cpu_realize() local
1254 if (!riscv_cpu_tcg_compatible(cpu)) { in riscv_tcg_cpu_realize()
1255 g_autofree char *name = riscv_cpu_get_name(cpu); in riscv_tcg_cpu_realize()
1256 error_setg(errp, "'%s' CPU is not compatible with TCG acceleration", in riscv_tcg_cpu_realize()
1262 RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(cpu); in riscv_tcg_cpu_realize()
1272 CPURISCVState *env = &cpu->env; in riscv_tcg_cpu_realize()
1274 tcg_cflags_set(CPU(cs), CF_PCREL); in riscv_tcg_cpu_realize()
1276 if (cpu->cfg.ext_sstc) { in riscv_tcg_cpu_realize()
1277 riscv_timer_init(cpu); in riscv_tcg_cpu_realize()
1299 RISCVCPU *cpu = RISCV_CPU(obj); in cpu_set_misa_ext_cfg() local
1300 CPURISCVState *env = &cpu->env; in cpu_set_misa_ext_cfg()
1318 g_autofree char *cpuname = riscv_cpu_get_name(cpu); in cpu_set_misa_ext_cfg()
1319 error_setg(errp, "'%s' CPU does not allow enabling extensions", in cpu_set_misa_ext_cfg()
1333 riscv_cpu_write_misa_bit(cpu, misa_bit, value); in cpu_set_misa_ext_cfg()
1341 RISCVCPU *cpu = RISCV_CPU(obj); in cpu_get_misa_ext_cfg() local
1342 CPURISCVState *env = &cpu->env; in cpu_get_misa_ext_cfg()
1407 RISCVCPU *cpu = RISCV_CPU(obj); in cpu_set_profile() local
1416 if (cpu->env.misa_mxl != MXL_RV64) { in cpu_set_profile()
1428 riscv_cpu_set_profile(cpu, profile, value); in cpu_set_profile()
1464 RISCVCPU *cpu = RISCV_CPU(obj); in cpu_set_multi_ext_cfg() local
1474 prev_val = isa_ext_is_enabled(cpu, multi_ext_cfg->offset); in cpu_set_multi_ext_cfg()
1481 g_autofree char *cpuname = riscv_cpu_get_name(cpu); in cpu_set_multi_ext_cfg()
1482 error_setg(errp, "'%s' CPU does not allow enabling extensions", in cpu_set_multi_ext_cfg()
1488 cpu_bump_multi_ext_priv_ver(&cpu->env, multi_ext_cfg->offset); in cpu_set_multi_ext_cfg()
1491 isa_ext_update_enabled(cpu, multi_ext_cfg->offset, value); in cpu_set_multi_ext_cfg()
1539 * Add CPU properties with user-facing flags.
1560 * The 'max' type CPU will have all possible ratified
1565 RISCVCPU *cpu = RISCV_CPU(obj); in riscv_init_max_cpu_extensions() local
1566 CPURISCVState *env = &cpu->env; in riscv_init_max_cpu_extensions()
1573 isa_ext_update_enabled(cpu, prop->offset, true); in riscv_init_max_cpu_extensions()
1580 cpu->cfg.ext_svade = false; in riscv_init_max_cpu_extensions()
1586 isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zfinx), false); in riscv_init_max_cpu_extensions()
1587 isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zdinx), false); in riscv_init_max_cpu_extensions()
1588 isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zhinx), false); in riscv_init_max_cpu_extensions()
1589 isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zhinxmin), false); in riscv_init_max_cpu_extensions()
1591 isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zce), false); in riscv_init_max_cpu_extensions()
1592 isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zcmp), false); in riscv_init_max_cpu_extensions()
1593 isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zcmt), false); in riscv_init_max_cpu_extensions()
1596 isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zcf), false); in riscv_init_max_cpu_extensions()
1598 isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_svrsw60t59b), false); in riscv_init_max_cpu_extensions()
1605 if (cpu->cfg.ext_smrnmi) { in riscv_init_max_cpu_extensions()
1606 isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_smrnmi), false); in riscv_init_max_cpu_extensions()
1614 if (cpu->cfg.ext_smdbltrp) { in riscv_init_max_cpu_extensions()
1615 isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_smdbltrp), false); in riscv_init_max_cpu_extensions()
1626 RISCVCPU *cpu = RISCV_CPU(cs); in riscv_tcg_cpu_instance_init() local
1627 Object *obj = OBJECT(cpu); in riscv_tcg_cpu_instance_init()