Lines Matching full:cpu
2 * riscv TCG cpu class initialization
22 #include "tcg-cpu.h"
23 #include "cpu.h"
33 #include "accel/accel-cpu-target.h"
34 #include "accel/tcg/cpu-ops.h"
73 static void riscv_cpu_write_misa_bit(RISCVCPU *cpu, uint32_t bit,
76 CPURISCVState *env = &cpu->env;
104 RISCVCPU *cpu = env_archcpu(env);
109 if (cpu->cfg.ext_zve32x) {
122 uint32_t vlmax = vext_get_vlmax(cpu->cfg.vlenb, vsew, lmul);
180 if (cpu->cfg.debug && !icount_enabled()) {
202 RISCVCPU *cpu = RISCV_CPU(cs);
203 CPURISCVState *env = &cpu->env;
220 RISCVCPU *cpu = RISCV_CPU(cs);
221 CPURISCVState *env = &cpu->env;
339 static void riscv_cpu_enable_named_feat(RISCVCPU *cpu, uint32_t feat_offset)
347 cpu->cfg.cbom_blocksize = 64;
348 cpu->cfg.cbop_blocksize = 64;
349 cpu->cfg.cboz_blocksize = 64;
353 riscv_cpu_write_misa_bit(cpu, RVH, true);
357 cpu->cfg.ext_smstateen = true;
382 static void cpu_cfg_ext_auto_update(RISCVCPU *cpu, uint32_t ext_offset,
385 CPURISCVState *env = &cpu->env;
386 bool prev_val = isa_ext_is_enabled(cpu, ext_offset);
405 isa_ext_update_enabled(cpu, ext_offset, value);
451 static void riscv_cpu_disable_priv_spec_isa_exts(RISCVCPU *cpu)
453 CPURISCVState *env = &cpu->env;
458 if (isa_ext_is_enabled(cpu, edata->ext_enable_offset) &&
470 * cpu.debug = true is marked as 'sdtrig', priv spec 1.12.
478 isa_ext_update_enabled(cpu, edata->ext_enable_offset, false);
501 static void riscv_cpu_update_named_features(RISCVCPU *cpu)
503 if (cpu->env.priv_ver >= PRIV_VERSION_1_11_0) {
504 cpu->cfg.has_priv_1_11 = true;
507 if (cpu->env.priv_ver >= PRIV_VERSION_1_12_0) {
508 cpu->cfg.has_priv_1_12 = true;
511 if (cpu->env.priv_ver >= PRIV_VERSION_1_13_0) {
512 cpu->cfg.has_priv_1_13 = true;
515 cpu->cfg.ext_zic64b = cpu->cfg.cbom_blocksize == 64 &&
516 cpu->cfg.cbop_blocksize == 64 &&
517 cpu->cfg.cboz_blocksize == 64;
519 cpu->cfg.ext_ssstateen = cpu->cfg.ext_smstateen;
521 cpu->cfg.ext_sha = riscv_has_ext(&cpu->env, RVH) &&
522 cpu->cfg.ext_ssstateen;
524 cpu->cfg.ext_ziccrse = cpu->cfg.has_priv_1_11;
527 static void riscv_cpu_validate_g(RISCVCPU *cpu)
536 if (riscv_has_ext(&cpu->env, bit)) {
541 riscv_cpu_write_misa_bit(cpu, bit, true);
550 if (!cpu->cfg.ext_zicsr) {
552 cpu->cfg.ext_zicsr = true;
558 if (!cpu->cfg.ext_zifencei) {
560 cpu->cfg.ext_zifencei = true;
567 static void riscv_cpu_validate_b(RISCVCPU *cpu)
571 if (!cpu->cfg.ext_zba) {
573 cpu->cfg.ext_zba = true;
579 if (!cpu->cfg.ext_zbb) {
581 cpu->cfg.ext_zbb = true;
587 if (!cpu->cfg.ext_zbs) {
589 cpu->cfg.ext_zbs = true;
598 * cpu->cfg accordingly.
600 void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
602 RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(cpu);
603 CPURISCVState *env = &cpu->env;
607 riscv_cpu_validate_g(cpu);
611 riscv_cpu_validate_b(cpu);
643 if (riscv_has_ext(env, RVF) && !cpu->cfg.ext_zicsr) {
648 if ((cpu->cfg.ext_zacas) && !riscv_has_ext(env, RVA)) {
653 if ((cpu->cfg.ext_zawrs) && !riscv_has_ext(env, RVA)) {
658 if (cpu->cfg.ext_zfa && !riscv_has_ext(env, RVF)) {
663 if (cpu->cfg.ext_zfhmin && !riscv_has_ext(env, RVF)) {
668 if (cpu->cfg.ext_zfbfmin && !riscv_has_ext(env, RVF)) {
678 if (cpu->cfg.ext_zve32x) {
679 riscv_cpu_validate_v(env, &cpu->cfg, &local_err);
687 if (cpu->cfg.ext_zve64d) {
695 if (cpu->cfg.ext_zve32f) {
702 if (cpu->cfg.ext_zvfhmin && !cpu->cfg.ext_zve32f) {
707 if (cpu->cfg.ext_zvfh && !cpu->cfg.ext_zfhmin) {
712 if (cpu->cfg.ext_zvfbfmin && !cpu->cfg.ext_zve32f) {
717 if (cpu->cfg.ext_zvfbfwma && !cpu->cfg.ext_zvfbfmin) {
722 if ((cpu->cfg.ext_zdinx || cpu->cfg.ext_zhinxmin) && !cpu->cfg.ext_zfinx) {
727 if (cpu->cfg.ext_zfinx) {
728 if (!cpu->cfg.ext_zicsr) {
739 if (cpu->cfg.ext_zcmop && !cpu->cfg.ext_zca) {
744 if (mcc->def->misa_mxl_max != MXL_RV32 && cpu->cfg.ext_zcf) {
749 if (!riscv_has_ext(env, RVF) && cpu->cfg.ext_zcf) {
754 if (!riscv_has_ext(env, RVD) && cpu->cfg.ext_zcd) {
759 if ((cpu->cfg.ext_zcf || cpu->cfg.ext_zcd || cpu->cfg.ext_zcb ||
760 cpu->cfg.ext_zcmp || cpu->cfg.ext_zcmt) && !cpu->cfg.ext_zca) {
766 if (cpu->cfg.ext_zcd && (cpu->cfg.ext_zcmp || cpu->cfg.ext_zcmt)) {
772 if (cpu->cfg.ext_zcmt && !cpu->cfg.ext_zicsr) {
777 if ((cpu->cfg.ext_zvbb || cpu->cfg.ext_zvkb || cpu->cfg.ext_zvkg ||
778 cpu->cfg.ext_zvkned || cpu->cfg.ext_zvknha || cpu->cfg.ext_zvksed ||
779 cpu->cfg.ext_zvksh) && !cpu->cfg.ext_zve32x) {
785 if ((cpu->cfg.ext_zvbc || cpu->cfg.ext_zvknhb) && !cpu->cfg.ext_zve64x) {
792 if (cpu->cfg.ext_zicntr && !cpu->cfg.ext_zicsr) {
797 cpu->cfg.ext_zicntr = false;
800 if (cpu->cfg.ext_zihpm && !cpu->cfg.ext_zicsr) {
805 cpu->cfg.ext_zihpm = false;
808 if (cpu->cfg.ext_zicfiss) {
809 if (!cpu->cfg.ext_zicsr) {
821 if (!cpu->cfg.ext_zimop) {
825 if (cpu->cfg.ext_zca && !cpu->cfg.ext_zcmop) {
831 if (!cpu->cfg.ext_zihpm) {
832 cpu->cfg.pmu_mask = 0;
833 cpu->pmu_avail_ctrs = 0;
836 if (cpu->cfg.ext_zicfilp && !cpu->cfg.ext_zicsr) {
841 if (mcc->def->misa_mxl_max == MXL_RV32 && cpu->cfg.ext_svukte) {
846 if ((cpu->cfg.ext_smctr || cpu->cfg.ext_ssctr) &&
847 (!riscv_has_ext(env, RVS) || !cpu->cfg.ext_sscsrind)) {
853 cpu->cfg.ext_smctr = false;
854 cpu->cfg.ext_ssctr = false;
857 if (cpu->cfg.ext_svrsw60t59b &&
858 (!cpu->cfg.mmu || mcc->def->misa_mxl_max == MXL_RV32)) {
867 riscv_cpu_disable_priv_spec_isa_exts(cpu);
871 static bool riscv_cpu_validate_profile_satp(RISCVCPU *cpu,
875 int satp_max = cpu->cfg.max_satp_mode;
880 bool is_32bit = riscv_cpu_is_32bit(cpu);
896 static void riscv_cpu_check_parent_profile(RISCVCPU *cpu,
907 static void riscv_cpu_validate_profile(RISCVCPU *cpu,
910 CPURISCVState *env = &cpu->env;
918 profile_impl = riscv_cpu_validate_profile_satp(cpu, profile,
942 if (!riscv_has_ext(&cpu->env, bit)) {
955 if (!isa_ext_is_enabled(cpu, ext_offset)) {
967 riscv_cpu_check_parent_profile(cpu, profile, profile->u_parent);
968 riscv_cpu_check_parent_profile(cpu, profile, profile->s_parent);
971 static void riscv_cpu_validate_profiles(RISCVCPU *cpu)
974 riscv_cpu_validate_profile(cpu, riscv_profiles[i]);
1011 static void cpu_enable_implied_rule(RISCVCPU *cpu,
1014 CPURISCVState *env = &cpu->env;
1020 enabled = test_bit(cpu->env.mhartid, rule->enabled);
1042 cpu_enable_implied_rule(cpu, ir);
1051 cpu_cfg_ext_auto_update(cpu, rule->implied_multi_exts[i], true);
1058 cpu_enable_implied_rule(cpu, ir);
1063 bitmap_set(rule->enabled, cpu->env.mhartid, 1);
1069 static void cpu_enable_zc_implied_rules(RISCVCPU *cpu)
1071 RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(cpu);
1072 CPURISCVState *env = &cpu->env;
1074 if (cpu->cfg.ext_zce) {
1075 cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zca), true);
1076 cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcb), true);
1077 cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcmp), true);
1078 cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcmt), true);
1081 cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcf), true);
1087 cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zca), true);
1090 cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcf), true);
1094 cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcd), true);
1099 static void riscv_cpu_enable_implied_rules(RISCVCPU *cpu)
1105 cpu_enable_zc_implied_rules(cpu);
1109 if (riscv_has_ext(&cpu->env, rule->ext)) {
1110 cpu_enable_implied_rule(cpu, rule);
1116 if (isa_ext_is_enabled(cpu, rule->ext)) {
1117 cpu_enable_implied_rule(cpu, rule);
1122 void riscv_tcg_cpu_finalize_features(RISCVCPU *cpu, Error **errp)
1124 CPURISCVState *env = &cpu->env;
1128 riscv_cpu_enable_implied_rules(cpu);
1136 riscv_cpu_update_named_features(cpu);
1137 riscv_cpu_validate_profiles(cpu);
1139 if (cpu->cfg.ext_smepmp && !cpu->cfg.pmp) {
1148 riscv_cpu_validate_set_extensions(cpu, &local_err);
1154 if (cpu->cfg.pmu_mask) {
1155 riscv_pmu_init(cpu, &local_err);
1161 if (cpu->cfg.ext_sscofpmf) {
1162 cpu->pmu_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL,
1163 riscv_pmu_timer_cb, cpu);
1169 void riscv_tcg_cpu_finalize_dynamic_decoder(RISCVCPU *cpu)
1175 decoder_table[i].guard_func(&cpu->cfg)) {
1181 cpu->decoders = dynamic_decoders;
1184 bool riscv_cpu_tcg_compatible(RISCVCPU *cpu)
1186 return object_dynamic_cast(OBJECT(cpu), TYPE_RISCV_CPU_HOST) == NULL;
1194 static void riscv_cpu_set_profile(RISCVCPU *cpu,
1201 riscv_cpu_set_profile(cpu, profile->u_parent, enabled);
1205 riscv_cpu_set_profile(cpu, profile->s_parent, enabled);
1211 cpu->env.priv_ver = profile->priv_spec;
1215 object_property_set_bool(OBJECT(cpu), "mmu", true, NULL);
1217 riscv_cpu_is_32bit(cpu));
1218 object_property_set_bool(OBJECT(cpu), satp_prop, true, NULL);
1239 riscv_cpu_write_misa_bit(cpu, bit, profile->enabled);
1247 riscv_cpu_enable_named_feat(cpu, ext_offset);
1250 cpu_bump_multi_ext_priv_ver(&cpu->env, ext_offset);
1254 isa_ext_update_enabled(cpu, ext_offset, profile->enabled);
1267 RISCVCPU *cpu = RISCV_CPU(cs);
1269 if (!riscv_cpu_tcg_compatible(cpu)) {
1270 g_autofree char *name = riscv_cpu_get_name(cpu);
1271 error_setg(errp, "'%s' CPU is not compatible with TCG acceleration",
1277 RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(cpu);
1287 CPURISCVState *env = &cpu->env;
1289 tcg_cflags_set(CPU(cs), CF_PCREL);
1291 if (cpu->cfg.ext_sstc) {
1292 riscv_timer_init(cpu);
1314 RISCVCPU *cpu = RISCV_CPU(obj);
1315 CPURISCVState *env = &cpu->env;
1333 g_autofree char *cpuname = riscv_cpu_get_name(cpu);
1334 error_setg(errp, "'%s' CPU does not allow enabling extensions",
1348 riscv_cpu_write_misa_bit(cpu, misa_bit, value);
1356 RISCVCPU *cpu = RISCV_CPU(obj);
1357 CPURISCVState *env = &cpu->env;
1422 RISCVCPU *cpu = RISCV_CPU(obj);
1431 if (cpu->env.misa_mxl != MXL_RV64) {
1443 riscv_cpu_set_profile(cpu, profile, value);
1479 RISCVCPU *cpu = RISCV_CPU(obj);
1489 prev_val = isa_ext_is_enabled(cpu, multi_ext_cfg->offset);
1496 g_autofree char *cpuname = riscv_cpu_get_name(cpu);
1497 error_setg(errp, "'%s' CPU does not allow enabling extensions",
1503 cpu_bump_multi_ext_priv_ver(&cpu->env, multi_ext_cfg->offset);
1506 isa_ext_update_enabled(cpu, multi_ext_cfg->offset, value);
1554 * Add CPU properties with user-facing flags.
1575 * The 'max' type CPU will have all possible ratified
1580 RISCVCPU *cpu = RISCV_CPU(obj);
1581 CPURISCVState *env = &cpu->env;
1588 isa_ext_update_enabled(cpu, prop->offset, true);
1595 cpu->cfg.ext_svade = false;
1601 isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zfinx), false);
1602 isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zdinx), false);
1603 isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zhinx), false);
1604 isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zhinxmin), false);
1606 isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zce), false);
1607 isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zcmp), false);
1608 isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zcmt), false);
1611 isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zcf), false);
1613 isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_svrsw60t59b), false);
1620 if (cpu->cfg.ext_smrnmi) {
1621 isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_smrnmi), false);
1629 if (cpu->cfg.ext_smdbltrp) {
1630 isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_smdbltrp), false);
1641 RISCVCPU *cpu = RISCV_CPU(cs);
1642 Object *obj = OBJECT(cpu);