275 int riscv_pmu_incr_ctr(RISCVCPU *cpu, enum riscv_pmu_event_idx event_idx)  in riscv_pmu_incr_ctr()  argument
286                                 GUINT_TO_POINTER(event_idx));  in riscv_pmu_incr_ctr()
309     uint32_t event_idx;  in riscv_pmu_ctr_monitor_instructions()  local
322     event_idx = RISCV_PMU_EVENT_HW_INSTRUCTIONS;  in riscv_pmu_ctr_monitor_instructions()
324                                GUINT_TO_POINTER(event_idx)));  in riscv_pmu_ctr_monitor_instructions()
335     uint32_t event_idx;  in riscv_pmu_ctr_monitor_cycles()  local
348     event_idx = RISCV_PMU_EVENT_HW_CPU_CYCLES;  in riscv_pmu_ctr_monitor_cycles()
350                                GUINT_TO_POINTER(event_idx)));  in riscv_pmu_ctr_monitor_cycles()
382     uint32_t event_idx;  in riscv_pmu_update_event_map()  local
400     event_idx = value & MHPMEVENT_IDX_MASK;  in riscv_pmu_update_event_map()
402                             GUINT_TO_POINTER(event_idx))) {  in riscv_pmu_update_event_map()
406     switch (event_idx) {  in riscv_pmu_update_event_map()
417     g_hash_table_insert(cpu->pmu_event_ctr_map, GUINT_TO_POINTER(event_idx),  in riscv_pmu_update_event_map()