29 G_NORETURN void riscv_raise_exception(CPURISCVState *env,  in riscv_raise_exception()  argument
32     CPUState *cs = env_cpu(env);  in riscv_raise_exception()
37 void helper_raise_exception(CPURISCVState *env, uint32_t exception)  in helper_raise_exception()  argument
39     riscv_raise_exception(env, exception, 0);  in helper_raise_exception()
42 target_ulong helper_csrr(CPURISCVState *env, int csr)  in helper_csrr()  argument
50         riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());  in helper_csrr()
54     RISCVException ret = riscv_csrr(env, csr, &val);  in helper_csrr()
57         riscv_raise_exception(env, ret, GETPC());  in helper_csrr()
62 void helper_csrw(CPURISCVState *env, int csr, target_ulong src)  in helper_csrw()  argument
64     target_ulong mask = env->xl == MXL_RV32 ? UINT32_MAX : (target_ulong)-1;  in helper_csrw()
65     RISCVException ret = riscv_csrrw(env, csr, NULL, src, mask);  in helper_csrw()
68         riscv_raise_exception(env, ret, GETPC());  in helper_csrw()
72 target_ulong helper_csrrw(CPURISCVState *env, int csr,  in helper_csrrw()  argument
76     RISCVException ret = riscv_csrrw(env, csr, &val, src, write_mask);  in helper_csrrw()
79         riscv_raise_exception(env, ret, GETPC());  in helper_csrrw()
84 target_ulong helper_csrr_i128(CPURISCVState *env, int csr)  in helper_csrr_i128()  argument
87     RISCVException ret = riscv_csrr_i128(env, csr, &rv);  in helper_csrr_i128()
90         riscv_raise_exception(env, ret, GETPC());  in helper_csrr_i128()
93     env->retxh = int128_gethi(rv);  in helper_csrr_i128()
97 void helper_csrw_i128(CPURISCVState *env, int csr,  in helper_csrw_i128()  argument
100     RISCVException ret = riscv_csrrw_i128(env, csr, NULL,  in helper_csrw_i128()
105         riscv_raise_exception(env, ret, GETPC());  in helper_csrw_i128()
109 target_ulong helper_csrrw_i128(CPURISCVState *env, int csr,  in helper_csrrw_i128()  argument
114     RISCVException ret = riscv_csrrw_i128(env, csr, &rv,  in helper_csrrw_i128()
119         riscv_raise_exception(env, ret, GETPC());  in helper_csrrw_i128()
122     env->retxh = int128_gethi(rv);  in helper_csrrw_i128()
134 static void check_zicbo_envcfg(CPURISCVState *env, target_ulong envbits,  in check_zicbo_envcfg()  argument
138     if ((env->priv < PRV_M) && !get_field(env->menvcfg, envbits)) {  in check_zicbo_envcfg()
139         riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, ra);  in check_zicbo_envcfg()
142     if (env->virt_enabled &&  in check_zicbo_envcfg()
143         (((env->priv <= PRV_S) && !get_field(env->henvcfg, envbits)) ||  in check_zicbo_envcfg()
144          ((env->priv < PRV_S) && !get_field(env->senvcfg, envbits)))) {  in check_zicbo_envcfg()
145         riscv_raise_exception(env, RISCV_EXCP_VIRT_INSTRUCTION_FAULT, ra);  in check_zicbo_envcfg()
148     if ((env->priv < PRV_S) && !get_field(env->senvcfg, envbits)) {  in check_zicbo_envcfg()
149         riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, ra);  in check_zicbo_envcfg()
154 void helper_cbo_zero(CPURISCVState *env, target_ulong address)  in helper_cbo_zero()  argument
156     RISCVCPU *cpu = env_archcpu(env);  in helper_cbo_zero()
158     int mmu_idx = riscv_env_mmu_index(env, false);  in helper_cbo_zero()
162     check_zicbo_envcfg(env, MENVCFG_CBZE, ra);  in helper_cbo_zero()
171     mem = probe_write(env, address, cbozlen, mmu_idx, ra);  in helper_cbo_zero()
188             cpu_stb_mmuidx_ra(env, address + i, 0, mmu_idx, ra);  in helper_cbo_zero()
201 static void check_zicbom_access(CPURISCVState *env,  in check_zicbom_access()  argument
205     RISCVCPU *cpu = env_archcpu(env);  in check_zicbom_access()
206     int mmu_idx = riscv_env_mmu_index(env, false);  in check_zicbom_access()
226     ret = probe_access_flags(env, address, cbomlen, MMU_DATA_LOAD,  in check_zicbom_access()
239     probe_write(env, address, cbomlen, mmu_idx, ra);  in check_zicbom_access()
242 void helper_cbo_clean_flush(CPURISCVState *env, target_ulong address)  in helper_cbo_clean_flush()  argument
245     check_zicbo_envcfg(env, MENVCFG_CBCFE, ra);  in helper_cbo_clean_flush()
246     check_zicbom_access(env, address, ra);  in helper_cbo_clean_flush()
251 void helper_cbo_inval(CPURISCVState *env, target_ulong address)  in helper_cbo_inval()  argument
254     check_zicbo_envcfg(env, MENVCFG_CBIE, ra);  in helper_cbo_inval()
255     check_zicbom_access(env, address, ra);  in helper_cbo_inval()
262 target_ulong helper_sret(CPURISCVState *env)  in helper_sret()  argument
265     target_ulong prev_priv, prev_virt = env->virt_enabled;  in helper_sret()
267     if (!(env->priv >= PRV_S)) {  in helper_sret()
268         riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());  in helper_sret()
271     target_ulong retpc = env->sepc;  in helper_sret()
272     if (!riscv_has_ext(env, RVC) && (retpc & 0x3)) {  in helper_sret()
273         riscv_raise_exception(env, RISCV_EXCP_INST_ADDR_MIS, GETPC());  in helper_sret()
276     if (get_field(env->mstatus, MSTATUS_TSR) && !(env->priv >= PRV_M)) {  in helper_sret()
277         riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());  in helper_sret()
280     if (env->virt_enabled && get_field(env->hstatus, HSTATUS_VTSR)) {  in helper_sret()
281         riscv_raise_exception(env, RISCV_EXCP_VIRT_INSTRUCTION_FAULT, GETPC());  in helper_sret()
284     mstatus = env->mstatus;  in helper_sret()
290     if (env->priv_ver >= PRIV_VERSION_1_12_0) {  in helper_sret()
293     env->mstatus = mstatus;  in helper_sret()
295     if (riscv_has_ext(env, RVH) && !env->virt_enabled) {  in helper_sret()
297         target_ulong hstatus = env->hstatus;  in helper_sret()
303         env->hstatus = hstatus;  in helper_sret()
306             riscv_cpu_swap_hypervisor_regs(env);  in helper_sret()
310     riscv_cpu_set_mode(env, prev_priv, prev_virt);  in helper_sret()
316     if (cpu_get_fcfien(env)) {  in helper_sret()
317         env->elp = get_field(env->mstatus, MSTATUS_SPELP);  in helper_sret()
319     env->mstatus = set_field(env->mstatus, MSTATUS_SPELP, 0);  in helper_sret()
324 target_ulong helper_mret(CPURISCVState *env)  in helper_mret()  argument
326     if (!(env->priv >= PRV_M)) {  in helper_mret()
327         riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());  in helper_mret()
330     target_ulong retpc = env->mepc;  in helper_mret()
331     if (!riscv_has_ext(env, RVC) && (retpc & 0x3)) {  in helper_mret()
332         riscv_raise_exception(env, RISCV_EXCP_INST_ADDR_MIS, GETPC());  in helper_mret()
335     uint64_t mstatus = env->mstatus;  in helper_mret()
338     if (riscv_cpu_cfg(env)->pmp &&  in helper_mret()
339         !pmp_get_num_rules(env) && (prev_priv != PRV_M)) {  in helper_mret()
340         riscv_raise_exception(env, RISCV_EXCP_INST_ACCESS_FAULT, GETPC());  in helper_mret()
343     target_ulong prev_virt = get_field(env->mstatus, MSTATUS_MPV) &&  in helper_mret()
349                         riscv_has_ext(env, RVU) ? PRV_U : PRV_M);  in helper_mret()
351     if ((env->priv_ver >= PRIV_VERSION_1_12_0) && (prev_priv != PRV_M)) {  in helper_mret()
354     env->mstatus = mstatus;  in helper_mret()
356     if (riscv_has_ext(env, RVH) && prev_virt) {  in helper_mret()
357         riscv_cpu_swap_hypervisor_regs(env);  in helper_mret()
360     riscv_cpu_set_mode(env, prev_priv, prev_virt);  in helper_mret()
365     if (cpu_get_fcfien(env)) {  in helper_mret()
366         env->elp = get_field(env->mstatus, MSTATUS_MPELP);  in helper_mret()
368     env->mstatus = set_field(env->mstatus, MSTATUS_MPELP, 0);  in helper_mret()
373 void helper_wfi(CPURISCVState *env)  in helper_wfi()  argument
375     CPUState *cs = env_cpu(env);  in helper_wfi()
376     bool rvs = riscv_has_ext(env, RVS);  in helper_wfi()
377     bool prv_u = env->priv == PRV_U;  in helper_wfi()
378     bool prv_s = env->priv == PRV_S;  in helper_wfi()
380     if (((prv_s || (!rvs && prv_u)) && get_field(env->mstatus, MSTATUS_TW)) ||  in helper_wfi()
381         (rvs && prv_u && !env->virt_enabled)) {  in helper_wfi()
382         riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());  in helper_wfi()
383     } else if (env->virt_enabled &&  in helper_wfi()
384                (prv_u || (prv_s && get_field(env->hstatus, HSTATUS_VTW)))) {  in helper_wfi()
385         riscv_raise_exception(env, RISCV_EXCP_VIRT_INSTRUCTION_FAULT, GETPC());  in helper_wfi()
393 void helper_wrs_nto(CPURISCVState *env)  in helper_wrs_nto()  argument
395     if (env->virt_enabled && (env->priv == PRV_S || env->priv == PRV_U) &&  in helper_wrs_nto()
396         get_field(env->hstatus, HSTATUS_VTW) &&  in helper_wrs_nto()
397         !get_field(env->mstatus, MSTATUS_TW)) {  in helper_wrs_nto()
398         riscv_raise_exception(env, RISCV_EXCP_VIRT_INSTRUCTION_FAULT, GETPC());  in helper_wrs_nto()
399     } else if (env->priv != PRV_M && get_field(env->mstatus, MSTATUS_TW)) {  in helper_wrs_nto()
400         riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());  in helper_wrs_nto()
404 void helper_tlb_flush(CPURISCVState *env)  in helper_tlb_flush()  argument
406     CPUState *cs = env_cpu(env);  in helper_tlb_flush()
407     if (!env->virt_enabled &&  in helper_tlb_flush()
408         (env->priv == PRV_U ||  in helper_tlb_flush()
409          (env->priv == PRV_S && get_field(env->mstatus, MSTATUS_TVM)))) {  in helper_tlb_flush()
410         riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());  in helper_tlb_flush()
411     } else if (env->virt_enabled &&  in helper_tlb_flush()
412                (env->priv == PRV_U || get_field(env->hstatus, HSTATUS_VTVM))) {  in helper_tlb_flush()
413         riscv_raise_exception(env, RISCV_EXCP_VIRT_INSTRUCTION_FAULT, GETPC());  in helper_tlb_flush()
419 void helper_tlb_flush_all(CPURISCVState *env)  in helper_tlb_flush_all()  argument
421     CPUState *cs = env_cpu(env);  in helper_tlb_flush_all()
425 void helper_hyp_tlb_flush(CPURISCVState *env)  in helper_hyp_tlb_flush()  argument
427     CPUState *cs = env_cpu(env);  in helper_hyp_tlb_flush()
429     if (env->virt_enabled) {  in helper_hyp_tlb_flush()
430         riscv_raise_exception(env, RISCV_EXCP_VIRT_INSTRUCTION_FAULT, GETPC());  in helper_hyp_tlb_flush()
433     if (env->priv == PRV_M ||  in helper_hyp_tlb_flush()
434         (env->priv == PRV_S && !env->virt_enabled)) {  in helper_hyp_tlb_flush()
439     riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());  in helper_hyp_tlb_flush()
442 void helper_hyp_gvma_tlb_flush(CPURISCVState *env)  in helper_hyp_gvma_tlb_flush()  argument
444     if (env->priv == PRV_S && !env->virt_enabled &&  in helper_hyp_gvma_tlb_flush()
445         get_field(env->mstatus, MSTATUS_TVM)) {  in helper_hyp_gvma_tlb_flush()
446         riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());  in helper_hyp_gvma_tlb_flush()
449     helper_hyp_tlb_flush(env);  in helper_hyp_gvma_tlb_flush()
452 static int check_access_hlsv(CPURISCVState *env, bool x, uintptr_t ra)  in check_access_hlsv()  argument
454     if (env->priv == PRV_M) {  in check_access_hlsv()
456     } else if (env->virt_enabled) {  in check_access_hlsv()
457         riscv_raise_exception(env, RISCV_EXCP_VIRT_INSTRUCTION_FAULT, ra);  in check_access_hlsv()
458     } else if (env->priv == PRV_U && !get_field(env->hstatus, HSTATUS_HU)) {  in check_access_hlsv()
459         riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, ra);  in check_access_hlsv()
462     int mode = get_field(env->hstatus, HSTATUS_SPVP);  in check_access_hlsv()
463     if (!x && mode == PRV_S && get_field(env->vsstatus, MSTATUS_SUM)) {  in check_access_hlsv()
469 target_ulong helper_hyp_hlv_bu(CPURISCVState *env, target_ulong addr)  in helper_hyp_hlv_bu()  argument
472     int mmu_idx = check_access_hlsv(env, false, ra);  in helper_hyp_hlv_bu()
475     return cpu_ldb_mmu(env, addr, oi, ra);  in helper_hyp_hlv_bu()
478 target_ulong helper_hyp_hlv_hu(CPURISCVState *env, target_ulong addr)  in helper_hyp_hlv_hu()  argument
481     int mmu_idx = check_access_hlsv(env, false, ra);  in helper_hyp_hlv_hu()
484     return cpu_ldw_mmu(env, addr, oi, ra);  in helper_hyp_hlv_hu()
487 target_ulong helper_hyp_hlv_wu(CPURISCVState *env, target_ulong addr)  in helper_hyp_hlv_wu()  argument
490     int mmu_idx = check_access_hlsv(env, false, ra);  in helper_hyp_hlv_wu()
493     return cpu_ldl_mmu(env, addr, oi, ra);  in helper_hyp_hlv_wu()
496 target_ulong helper_hyp_hlv_d(CPURISCVState *env, target_ulong addr)  in helper_hyp_hlv_d()  argument
499     int mmu_idx = check_access_hlsv(env, false, ra);  in helper_hyp_hlv_d()
502     return cpu_ldq_mmu(env, addr, oi, ra);  in helper_hyp_hlv_d()
505 void helper_hyp_hsv_b(CPURISCVState *env, target_ulong addr, target_ulong val)  in helper_hyp_hsv_b()  argument
508     int mmu_idx = check_access_hlsv(env, false, ra);  in helper_hyp_hsv_b()
511     cpu_stb_mmu(env, addr, val, oi, ra);  in helper_hyp_hsv_b()
514 void helper_hyp_hsv_h(CPURISCVState *env, target_ulong addr, target_ulong val)  in helper_hyp_hsv_h()  argument
517     int mmu_idx = check_access_hlsv(env, false, ra);  in helper_hyp_hsv_h()
520     cpu_stw_mmu(env, addr, val, oi, ra);  in helper_hyp_hsv_h()
523 void helper_hyp_hsv_w(CPURISCVState *env, target_ulong addr, target_ulong val)  in helper_hyp_hsv_w()  argument
526     int mmu_idx = check_access_hlsv(env, false, ra);  in helper_hyp_hsv_w()
529     cpu_stl_mmu(env, addr, val, oi, ra);  in helper_hyp_hsv_w()
532 void helper_hyp_hsv_d(CPURISCVState *env, target_ulong addr, target_ulong val)  in helper_hyp_hsv_d()  argument
535     int mmu_idx = check_access_hlsv(env, false, ra);  in helper_hyp_hsv_d()
538     cpu_stq_mmu(env, addr, val, oi, ra);  in helper_hyp_hsv_d()
548 target_ulong helper_hyp_hlvx_hu(CPURISCVState *env, target_ulong addr)  in helper_hyp_hlvx_hu()  argument
551     int mmu_idx = check_access_hlsv(env, true, ra);  in helper_hyp_hlvx_hu()
554     return cpu_ldw_code_mmu(env, addr, oi, GETPC());  in helper_hyp_hlvx_hu()
557 target_ulong helper_hyp_hlvx_wu(CPURISCVState *env, target_ulong addr)  in helper_hyp_hlvx_wu()  argument
560     int mmu_idx = check_access_hlsv(env, true, ra);  in helper_hyp_hlvx_wu()
563     return cpu_ldl_code_mmu(env, addr, oi, ra);  in helper_hyp_hlvx_wu()