37     CPURISCVState *env = &cpu->env;  in pmp_post_load()  local
41         pmp_update_rule_addr(env, i);  in pmp_post_load()
43     pmp_update_rule_nums(env);  in pmp_post_load()
66         VMSTATE_STRUCT_ARRAY(env.pmp_state.pmp, RISCVCPU, MAX_RISCV_PMPS,
75     CPURISCVState *env = &cpu->env;  in hyper_needed()  local
77     return riscv_has_ext(env, RVH);  in hyper_needed()
86         VMSTATE_UINTTL(env.hstatus, RISCVCPU),
87         VMSTATE_UINTTL(env.hedeleg, RISCVCPU),
88         VMSTATE_UINT64(env.hideleg, RISCVCPU),
89         VMSTATE_UINT32(env.hcounteren, RISCVCPU),
90         VMSTATE_UINTTL(env.htval, RISCVCPU),
91         VMSTATE_UINTTL(env.htinst, RISCVCPU),
92         VMSTATE_UINTTL(env.hgatp, RISCVCPU),
93         VMSTATE_UINTTL(env.hgeie, RISCVCPU),
94         VMSTATE_UINTTL(env.hgeip, RISCVCPU),
95         VMSTATE_UINT64(env.hvien, RISCVCPU),
96         VMSTATE_UINT64(env.hvip, RISCVCPU),
97         VMSTATE_UINT64(env.htimedelta, RISCVCPU),
98         VMSTATE_UINT64(env.vstimecmp, RISCVCPU),
100         VMSTATE_UINTTL(env.hvictl, RISCVCPU),
101         VMSTATE_UINT8_ARRAY(env.hviprio, RISCVCPU, 64),
103         VMSTATE_UINT64(env.vsstatus, RISCVCPU),
104         VMSTATE_UINTTL(env.vstvec, RISCVCPU),
105         VMSTATE_UINTTL(env.vsscratch, RISCVCPU),
106         VMSTATE_UINTTL(env.vsepc, RISCVCPU),
107         VMSTATE_UINTTL(env.vscause, RISCVCPU),
108         VMSTATE_UINTTL(env.vstval, RISCVCPU),
109         VMSTATE_UINTTL(env.vsatp, RISCVCPU),
110         VMSTATE_UINTTL(env.vsiselect, RISCVCPU),
111         VMSTATE_UINT64(env.vsie, RISCVCPU),
113         VMSTATE_UINTTL(env.mtval2, RISCVCPU),
114         VMSTATE_UINTTL(env.mtinst, RISCVCPU),
116         VMSTATE_UINTTL(env.stvec_hs, RISCVCPU),
117         VMSTATE_UINTTL(env.sscratch_hs, RISCVCPU),
118         VMSTATE_UINTTL(env.sepc_hs, RISCVCPU),
119         VMSTATE_UINTTL(env.scause_hs, RISCVCPU),
120         VMSTATE_UINTTL(env.stval_hs, RISCVCPU),
121         VMSTATE_UINTTL(env.satp_hs, RISCVCPU),
122         VMSTATE_UINT64(env.mstatus_hs, RISCVCPU),
131     CPURISCVState *env = &cpu->env;  in vector_needed()  local
133     return riscv_has_ext(env, RVV);  in vector_needed()
142         VMSTATE_UINT64_ARRAY(env.vreg, RISCVCPU, 32 * RV_VLEN_MAX / 64),
143         VMSTATE_UINTTL(env.vxrm, RISCVCPU),
144         VMSTATE_UINTTL(env.vxsat, RISCVCPU),
145         VMSTATE_UINTTL(env.vl, RISCVCPU),
146         VMSTATE_UINTTL(env.vstart, RISCVCPU),
147         VMSTATE_UINTTL(env.vtype, RISCVCPU),
148         VMSTATE_BOOL(env.vill, RISCVCPU),
156     CPURISCVState *env = &cpu->env;  in pointermasking_needed()  local
158     return riscv_has_ext(env, RVJ);  in pointermasking_needed()
167         VMSTATE_UINTTL(env.mmte, RISCVCPU),
168         VMSTATE_UINTTL(env.mpmmask, RISCVCPU),
169         VMSTATE_UINTTL(env.mpmbase, RISCVCPU),
170         VMSTATE_UINTTL(env.spmmask, RISCVCPU),
171         VMSTATE_UINTTL(env.spmbase, RISCVCPU),
172         VMSTATE_UINTTL(env.upmmask, RISCVCPU),
173         VMSTATE_UINTTL(env.upmbase, RISCVCPU),
192         VMSTATE_UINTTL_ARRAY(env.gprh, RISCVCPU, 32),
193         VMSTATE_UINT64(env.mscratchh, RISCVCPU),
194         VMSTATE_UINT64(env.sscratchh, RISCVCPU),
208     CPURISCVState *env = &cpu->env;  in cpu_kvmtimer_post_load()  local
210     env->kvm_timer_dirty = true;  in cpu_kvmtimer_post_load()
221         VMSTATE_UINT64(env.kvm_timer_time, RISCVCPU),
222         VMSTATE_UINT64(env.kvm_timer_compare, RISCVCPU),
223         VMSTATE_UINT64(env.kvm_timer_state, RISCVCPU),
239     CPURISCVState *env = &cpu->env;  in debug_post_load()  local
242         env->itrigger_enabled = riscv_itrigger_enabled(env);  in debug_post_load()
255         VMSTATE_UINTTL(env.trigger_cur, RISCVCPU),
256         VMSTATE_UINTTL_ARRAY(env.tdata1, RISCVCPU, RV_MAX_TRIGGERS),
257         VMSTATE_UINTTL_ARRAY(env.tdata2, RISCVCPU, RV_MAX_TRIGGERS),
258         VMSTATE_UINTTL_ARRAY(env.tdata3, RISCVCPU, RV_MAX_TRIGGERS),
266     CPURISCVState *env = &cpu->env;  in riscv_cpu_post_load()  local
268     env->xl = cpu_recompute_xl(env);  in riscv_cpu_post_load()
269     riscv_cpu_update_mask(env);  in riscv_cpu_post_load()
286         VMSTATE_UINT64_ARRAY(env.mstateen, RISCVCPU, 4),
287         VMSTATE_UINT64_ARRAY(env.hstateen, RISCVCPU, 4),
288         VMSTATE_UINT64_ARRAY(env.sstateen, RISCVCPU, 4),
296     CPURISCVState *env = &cpu->env;  in envcfg_needed()  local
298     return (env->priv_ver >= PRIV_VERSION_1_12_0 ? 1 : 0);  in envcfg_needed()
307         VMSTATE_UINT64(env.menvcfg, RISCVCPU),
308         VMSTATE_UINTTL(env.senvcfg, RISCVCPU),
309         VMSTATE_UINT64(env.henvcfg, RISCVCPU),
348         VMSTATE_UINTTL(env.jvt, RISCVCPU),
366         VMSTATE_BOOL(env.elp, RISCVCPU),
384         VMSTATE_UINTTL(env.ssp, RISCVCPU),
395         VMSTATE_UINTTL_ARRAY(env.gpr, RISCVCPU, 32),
396         VMSTATE_UINT64_ARRAY(env.fpr, RISCVCPU, 32),
397         VMSTATE_UINT8_ARRAY(env.miprio, RISCVCPU, 64),
398         VMSTATE_UINT8_ARRAY(env.siprio, RISCVCPU, 64),
399         VMSTATE_UINTTL(env.pc, RISCVCPU),
400         VMSTATE_UINTTL(env.load_res, RISCVCPU),
401         VMSTATE_UINTTL(env.load_val, RISCVCPU),
402         VMSTATE_UINTTL(env.frm, RISCVCPU),
403         VMSTATE_UINTTL(env.badaddr, RISCVCPU),
404         VMSTATE_UINTTL(env.guest_phys_fault_addr, RISCVCPU),
405         VMSTATE_UINTTL(env.priv_ver, RISCVCPU),
406         VMSTATE_UINTTL(env.vext_ver, RISCVCPU),
407         VMSTATE_UINT32(env.misa_mxl, RISCVCPU),
408         VMSTATE_UINT32(env.misa_ext, RISCVCPU),
410         VMSTATE_UINT32(env.misa_ext_mask, RISCVCPU),
411         VMSTATE_UINTTL(env.priv, RISCVCPU),
412         VMSTATE_BOOL(env.virt_enabled, RISCVCPU),
413         VMSTATE_UINT64(env.resetvec, RISCVCPU),
414         VMSTATE_UINTTL(env.mhartid, RISCVCPU),
415         VMSTATE_UINT64(env.mstatus, RISCVCPU),
416         VMSTATE_UINT64(env.mip, RISCVCPU),
417         VMSTATE_UINT64(env.miclaim, RISCVCPU),
418         VMSTATE_UINT64(env.mie, RISCVCPU),
419         VMSTATE_UINT64(env.mvien, RISCVCPU),
420         VMSTATE_UINT64(env.mvip, RISCVCPU),
421         VMSTATE_UINT64(env.sie, RISCVCPU),
422         VMSTATE_UINT64(env.mideleg, RISCVCPU),
423         VMSTATE_UINTTL(env.satp, RISCVCPU),
424         VMSTATE_UINTTL(env.stval, RISCVCPU),
425         VMSTATE_UINTTL(env.medeleg, RISCVCPU),
426         VMSTATE_UINTTL(env.stvec, RISCVCPU),
427         VMSTATE_UINTTL(env.sepc, RISCVCPU),
428         VMSTATE_UINTTL(env.scause, RISCVCPU),
429         VMSTATE_UINTTL(env.mtvec, RISCVCPU),
430         VMSTATE_UINTTL(env.mepc, RISCVCPU),
431         VMSTATE_UINTTL(env.mcause, RISCVCPU),
432         VMSTATE_UINTTL(env.mtval, RISCVCPU),
433         VMSTATE_UINTTL(env.miselect, RISCVCPU),
434         VMSTATE_UINTTL(env.siselect, RISCVCPU),
435         VMSTATE_UINT32(env.scounteren, RISCVCPU),
436         VMSTATE_UINT32(env.mcounteren, RISCVCPU),
437         VMSTATE_UINT32(env.mcountinhibit, RISCVCPU),
438         VMSTATE_STRUCT_ARRAY(env.pmu_ctrs, RISCVCPU, RV_MAX_MHPMCOUNTERS, 0,
440         VMSTATE_UINTTL_ARRAY(env.mhpmevent_val, RISCVCPU, RV_MAX_MHPMEVENTS),
441         VMSTATE_UINTTL_ARRAY(env.mhpmeventh_val, RISCVCPU, RV_MAX_MHPMEVENTS),
442         VMSTATE_UINTTL(env.sscratch, RISCVCPU),
443         VMSTATE_UINTTL(env.mscratch, RISCVCPU),
444         VMSTATE_UINT64(env.stimecmp, RISCVCPU),