Lines Matching full:12
56 #define MASK_OP_ARITH(op) (MASK_OP_MAJOR(op) | (op & ((0x7 << 12) | \
59 OPC_RISC_ADD = OPC_RISC_ARITH | (0x0 << 12) | (0x00 << 25),
60 OPC_RISC_SUB = OPC_RISC_ARITH | (0x0 << 12) | (0x20 << 25),
61 OPC_RISC_SLL = OPC_RISC_ARITH | (0x1 << 12) | (0x00 << 25),
62 OPC_RISC_SLT = OPC_RISC_ARITH | (0x2 << 12) | (0x00 << 25),
63 OPC_RISC_SLTU = OPC_RISC_ARITH | (0x3 << 12) | (0x00 << 25),
64 OPC_RISC_XOR = OPC_RISC_ARITH | (0x4 << 12) | (0x00 << 25),
65 OPC_RISC_SRL = OPC_RISC_ARITH | (0x5 << 12) | (0x00 << 25),
66 OPC_RISC_SRA = OPC_RISC_ARITH | (0x5 << 12) | (0x20 << 25),
67 OPC_RISC_OR = OPC_RISC_ARITH | (0x6 << 12) | (0x00 << 25),
68 OPC_RISC_AND = OPC_RISC_ARITH | (0x7 << 12) | (0x00 << 25),
71 OPC_RISC_MUL = OPC_RISC_ARITH | (0x0 << 12) | (0x01 << 25),
72 OPC_RISC_MULH = OPC_RISC_ARITH | (0x1 << 12) | (0x01 << 25),
73 OPC_RISC_MULHSU = OPC_RISC_ARITH | (0x2 << 12) | (0x01 << 25),
74 OPC_RISC_MULHU = OPC_RISC_ARITH | (0x3 << 12) | (0x01 << 25),
76 OPC_RISC_DIV = OPC_RISC_ARITH | (0x4 << 12) | (0x01 << 25),
77 OPC_RISC_DIVU = OPC_RISC_ARITH | (0x5 << 12) | (0x01 << 25),
78 OPC_RISC_REM = OPC_RISC_ARITH | (0x6 << 12) | (0x01 << 25),
79 OPC_RISC_REMU = OPC_RISC_ARITH | (0x7 << 12) | (0x01 << 25),
83 #define MASK_OP_ARITH_IMM(op) (MASK_OP_MAJOR(op) | (op & (0x7 << 12)))
85 OPC_RISC_ADDI = OPC_RISC_ARITH_IMM | (0x0 << 12),
86 OPC_RISC_SLTI = OPC_RISC_ARITH_IMM | (0x2 << 12),
87 OPC_RISC_SLTIU = OPC_RISC_ARITH_IMM | (0x3 << 12),
88 OPC_RISC_XORI = OPC_RISC_ARITH_IMM | (0x4 << 12),
89 OPC_RISC_ORI = OPC_RISC_ARITH_IMM | (0x6 << 12),
90 OPC_RISC_ANDI = OPC_RISC_ARITH_IMM | (0x7 << 12),
91 OPC_RISC_SLLI = OPC_RISC_ARITH_IMM | (0x1 << 12), /* additional part of
93 OPC_RISC_SHIFT_RIGHT_I = OPC_RISC_ARITH_IMM | (0x5 << 12) /* SRAI, SRLI */
96 #define MASK_OP_BRANCH(op) (MASK_OP_MAJOR(op) | (op & (0x7 << 12)))
98 OPC_RISC_BEQ = OPC_RISC_BRANCH | (0x0 << 12),
99 OPC_RISC_BNE = OPC_RISC_BRANCH | (0x1 << 12),
100 OPC_RISC_BLT = OPC_RISC_BRANCH | (0x4 << 12),
101 OPC_RISC_BGE = OPC_RISC_BRANCH | (0x5 << 12),
102 OPC_RISC_BLTU = OPC_RISC_BRANCH | (0x6 << 12),
103 OPC_RISC_BGEU = OPC_RISC_BRANCH | (0x7 << 12)
107 OPC_RISC_ADDIW = OPC_RISC_ARITH_IMM_W | (0x0 << 12),
108 OPC_RISC_SLLIW = OPC_RISC_ARITH_IMM_W | (0x1 << 12), /* additional part of
110 OPC_RISC_SHIFT_RIGHT_IW = OPC_RISC_ARITH_IMM_W | (0x5 << 12) /* SRAI, SRLI
115 OPC_RISC_ADDW = OPC_RISC_ARITH_W | (0x0 << 12) | (0x00 << 25),
116 OPC_RISC_SUBW = OPC_RISC_ARITH_W | (0x0 << 12) | (0x20 << 25),
117 OPC_RISC_SLLW = OPC_RISC_ARITH_W | (0x1 << 12) | (0x00 << 25),
118 OPC_RISC_SRLW = OPC_RISC_ARITH_W | (0x5 << 12) | (0x00 << 25),
119 OPC_RISC_SRAW = OPC_RISC_ARITH_W | (0x5 << 12) | (0x20 << 25),
122 OPC_RISC_MULW = OPC_RISC_ARITH_W | (0x0 << 12) | (0x01 << 25),
123 OPC_RISC_DIVW = OPC_RISC_ARITH_W | (0x4 << 12) | (0x01 << 25),
124 OPC_RISC_DIVUW = OPC_RISC_ARITH_W | (0x5 << 12) | (0x01 << 25),
125 OPC_RISC_REMW = OPC_RISC_ARITH_W | (0x6 << 12) | (0x01 << 25),
126 OPC_RISC_REMUW = OPC_RISC_ARITH_W | (0x7 << 12) | (0x01 << 25),
129 #define MASK_OP_LOAD(op) (MASK_OP_MAJOR(op) | (op & (0x7 << 12)))
131 OPC_RISC_LB = OPC_RISC_LOAD | (0x0 << 12),
132 OPC_RISC_LH = OPC_RISC_LOAD | (0x1 << 12),
133 OPC_RISC_LW = OPC_RISC_LOAD | (0x2 << 12),
134 OPC_RISC_LD = OPC_RISC_LOAD | (0x3 << 12),
135 OPC_RISC_LBU = OPC_RISC_LOAD | (0x4 << 12),
136 OPC_RISC_LHU = OPC_RISC_LOAD | (0x5 << 12),
137 OPC_RISC_LWU = OPC_RISC_LOAD | (0x6 << 12),
140 #define MASK_OP_STORE(op) (MASK_OP_MAJOR(op) | (op & (0x7 << 12)))
142 OPC_RISC_SB = OPC_RISC_STORE | (0x0 << 12),
143 OPC_RISC_SH = OPC_RISC_STORE | (0x1 << 12),
144 OPC_RISC_SW = OPC_RISC_STORE | (0x2 << 12),
145 OPC_RISC_SD = OPC_RISC_STORE | (0x3 << 12),
148 #define MASK_OP_JALR(op) (MASK_OP_MAJOR(op) | (op & (0x7 << 12)))
152 (MASK_OP_MAJOR(op) | (op & ((0x7 << 12) | (0x7F << 25))))
170 #define MASK_OP_SYSTEM(op) (MASK_OP_MAJOR(op) | (op & (0x7 << 12)))
172 OPC_RISC_ECALL = OPC_RISC_SYSTEM | (0x0 << 12),
173 OPC_RISC_EBREAK = OPC_RISC_SYSTEM | (0x0 << 12),
174 OPC_RISC_ERET = OPC_RISC_SYSTEM | (0x0 << 12),
175 OPC_RISC_MRTS = OPC_RISC_SYSTEM | (0x0 << 12),
176 OPC_RISC_MRTH = OPC_RISC_SYSTEM | (0x0 << 12),
177 OPC_RISC_HRTS = OPC_RISC_SYSTEM | (0x0 << 12),
178 OPC_RISC_WFI = OPC_RISC_SYSTEM | (0x0 << 12),
179 OPC_RISC_SFENCEVM = OPC_RISC_SYSTEM | (0x0 << 12),
181 OPC_RISC_CSRRW = OPC_RISC_SYSTEM | (0x1 << 12),
182 OPC_RISC_CSRRS = OPC_RISC_SYSTEM | (0x2 << 12),
183 OPC_RISC_CSRRC = OPC_RISC_SYSTEM | (0x3 << 12),
184 OPC_RISC_CSRRWI = OPC_RISC_SYSTEM | (0x5 << 12),
185 OPC_RISC_CSRRSI = OPC_RISC_SYSTEM | (0x6 << 12),
186 OPC_RISC_CSRRCI = OPC_RISC_SYSTEM | (0x7 << 12),
188 OPC_RISC_HLVHSV = OPC_RISC_SYSTEM | (0x4 << 12),
191 #define MASK_OP_FP_LOAD(op) (MASK_OP_MAJOR(op) | (op & (0x7 << 12)))
193 OPC_RISC_FLW = OPC_RISC_FP_LOAD | (0x2 << 12),
194 OPC_RISC_FLD = OPC_RISC_FP_LOAD | (0x3 << 12),
197 #define MASK_OP_FP_STORE(op) (MASK_OP_MAJOR(op) | (op & (0x7 << 12)))
199 OPC_RISC_FSW = OPC_RISC_FP_STORE | (0x2 << 12),
200 OPC_RISC_FSD = OPC_RISC_FP_STORE | (0x3 << 12),
305 | (sextract64(inst, 31, 1) << 12))
312 | (extract32(inst, 12, 8) << 12) \
315 #define GET_FUNCT3(inst) extract32(inst, 12, 3)
317 #define GET_RM(inst) extract32(inst, 12, 3)
322 #define GET_IMM(inst) sextract64(inst, 20, 12)
326 #define SET_I_IMM(inst, val) deposit32(inst, 20, 12, val)
332 | (sextract64(inst, 12, 1) << 5))
334 | (extract32(inst, 12, 1) << 5))
343 | (sextract64(inst, 12, 1) << 9))
345 | (extract32(inst, 12, 1) << 5) \
348 | (extract32(inst, 12, 1) << 5) \
368 | (sextract64(inst, 12, 1) << 11))
373 | (sextract64(inst, 12, 1) << 8))