riscv/insn_trans/trans_rvzacas.c.inc

2  * RISC-V translation routines for the RV64 Zacas Standard Extension.
4  * Copyright (c) 2020-2023 PLCT Lab
11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
20     if (!ctx->cfg_ptr->ext_zacas) {      \
68      * Encodings with odd numbered registers specified in rs2 and rd are
71     if ((a->rs2 | a->rd) & 1) {
75     TCGv_i64 dest = get_gpr_pair(ctx, a->rd);
76     TCGv src1 = get_address(ctx, a->rs1, 0);
77     TCGv_i64 src2 = get_gpr_pair(ctx, a->rs2);
80     tcg_gen_atomic_cmpxchg_i64(dest, src1, dest, src2, ctx->mem_idx, mop);
82     gen_set_gpr_pair(ctx, a->rd, dest);
106      * Encodings with odd numbered registers specified in rs2 and rd are
109     if ((a->rs2 | a->rd) & 1) {
115     TCGv src1 = get_address(ctx, a->rs1, 0);
117     TCGv_i64 src2l = get_gpr(ctx, a->rs2, EXT_NONE);
118     TCGv_i64 src2h = get_gpr(ctx, a->rs2 == 0 ? 0 : a->rs2 + 1, EXT_NONE);
119     TCGv_i64 destl = get_gpr(ctx, a->rd, EXT_NONE);
120     TCGv_i64 desth = get_gpr(ctx, a->rd == 0 ? 0 : a->rd + 1, EXT_NONE);
125     tcg_gen_atomic_cmpxchg_i128(dest, src1, dest, src2, ctx->mem_idx,
130     if (a->rd != 0) {
131         gen_set_gpr(ctx, a->rd, destl);
132         gen_set_gpr(ctx, a->rd + 1, desth);