riscv/insn_trans/trans_rvi.c.inc

17  * You should have received a copy of the GNU General Public License along with
21 static bool trans_illegal(DisasContext *ctx, arg_empty *a)
27 static bool trans_c64_illegal(DisasContext *ctx, arg_empty *a)
30     return trans_illegal(ctx, a);
33 static bool trans_lui(DisasContext *ctx, arg_lui *a)
35     gen_set_gpri(ctx, a->rd, a->imm);
39 static bool trans_auipc(DisasContext *ctx, arg_auipc *a)
41     TCGv target_pc = dest_gpr(ctx, a->rd);
42     gen_pc_plus_diff(target_pc, ctx, a->imm);
43     gen_set_gpr(ctx, a->rd, target_pc);
47 static bool trans_jal(DisasContext *ctx, arg_jal *a)
49     gen_jal(ctx, a->rd, a->imm);
53 static bool trans_jalr(DisasContext *ctx, arg_jalr *a)
57     TCGv succ_pc = dest_gpr(ctx, a->rd);
59     tcg_gen_addi_tl(target_pc, get_gpr(ctx, a->rs1, EXT_NONE), a->imm);
75     gen_set_gpr(ctx, a->rd, succ_pc);
161 static bool gen_branch(DisasContext *ctx, arg_b *a, TCGCond cond)
164     TCGv src1 = get_gpr(ctx, a->rs1, EXT_SIGN);
165     TCGv src2 = get_gpr(ctx, a->rs2, EXT_SIGN);
169         TCGv src1h = get_gprh(ctx, a->rs1);
170         TCGv src2h = get_gprh(ctx, a->rs2);
173         cond = gen_compare_i128(a->rs2 == 0,
185         (a->imm & 0x3)) {
188         gen_pc_plus_diff(target_pc, ctx, a->imm);
191         gen_goto_tb(ctx, 0, a->imm);
199 static bool trans_beq(DisasContext *ctx, arg_beq *a)
201     return gen_branch(ctx, a, TCG_COND_EQ);
204 static bool trans_bne(DisasContext *ctx, arg_bne *a)
206     return gen_branch(ctx, a, TCG_COND_NE);
209 static bool trans_blt(DisasContext *ctx, arg_blt *a)
211     return gen_branch(ctx, a, TCG_COND_LT);
214 static bool trans_bge(DisasContext *ctx, arg_bge *a)
216     return gen_branch(ctx, a, TCG_COND_GE);
219 static bool trans_bltu(DisasContext *ctx, arg_bltu *a)
221     return gen_branch(ctx, a, TCG_COND_LTU);
224 static bool trans_bgeu(DisasContext *ctx, arg_bgeu *a)
226     return gen_branch(ctx, a, TCG_COND_GEU);
229 static bool gen_load_tl(DisasContext *ctx, arg_lb *a, MemOp memop)
231     TCGv dest = dest_gpr(ctx, a->rd);
232     TCGv addr = get_address(ctx, a->rs1, a->imm);
235     gen_set_gpr(ctx, a->rd, dest);
240 static bool gen_load_i128(DisasContext *ctx, arg_lb *a, MemOp memop)
242     TCGv src1l = get_gpr(ctx, a->rs1, EXT_NONE);
243     TCGv destl = dest_gpr(ctx, a->rd);
244     TCGv desth = dest_gprh(ctx, a->rd);
247     tcg_gen_addi_tl(addrl, src1l, a->imm);
263     gen_set_gpr128(ctx, a->rd, destl, desth);
267 static bool gen_load(DisasContext *ctx, arg_lb *a, MemOp memop)
276         out = gen_load_i128(ctx, a, memop);
278         out = gen_load_tl(ctx, a, memop);
288 static bool trans_lb(DisasContext *ctx, arg_lb *a)
290     return gen_load(ctx, a, MO_SB);
293 static bool trans_lh(DisasContext *ctx, arg_lh *a)
295     return gen_load(ctx, a, MO_TESW);
298 static bool trans_lw(DisasContext *ctx, arg_lw *a)
300     return gen_load(ctx, a, MO_TESL);
303 static bool trans_ld(DisasContext *ctx, arg_ld *a)
306     return gen_load(ctx, a, MO_TESQ);
309 static bool trans_lq(DisasContext *ctx, arg_lq *a)
312     return gen_load(ctx, a, MO_TEUO);
315 static bool trans_lbu(DisasContext *ctx, arg_lbu *a)
317     return gen_load(ctx, a, MO_UB);
320 static bool trans_lhu(DisasContext *ctx, arg_lhu *a)
322     return gen_load(ctx, a, MO_TEUW);
325 static bool trans_lwu(DisasContext *ctx, arg_lwu *a)
328     return gen_load(ctx, a, MO_TEUL);
331 static bool trans_ldu(DisasContext *ctx, arg_ldu *a)
334     return gen_load(ctx, a, MO_TEUQ);
337 static bool gen_store_tl(DisasContext *ctx, arg_sb *a, MemOp memop)
339     TCGv addr = get_address(ctx, a->rs1, a->imm);
340     TCGv data = get_gpr(ctx, a->rs2, EXT_NONE);
350 static bool gen_store_i128(DisasContext *ctx, arg_sb *a, MemOp memop)
352     TCGv src1l = get_gpr(ctx, a->rs1, EXT_NONE);
353     TCGv src2l = get_gpr(ctx, a->rs2, EXT_NONE);
354     TCGv src2h = get_gprh(ctx, a->rs2);
357     tcg_gen_addi_tl(addrl, src1l, a->imm);
370 static bool gen_store(DisasContext *ctx, arg_sb *a, MemOp memop)
377         return gen_store_i128(ctx, a, memop);
379         return gen_store_tl(ctx, a, memop);
383 static bool trans_sb(DisasContext *ctx, arg_sb *a)
385     return gen_store(ctx, a, MO_SB);
388 static bool trans_sh(DisasContext *ctx, arg_sh *a)
390     return gen_store(ctx, a, MO_TESW);
393 static bool trans_sw(DisasContext *ctx, arg_sw *a)
395     return gen_store(ctx, a, MO_TESL);
398 static bool trans_sd(DisasContext *ctx, arg_sd *a)
401     return gen_store(ctx, a, MO_TEUQ);
404 static bool trans_sq(DisasContext *ctx, arg_sq *a)
407     return gen_store(ctx, a, MO_TEUO);
410 static bool trans_addd(DisasContext *ctx, arg_addd *a)
414     return gen_arith(ctx, a, EXT_NONE, tcg_gen_add_tl, NULL);
417 static bool trans_addid(DisasContext *ctx, arg_addid *a)
421     return gen_arith_imm_fn(ctx, a, EXT_NONE, tcg_gen_addi_tl, NULL);
424 static bool trans_subd(DisasContext *ctx, arg_subd *a)
428     return gen_arith(ctx, a, EXT_NONE, tcg_gen_sub_tl, NULL);
439 static bool trans_addi(DisasContext *ctx, arg_addi *a)
441     return gen_arith_imm_fn(ctx, a, EXT_NONE, tcg_gen_addi_tl, gen_addi2_i128);
466 static bool trans_slti(DisasContext *ctx, arg_slti *a)
468     return gen_arith_imm_tl(ctx, a, EXT_SIGN, gen_slt, gen_slt_i128);
471 static bool trans_sltiu(DisasContext *ctx, arg_sltiu *a)
473     return gen_arith_imm_tl(ctx, a, EXT_SIGN, gen_sltu, gen_sltu_i128);
476 static bool trans_xori(DisasContext *ctx, arg_xori *a)
478     return gen_logic_imm_fn(ctx, a, tcg_gen_xori_tl);
481 static bool trans_ori(DisasContext *ctx, arg_ori *a)
483     return gen_logic_imm_fn(ctx, a, tcg_gen_ori_tl);
486 static bool trans_andi(DisasContext *ctx, arg_andi *a)
488     return gen_logic_imm_fn(ctx, a, tcg_gen_andi_tl);
504 static bool trans_slli(DisasContext *ctx, arg_slli *a)
506     return gen_shift_imm_fn(ctx, a, EXT_NONE, tcg_gen_shli_tl, gen_slli_i128);
527 static bool trans_srli(DisasContext *ctx, arg_srli *a)
529     return gen_shift_imm_fn_per_ol(ctx, a, EXT_NONE,
551 static bool trans_srai(DisasContext *ctx, arg_srai *a)
553     return gen_shift_imm_fn_per_ol(ctx, a, EXT_NONE,
557 static bool trans_add(DisasContext *ctx, arg_add *a)
559     return gen_arith(ctx, a, EXT_NONE, tcg_gen_add_tl, tcg_gen_add2_tl);
562 static bool trans_sub(DisasContext *ctx, arg_sub *a)
564     return gen_arith(ctx, a, EXT_NONE, tcg_gen_sub_tl, tcg_gen_sub2_tl);
594 static bool trans_sll(DisasContext *ctx, arg_sll *a)
596     return gen_shift(ctx, a, EXT_NONE, tcg_gen_shl_tl, gen_sll_i128);
599 static bool trans_slt(DisasContext *ctx, arg_slt *a)
601     return gen_arith(ctx, a, EXT_SIGN, gen_slt, gen_slt_i128);
604 static bool trans_sltu(DisasContext *ctx, arg_sltu *a)
606     return gen_arith(ctx, a, EXT_SIGN, gen_sltu, gen_sltu_i128);
636 static bool trans_srl(DisasContext *ctx, arg_srl *a)
638     return gen_shift(ctx, a, EXT_ZERO, tcg_gen_shr_tl, gen_srl_i128);
669 static bool trans_sra(DisasContext *ctx, arg_sra *a)
671     return gen_shift(ctx, a, EXT_SIGN, tcg_gen_sar_tl, gen_sra_i128);
674 static bool trans_xor(DisasContext *ctx, arg_xor *a)
676     return gen_logic(ctx, a, tcg_gen_xor_tl);
679 static bool trans_or(DisasContext *ctx, arg_or *a)
681     return gen_logic(ctx, a, tcg_gen_or_tl);
684 static bool trans_and(DisasContext *ctx, arg_and *a)
686     return gen_logic(ctx, a, tcg_gen_and_tl);
689 static bool trans_addiw(DisasContext *ctx, arg_addiw *a)
693     return gen_arith_imm_fn(ctx, a, EXT_NONE, tcg_gen_addi_tl, NULL);
696 static bool trans_slliw(DisasContext *ctx, arg_slliw *a)
700     return gen_shift_imm_fn(ctx, a, EXT_NONE, tcg_gen_shli_tl, NULL);
703 static bool trans_srliw(DisasContext *ctx, arg_srliw *a)
707     return gen_shift_imm_fn(ctx, a, EXT_NONE, gen_srliw, NULL);
710 static bool trans_sraiw(DisasContext *ctx, arg_sraiw *a)
714     return gen_shift_imm_fn(ctx, a, EXT_NONE, gen_sraiw, NULL);
717 static bool trans_sllid(DisasContext *ctx, arg_sllid *a)
721     return gen_shift_imm_fn(ctx, a, EXT_NONE, tcg_gen_shli_tl, NULL);
724 static bool trans_srlid(DisasContext *ctx, arg_srlid *a)
728     return gen_shift_imm_fn(ctx, a, EXT_NONE, tcg_gen_shri_tl, NULL);
731 static bool trans_sraid(DisasContext *ctx, arg_sraid *a)
735     return gen_shift_imm_fn(ctx, a, EXT_NONE, tcg_gen_sari_tl,  NULL);
738 static bool trans_addw(DisasContext *ctx, arg_addw *a)
742     return gen_arith(ctx, a, EXT_NONE, tcg_gen_add_tl, NULL);
745 static bool trans_subw(DisasContext *ctx, arg_subw *a)
749     return gen_arith(ctx, a, EXT_NONE, tcg_gen_sub_tl, NULL);
752 static bool trans_sllw(DisasContext *ctx, arg_sllw *a)
756     return gen_shift(ctx, a, EXT_NONE, tcg_gen_shl_tl, NULL);
759 static bool trans_srlw(DisasContext *ctx, arg_srlw *a)
763     return gen_shift(ctx, a, EXT_ZERO, tcg_gen_shr_tl, NULL);
766 static bool trans_sraw(DisasContext *ctx, arg_sraw *a)
770     return gen_shift(ctx, a, EXT_SIGN, tcg_gen_sar_tl, NULL);
773 static bool trans_slld(DisasContext *ctx, arg_slld *a)
777     return gen_shift(ctx, a, EXT_NONE, tcg_gen_shl_tl, NULL);
780 static bool trans_srld(DisasContext *ctx, arg_srld *a)
784     return gen_shift(ctx, a, EXT_ZERO, tcg_gen_shr_tl, NULL);
787 static bool trans_srad(DisasContext *ctx, arg_srad *a)
791     return gen_shift(ctx, a, EXT_SIGN, tcg_gen_sar_tl, NULL);
794 static bool trans_pause(DisasContext *ctx, arg_pause *a)
801      * PAUSE is a no-op in QEMU,
811 static bool trans_fence(DisasContext *ctx, arg_fence *a)
813     /* FENCE is a full memory barrier. */
818 static bool trans_fence_i(DisasContext *ctx, arg_fence_i *a)
825      * FENCE_I is a no-op in QEMU,
912 static bool trans_csrrw(DisasContext *ctx, arg_csrrw *a)
916         TCGv src = get_gpr(ctx, a->rs1, EXT_NONE);
920          * side effects that might occur on a csr read.
922         if (a->rd == 0) {
923             return do_csrw(ctx, a->csr, src);
928         return do_csrrw(ctx, a->rd, a->csr, src, mask);
930         TCGv srcl = get_gpr(ctx, a->rs1, EXT_NONE);
931         TCGv srch = get_gprh(ctx, a->rs1);
935          * side effects that might occur on a csr read.
937         if (a->rd == 0) {
938             return do_csrw_i128(ctx, a->csr, srcl, srch);
942         return do_csrrw_i128(ctx, a->rd, a->csr, srcl, srch, mask, mask);
946 static bool trans_csrrs(DisasContext *ctx, arg_csrrs *a)
950      * cause any of the side effects that might occur on a csr write.
951      * Note that if rs1 specifies a register other than x0, holding
952      * a zero value, the instruction will still attempt to write the
956         if (a->rs1 == 0) {
957             return do_csrr(ctx, a->rd, a->csr);
961         TCGv mask = get_gpr(ctx, a->rs1, EXT_ZERO);
962         return do_csrrw(ctx, a->rd, a->csr, ones, mask);
964         if (a->rs1 == 0) {
965             return do_csrr_i128(ctx, a->rd, a->csr);
969         TCGv maskl = get_gpr(ctx, a->rs1, EXT_ZERO);
970         TCGv maskh = get_gprh(ctx, a->rs1);
971         return do_csrrw_i128(ctx, a->rd, a->csr, ones, ones, maskl, maskh);
975 static bool trans_csrrc(DisasContext *ctx, arg_csrrc *a)
979      * cause any of the side effects that might occur on a csr write.
980      * Note that if rs1 specifies a register other than x0, holding
981      * a zero value, the instruction will still attempt to write the
985         if (a->rs1 == 0) {
986             return do_csrr(ctx, a->rd, a->csr);
989         TCGv mask = get_gpr(ctx, a->rs1, EXT_ZERO);
990         return do_csrrw(ctx, a->rd, a->csr, ctx->zero, mask);
992         if (a->rs1 == 0) {
993             return do_csrr_i128(ctx, a->rd, a->csr);
996         TCGv maskl = get_gpr(ctx, a->rs1, EXT_ZERO);
997         TCGv maskh = get_gprh(ctx, a->rs1);
998         return do_csrrw_i128(ctx, a->rd, a->csr,
1003 static bool trans_csrrwi(DisasContext *ctx, arg_csrrwi *a)
1007         TCGv src = tcg_constant_tl(a->rs1);
1011          * side effects that might occur on a csr read.
1013         if (a->rd == 0) {
1014             return do_csrw(ctx, a->csr, src);
1019         return do_csrrw(ctx, a->rd, a->csr, src, mask);
1021         TCGv src = tcg_constant_tl(a->rs1);
1025          * side effects that might occur on a csr read.
1027         if (a->rd == 0) {
1028             return do_csrw_i128(ctx, a->csr, src, ctx->zero);
1032         return do_csrrw_i128(ctx, a->rd, a->csr, src, ctx->zero, mask, mask);
1036 static bool trans_csrrsi(DisasContext *ctx, arg_csrrsi *a)
1040      * cause any of the side effects that might occur on a csr write.
1041      * Note that if rs1 specifies a register other than x0, holding
1042      * a zero value, the instruction will still attempt to write the
1046         if (a->rs1 == 0) {
1047             return do_csrr(ctx, a->rd, a->csr);
1051         TCGv mask = tcg_constant_tl(a->rs1);
1052         return do_csrrw(ctx, a->rd, a->csr, ones, mask);
1054         if (a->rs1 == 0) {
1055             return do_csrr_i128(ctx, a->rd, a->csr);
1059         TCGv mask = tcg_constant_tl(a->rs1);
1060         return do_csrrw_i128(ctx, a->rd, a->csr, ones, ones, mask, ctx->zero);
1064 static bool trans_csrrci(DisasContext *ctx, arg_csrrci * a)
1068      * cause any of the side effects that might occur on a csr write.
1069      * Note that if rs1 specifies a register other than x0, holding
1070      * a zero value, the instruction will still attempt to write the
1074         if (a->rs1 == 0) {
1075             return do_csrr(ctx, a->rd, a->csr);
1078         TCGv mask = tcg_constant_tl(a->rs1);
1079         return do_csrrw(ctx, a->rd, a->csr, ctx->zero, mask);
1081         if (a->rs1 == 0) {
1082             return do_csrr_i128(ctx, a->rd, a->csr);
1085         TCGv mask = tcg_constant_tl(a->rs1);
1086         return do_csrrw_i128(ctx, a->rd, a->csr,