riscv/insn_trans/trans_rvi.c.inc

982     TCGv_i32 csr = tcg_constant_i32(rc);
985     gen_helper_csrr(dest, tcg_env, csr);
992     TCGv_i32 csr = tcg_constant_i32(rc);
995     gen_helper_csrw(tcg_env, csr, src);
1002     TCGv_i32 csr = tcg_constant_i32(rc);
1005     gen_helper_csrrw(dest, tcg_env, csr, src, mask);
1014     TCGv_i32 csr = tcg_constant_i32(rc);
1017     gen_helper_csrr_i128(destl, tcg_env, csr);
1025     TCGv_i32 csr = tcg_constant_i32(rc);
1028     gen_helper_csrw_i128(tcg_env, csr, srcl, srch);
1037     TCGv_i32 csr = tcg_constant_i32(rc);
1040     gen_helper_csrrw_i128(destl, tcg_env, csr, srcl, srch, maskl, maskh);
1053          * If rd == 0, the insn shall not read the csr, nor cause any of the
1054          * side effects that might occur on a csr read.
1057             return do_csrw(ctx, a->csr, src);
1062         return do_csrrw(ctx, a->rd, a->csr, src, mask);
1068          * If rd == 0, the insn shall not read the csr, nor cause any of the
1069          * side effects that might occur on a csr read.
1072             return do_csrw_i128(ctx, a->csr, srcl, srch);
1076         return do_csrrw_i128(ctx, a->rd, a->csr, srcl, srch, mask, mask);
1083      * If rs1 == 0, the insn shall not write to the csr at all, nor
1084      * cause any of the side effects that might occur on a csr write.
1087      * unmodified value back to the csr and will cause side effects.
1091             return do_csrr(ctx, a->rd, a->csr);
1096         return do_csrrw(ctx, a->rd, a->csr, ones, mask);
1099             return do_csrr_i128(ctx, a->rd, a->csr);
1105         return do_csrrw_i128(ctx, a->rd, a->csr, ones, ones, maskl, maskh);
1112      * If rs1 == 0, the insn shall not write to the csr at all, nor
1113      * cause any of the side effects that might occur on a csr write.
1116      * unmodified value back to the csr and will cause side effects.
1120             return do_csrr(ctx, a->rd, a->csr);
1124         return do_csrrw(ctx, a->rd, a->csr, ctx->zero, mask);
1127             return do_csrr_i128(ctx, a->rd, a->csr);
1132         return do_csrrw_i128(ctx, a->rd, a->csr,
1144          * If rd == 0, the insn shall not read the csr, nor cause any of the
1145          * side effects that might occur on a csr read.
1148             return do_csrw(ctx, a->csr, src);
1153         return do_csrrw(ctx, a->rd, a->csr, src, mask);
1158          * If rd == 0, the insn shall not read the csr, nor cause any of the
1159          * side effects that might occur on a csr read.
1162             return do_csrw_i128(ctx, a->csr, src, ctx->zero);
1166         return do_csrrw_i128(ctx, a->rd, a->csr, src, ctx->zero, mask, mask);
1173      * If rs1 == 0, the insn shall not write to the csr at all, nor
1174      * cause any of the side effects that might occur on a csr write.
1177      * unmodified value back to the csr and will cause side effects.
1181             return do_csrr(ctx, a->rd, a->csr);
1186         return do_csrrw(ctx, a->rd, a->csr, ones, mask);
1189             return do_csrr_i128(ctx, a->rd, a->csr);
1194         return do_csrrw_i128(ctx, a->rd, a->csr, ones, ones, mask, ctx->zero);
1201      * If rs1 == 0, the insn shall not write to the csr at all, nor
1202      * cause any of the side effects that might occur on a csr write.
1205      * unmodified value back to the csr and will cause side effects.
1209             return do_csrr(ctx, a->rd, a->csr);
1213         return do_csrrw(ctx, a->rd, a->csr, ctx->zero, mask);
1216             return do_csrr_i128(ctx, a->rd, a->csr);
1220         return do_csrrw_i128(ctx, a->rd, a->csr,