target/riscv/csr.c

1249     uint64_t cfg_val = 0;
1252         cfg_val = upper_half ? ((uint64_t)env->mcyclecfgh << 32) :
1255         cfg_val = upper_half ? ((uint64_t)env->minstretcfgh << 32) :
1258         cfg_val = upper_half ?
1261         cfg_val &= MHPMEVENT_FILTER_MASK;
1264     if (!cfg_val) {
1277     if (!(cfg_val & MCYCLECFG_BIT_MINH)) {
1281     if (!(cfg_val & MCYCLECFG_BIT_SINH)) {
1285     if (!(cfg_val & MCYCLECFG_BIT_UINH)) {
1289     if (!(cfg_val & MCYCLECFG_BIT_VSINH)) {
1293     if (!(cfg_val & MCYCLECFG_BIT_VUINH)) {