42     bool virt = env->virt_enabled;  in riscv_env_mmu_index()
117     if (env->virt_enabled) {  in cpu_get_tb_cpu_state()
438     if (env->virt_enabled) {  in riscv_cpu_local_irq_pending()
516         if (env->virt_enabled && !(env->mstatus_hs & MSTATUS_FS)) {  in riscv_cpu_fp_enabled()
529         if (env->virt_enabled && !(env->mstatus_hs & MSTATUS_VS)) {  in riscv_cpu_vector_enabled()
547     bool current_virt = env->virt_enabled;  in riscv_cpu_swap_hypervisor_regs()
640     if (env->virt_enabled) {  in riscv_cpu_interrupt()
698     if (newpriv != env->priv || env->virt_enabled != virt_en) {  in riscv_cpu_set_mode()
723         if (env->virt_enabled != virt_en) {  in riscv_cpu_set_mode()
727         env->virt_enabled = virt_en;  in riscv_cpu_set_mode()
829     if (!env->virt_enabled && two_stage) {  in get_physical_address()
918     if (first_stage && two_stage && env->virt_enabled) {  in get_physical_address()
1050         if (first_stage || !env->virt_enabled) {  in get_physical_address()
1055         if (first_stage && two_stage && !env->virt_enabled) {  in get_physical_address()
1063         if (env->virt_enabled) {  in get_physical_address()
1185         } else if (env->virt_enabled && !first_stage) {  in raise_mmu_exception()
1226                              true, env->virt_enabled, true)) {  in riscv_cpu_get_phys_page_debug()
1230     if (env->virt_enabled) {  in riscv_cpu_get_phys_page_debug()
1654     bool virt = env->virt_enabled;  in riscv_cpu_do_interrupt()
1739             } else if (env->priv == PRV_S && env->virt_enabled) {  in riscv_cpu_do_interrupt()
1741             } else if (env->priv == PRV_S && !env->virt_enabled) {  in riscv_cpu_do_interrupt()
1764             if (env->virt_enabled &&  in riscv_cpu_do_interrupt()
1776             } else if (env->virt_enabled) {  in riscv_cpu_do_interrupt()
1810             if (env->virt_enabled) {  in riscv_cpu_do_interrupt()
1814                                      env->virt_enabled);  in riscv_cpu_do_interrupt()
1815             if (env->virt_enabled && tval) {  in riscv_cpu_do_interrupt()