Lines Matching +full:irqs +full:- +full:reserved
2 * RISC-V CPU helpers for qemu.
4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
5 * Copyright (c) 2017-2018 SiFive, Inc.
22 #include "qemu/main-loop.h"
26 #include "exec/exec-all.h"
27 #include "exec/page-protection.h"
29 #include "tcg/tcg-op.h"
30 #include "hw/core/tcg-cpu-ops.h"
32 #include "semihosting/common-semi.h"
33 #include "sysemu/cpu-timers.h"
36 #include "tcg/oversized-guest.h"
44 bool virt = env->virt_enabled;
45 int mode = env->priv;
47 /* All priv -> mmu_idx mapping are here */
49 uint64_t status = env->mstatus;
52 mode = get_field(env->mstatus, MSTATUS_MPP);
53 virt = get_field(env->mstatus, MSTATUS_MPV) &&
56 status = env->vsstatus;
71 if (!env_archcpu(env)->cfg.ext_zicfilp) {
75 switch (env->priv) {
78 return env->senvcfg & SENVCFG_LPE;
80 return env->menvcfg & MENVCFG_LPE;
83 if (env->virt_enabled) {
84 return env->henvcfg & HENVCFG_LPE;
86 return env->menvcfg & MENVCFG_LPE;
88 return env->mseccfg & MSECCFG_MLPE;
98 if (!env_archcpu(env)->cfg.ext_zicfiss) {
102 switch (env->priv) {
109 return env->senvcfg & SENVCFG_SSE;
112 if (env->virt_enabled) {
113 return env->henvcfg & HENVCFG_SSE;
115 return env->menvcfg & MENVCFG_SSE;
116 case PRV_M: /* M-mode shadow stack is always off */
131 *pc = env->xl == MXL_RV32 ? env->pc & UINT32_MAX : env->pc;
134 if (cpu->cfg.ext_zve32x) {
136 * If env->vl equals to VLMAX, we can use generic vector operation
145 int8_t lmul = sextract32(FIELD_EX64(env->vtype, VTYPE, VLMUL), 0, 3);
146 uint32_t vsew = FIELD_EX64(env->vtype, VTYPE, VSEW);
147 uint32_t vlmax = vext_get_vlmax(cpu->cfg.vlenb, vsew, lmul);
149 bool vl_eq_vlmax = (env->vstart == 0) && (vlmax == env->vl) &&
151 flags = FIELD_DP32(flags, TB_FLAGS, VILL, env->vill);
154 FIELD_EX64(env->vtype, VTYPE, VLMUL));
157 FIELD_EX64(env->vtype, VTYPE, VTA));
159 FIELD_EX64(env->vtype, VTYPE, VMA));
160 flags = FIELD_DP32(flags, TB_FLAGS, VSTART_EQ_ZERO, env->vstart == 0);
168 * the start of the block is tracked via env->elp. env->elp
171 flags = FIELD_DP32(flags, TB_FLAGS, FCFI_LP_EXPECTED, env->elp);
183 flags = FIELD_DP32(flags, TB_FLAGS, PRIV, env->priv);
186 fs = get_field(env->mstatus, MSTATUS_FS);
187 vs = get_field(env->mstatus, MSTATUS_VS);
189 if (env->virt_enabled) {
195 fs = MIN(fs, get_field(env->mstatus_hs, MSTATUS_FS));
196 vs = MIN(vs, get_field(env->mstatus_hs, MSTATUS_VS));
205 if (cpu->cfg.debug && !icount_enabled()) {
206 flags = FIELD_DP32(flags, TB_FLAGS, ITRIGGER, env->itrigger_enabled);
212 flags = FIELD_DP32(flags, TB_FLAGS, XL, env->xl);
214 if (env->cur_pmmask != 0) {
217 if (env->cur_pmbase != 0) {
227 RISCVMXL xl = env->xl;
238 if (env->mmte & M_PM_ENABLE) {
239 mask = env->mpmmask;
240 base = env->mpmbase;
244 if (env->mmte & S_PM_ENABLE) {
245 mask = env->spmmask;
246 base = env->spmbase;
250 if (env->mmte & U_PM_ENABLE) {
251 mask = env->upmmask;
252 base = env->upmbase;
261 env->cur_pmmask = mask & UINT32_MAX;
262 env->cur_pmbase = base & UINT32_MAX;
264 env->cur_pmmask = mask;
265 env->cur_pmbase = base;
272 * The HS-mode is allowed to configure priority only for the
273 * following VS-mode local interrupts:
275 * 0 (Reserved interrupt, reads as zero)
277 * 4 (Reserved interrupt, reads as zero)
279 * 8 (Reserved interrupt, reads as zero)
280 * 13 (Reserved interrupt)
301 return -EINVAL;
317 * RISC-V Advanced Interrupt Architecture specification.
319 * ----------------------------------------------------------------
322 * ----------------------------------------------------------------
333 * ----------------------------------------------------------------
428 if (!((extirq == IRQ_M_EXT) ? riscv_cpu_cfg(env)->ext_smaia :
429 riscv_cpu_cfg(env)->ext_ssaia)) {
456 * Doesn't report interrupts inserted using mvip from M-mode firmware or
457 * using hvip bits 13:63 from HS-mode. Those are returned in
462 uint32_t gein = get_field(env->hstatus, HSTATUS_VGEIN);
463 uint64_t vsgein = (env->hgeip & (1ULL << gein)) ? MIP_VSEIP : 0;
464 uint64_t vstip = (env->vstime_irq) ? MIP_VSTIP : 0;
466 return (env->mip | vsgein | vstip) & env->mie;
471 uint64_t irqs = riscv_cpu_all_pending(env) & ~env->mideleg &
475 irqs, env->miprio);
480 uint64_t irqs = riscv_cpu_all_pending(env) & env->mideleg &
482 uint64_t irqs_f = env->mvip & env->mvien & ~env->mideleg & env->sie;
485 irqs | irqs_f, env->siprio);
490 uint64_t irqs = riscv_cpu_all_pending(env) & env->mideleg & env->hideleg;
491 uint64_t irqs_f_vs = env->hvip & env->hvien & ~env->hideleg & env->vsie;
494 /* Bring VS-level bits to correct position */
495 vsbits = irqs & VS_MODE_INTERRUPTS;
496 irqs &= ~VS_MODE_INTERRUPTS;
497 irqs |= vsbits >> 1;
500 (irqs | irqs_f_vs), env->hviprio);
505 uint64_t irqs, pending, mie, hsie, vsie, irqs_f, irqs_f_vs;
510 if (env->virt_enabled) {
513 vsie = (env->priv < PRV_S) ||
514 (env->priv == PRV_S && get_field(env->mstatus, MSTATUS_SIE));
516 mie = (env->priv < PRV_M) ||
517 (env->priv == PRV_M && get_field(env->mstatus, MSTATUS_MIE));
518 hsie = (env->priv < PRV_S) ||
519 (env->priv == PRV_S && get_field(env->mstatus, MSTATUS_SIE));
526 /* Check M-mode interrupts */
527 irqs = pending & ~env->mideleg & -mie;
528 if (irqs) {
530 irqs, env->miprio);
533 /* Check for virtual S-mode interrupts. */
534 irqs_f = env->mvip & (env->mvien & ~env->mideleg) & env->sie;
536 /* Check HS-mode interrupts */
537 irqs = ((pending & env->mideleg & ~env->hideleg) | irqs_f) & -hsie;
538 if (irqs) {
540 irqs, env->siprio);
543 /* Check for virtual VS-mode interrupts. */
544 irqs_f_vs = env->hvip & env->hvien & ~env->hideleg & env->vsie;
546 /* Check VS-mode interrupts */
547 irq_delegated = pending & env->mideleg & env->hideleg;
549 /* Bring VS-level bits to correct position */
554 irqs = (irq_delegated | irqs_f_vs) & -vsie;
555 if (irqs) {
557 irqs, env->hviprio);
573 CPURISCVState *env = &cpu->env;
576 cs->exception_index = RISCV_EXCP_INT_FLAG | interruptno;
587 if (env->mstatus & MSTATUS_FS) {
588 if (env->virt_enabled && !(env->mstatus_hs & MSTATUS_FS)) {
600 if (env->mstatus & MSTATUS_VS) {
601 if (env->virt_enabled && !(env->mstatus_hs & MSTATUS_VS)) {
619 bool current_virt = env->virt_enabled;
625 if (env_archcpu(env)->cfg.ext_zicfilp &&
626 get_field(env->henvcfg, HENVCFG_LPE)) {
634 env->vsstatus = env->mstatus & mstatus_mask;
635 env->mstatus &= ~mstatus_mask;
636 env->mstatus |= env->mstatus_hs;
638 env->vstvec = env->stvec;
639 env->stvec = env->stvec_hs;
641 env->vsscratch = env->sscratch;
642 env->sscratch = env->sscratch_hs;
644 env->vsepc = env->sepc;
645 env->sepc = env->sepc_hs;
647 env->vscause = env->scause;
648 env->scause = env->scause_hs;
650 env->vstval = env->stval;
651 env->stval = env->stval_hs;
653 env->vsatp = env->satp;
654 env->satp = env->satp_hs;
657 env->mstatus_hs = env->mstatus & mstatus_mask;
658 env->mstatus &= ~mstatus_mask;
659 env->mstatus |= env->vsstatus;
661 env->stvec_hs = env->stvec;
662 env->stvec = env->vstvec;
664 env->sscratch_hs = env->sscratch;
665 env->sscratch = env->vsscratch;
667 env->sepc_hs = env->sepc;
668 env->sepc = env->vsepc;
670 env->scause_hs = env->scause;
671 env->scause = env->vscause;
673 env->stval_hs = env->stval;
674 env->stval = env->vstval;
676 env->satp_hs = env->satp;
677 env->satp = env->vsatp;
687 return env->geilen;
696 if (geilen > (TARGET_LONG_BITS - 1)) {
700 env->geilen = geilen;
705 CPURISCVState *env = &cpu->env;
706 if (env->miclaim & interrupts) {
707 return -1;
709 env->miclaim |= interrupts;
721 if (env->virt_enabled) {
722 gein = get_field(env->hstatus, HSTATUS_VGEIN);
723 vsgein = (env->hgeip & (1ULL << gein)) ? MIP_VSEIP : 0;
724 irqf = env->hvien & env->hvip & env->vsie;
726 irqf = env->mvien & env->mvip & env->sie;
729 vstip = env->vstime_irq ? MIP_VSTIP : 0;
731 if (env->mip | vsgein | vstip | irqf) {
740 uint64_t old = env->mip;
743 mask = ((mask == MIP_VSTIP) && env->vstime_irq) ? 0 : mask;
747 env->mip = (env->mip & ~mask) | (value & mask);
757 env->rdtime_fn = fn;
758 env->rdtime_fn_arg = arg;
770 env->aia_ireg_rmw_fn[priv] = rmw_fn;
771 env->aia_ireg_rmw_fn_arg[priv] = rmw_fn_arg;
779 if (newpriv != env->priv || env->virt_enabled != virt_en) {
788 env->priv = newpriv;
789 env->xl = cpu_recompute_xl(env);
793 * Clear the load reservation - otherwise a reservation placed in one
800 env->load_res = -1;
804 if (env->virt_enabled != virt_en) {
808 env->virt_enabled = virt_en;
826 * get_physical_address_pmp - check PMP permission for this physical address
844 if (!riscv_cpu_cfg(env)->pmp) {
862 * get_physical_address - get the physical address for this virtual address
891 * NOTE: the env->pc value visible here will not be
912 if (!env->virt_enabled && two_stage) {
916 if (mode == PRV_M || !riscv_cpu_cfg(env)->mmu) {
930 base = (hwaddr)get_field(env->vsatp, SATP32_PPN) << PGSHIFT;
931 vm = get_field(env->vsatp, SATP32_MODE);
933 base = (hwaddr)get_field(env->vsatp, SATP64_PPN) << PGSHIFT;
934 vm = get_field(env->vsatp, SATP64_MODE);
938 base = (hwaddr)get_field(env->satp, SATP32_PPN) << PGSHIFT;
939 vm = get_field(env->satp, SATP32_MODE);
941 base = (hwaddr)get_field(env->satp, SATP64_PPN) << PGSHIFT;
942 vm = get_field(env->satp, SATP64_MODE);
948 base = (hwaddr)get_field(env->hgatp, SATP32_PPN) << PGSHIFT;
949 vm = get_field(env->hgatp, SATP32_MODE);
951 base = (hwaddr)get_field(env->hgatp, SATP64_PPN) << PGSHIFT;
952 vm = get_field(env->hgatp, SATP64_MODE);
982 if (sxlen > (va_bits - 1)) {
983 mask = (1L << (sxlen - (va_bits - 1))) - 1;
987 masked_msbs = (addr >> (va_bits - 1)) & mask;
998 bool pbmte = env->menvcfg & MENVCFG_PBMTE;
999 bool svade = riscv_cpu_cfg(env)->ext_svade;
1000 bool svadu = riscv_cpu_cfg(env)->ext_svadu;
1001 bool adue = svadu ? env->menvcfg & MENVCFG_ADUE : !svade;
1003 if (first_stage && two_stage && env->virt_enabled) {
1004 pbmte = pbmte && (env->henvcfg & HENVCFG_PBMTE);
1005 adue = adue && (env->henvcfg & HENVCFG_ADUE);
1008 int ptshift = (levels - 1) * ptidxbits;
1016 for (i = 0; i < levels; i++, ptshift -= ptidxbits) {
1020 ((1 << (ptidxbits + widened)) - 1);
1023 ((1 << ptidxbits) - 1);
1059 pte = address_space_ldl(cs->as, pte_addr, attrs, &res);
1061 pte = address_space_ldq(cs->as, pte_addr, attrs, &res);
1079 if (!riscv_cpu_cfg(env)->ext_svnapot && (pte & PTE_N)) {
1105 if (ppn & ((1ULL << ptshift) - 1)) {
1110 /* Reserved without Svpbmt. */
1115 /* Check for reserved combinations of RWX flags. */
1120 /* if bcfi enabled, PTE_W is not reserved and shadow stack page */
1157 if (first_stage || !env->virt_enabled) {
1158 mxr = get_field(env->mstatus, MSTATUS_MXR);
1162 if (first_stage && two_stage && !env->virt_enabled) {
1163 mxr |= get_field(env->vsstatus, MSTATUS_MXR);
1167 * Setting MXR at HS-level overrides both VS-stage and G-stage
1168 * execute-only permissions
1170 if (env->virt_enabled) {
1171 mxr |= get_field(env->mstatus_hs, MSTATUS_MXR);
1221 * - if accessed or dirty bits need updating, and the PTE is
1223 * - if the PTE is in IO space or ROM, then it can't be updated
1225 * - if the PTE changed by the time we went to update it, then
1226 * it is no longer valid and we must re-walk the page table.
1230 mr = address_space_translate(cs->as, pte_addr, &addr1, &l,
1233 target_ulong *pte_pa = qemu_map_ram_ptr(mr->ram_block, addr1);
1264 if (riscv_cpu_cfg(env)->ext_svnapot && (pte & PTE_N)) {
1266 if ((i != (levels - 1)) || (napot_bits != 4)) {
1271 napot_mask = (1 << napot_bits) - 1;
1273 (vpn & (((target_ulong)1 << ptshift) - 1))
1299 cs->exception_index = RISCV_EXCP_INST_ACCESS_FAULT;
1300 } else if (env->virt_enabled && !first_stage) {
1301 cs->exception_index = RISCV_EXCP_INST_GUEST_PAGE_FAULT;
1303 cs->exception_index = RISCV_EXCP_INST_PAGE_FAULT;
1308 cs->exception_index = RISCV_EXCP_LOAD_ACCESS_FAULT;
1310 cs->exception_index = RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT;
1312 cs->exception_index = RISCV_EXCP_LOAD_PAGE_FAULT;
1317 cs->exception_index = RISCV_EXCP_STORE_AMO_ACCESS_FAULT;
1319 cs->exception_index = RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT;
1321 cs->exception_index = RISCV_EXCP_STORE_PAGE_FAULT;
1327 env->badaddr = address;
1328 env->two_stage_lookup = two_stage;
1329 env->two_stage_indirect_lookup = two_stage_indirect;
1335 CPURISCVState *env = &cpu->env;
1338 int mmu_idx = riscv_env_mmu_index(&cpu->env, false);
1341 true, env->virt_enabled, true, false)) {
1342 return -1;
1345 if (env->virt_enabled) {
1348 return -1;
1362 CPURISCVState *env = &cpu->env;
1365 cs->exception_index = RISCV_EXCP_STORE_AMO_ACCESS_FAULT;
1367 cs->exception_index = RISCV_EXCP_LOAD_ACCESS_FAULT;
1369 cs->exception_index = RISCV_EXCP_INST_ACCESS_FAULT;
1372 env->badaddr = addr;
1373 env->two_stage_lookup = mmuidx_2stage(mmu_idx);
1374 env->two_stage_indirect_lookup = false;
1383 CPURISCVState *env = &cpu->env;
1386 cs->exception_index = RISCV_EXCP_INST_ADDR_MIS;
1389 cs->exception_index = RISCV_EXCP_LOAD_ADDR_MIS;
1392 cs->exception_index = RISCV_EXCP_LOAD_ACCESS_FAULT;
1396 cs->exception_index = RISCV_EXCP_STORE_AMO_ADDR_MIS;
1399 cs->exception_index = RISCV_EXCP_STORE_AMO_ACCESS_FAULT;
1405 env->badaddr = addr;
1406 env->two_stage_lookup = mmuidx_2stage(mmu_idx);
1407 env->two_stage_indirect_lookup = false;
1438 CPURISCVState *env = &cpu->env;
1451 env->guest_phys_fault_addr = 0;
1460 &env->guest_phys_fault_addr, access_type,
1464 * A G-stage exception may be triggered during two state lookup.
1465 * And the env->guest_phys_fault_addr has already been set in
1474 "%s 1st-stage address=%" VADDR_PRIx " ret %d physical "
1487 "%s 2nd-stage address=%" VADDR_PRIx
1512 env->guest_phys_fault_addr = (im_address |
1514 (TARGET_PAGE_SIZE - 1))) >> 2;
1548 tlb_set_page(cs, address & ~(tlb_size - 1), pa & ~(tlb_size - 1),
1564 * be a no-op and we'll resume the mmu_exception path.
1778 xinsn = SET_RS1(xinsn, (taddr - (env->gpr[access_rs1] + access_imm)) &
1779 (access_size - 1));
1810 CPURISCVState *env = &cpu->env;
1811 bool virt = env->virt_enabled;
1813 bool always_storeamo = (env->excp_uw2 & RISCV_UW2_ALWAYS_STORE_AMO);
1817 * cs->exception is 32-bits wide unlike mcause which is XLEN-bits wide
1820 bool async = !!(cs->exception_index & RISCV_EXCP_INT_FLAG);
1821 target_ulong cause = cs->exception_index & RISCV_EXCP_INT_MASK;
1822 uint64_t deleg = async ? env->mideleg : env->medeleg;
1823 bool s_injected = env->mvip & (1ULL << cause) & env->mvien &&
1824 !(env->mip & (1ULL << cause));
1825 bool vs_injected = env->hvip & (1ULL << cause) & env->hvien &&
1826 !(env->mip & (1ULL << cause));
1840 env->pc += 4;
1854 write_gva = env->two_stage_lookup;
1855 tval = env->badaddr;
1856 if (env->two_stage_indirect_lookup) {
1858 * special pseudoinstruction for G-stage fault taken while
1859 * doing VS-stage page table walk.
1865 * non-zero only for misaligned access.
1867 tinst = riscv_transformed_insn(env, env->bins, tval);
1874 write_gva = env->two_stage_lookup;
1875 tval = env->badaddr;
1876 if (env->two_stage_indirect_lookup) {
1878 * special pseudoinstruction for G-stage fault taken while
1879 * doing VS-stage page table walk.
1886 tval = env->bins;
1889 tval = env->badaddr;
1890 if (cs->watchpoint_hit) {
1891 tval = cs->watchpoint_hit->hitaddr;
1892 cs->watchpoint_hit = NULL;
1896 tval = env->sw_check_code;
1903 assert(env->priv <= 3);
1905 if (env->priv == PRV_M) {
1907 } else if (env->priv == PRV_S && env->virt_enabled) {
1909 } else if (env->priv == PRV_S && !env->virt_enabled) {
1911 } else if (env->priv == PRV_U) {
1917 trace_riscv_trap(env->mhartid, async, cause, env->pc, tval,
1923 __func__, env->mhartid, async, cause, env->pc, tval,
1926 if (env->priv <= PRV_S && cause < 64 &&
1928 /* handle the trap in S-mode */
1931 env->mstatus = set_field(env->mstatus, MSTATUS_SPELP, env->elp);
1935 uint64_t hdeleg = async ? env->hideleg : env->hedeleg;
1937 if (env->virt_enabled &&
1946 cause = cause - 1;
1949 } else if (env->virt_enabled) {
1952 env->hstatus = set_field(env->hstatus, HSTATUS_SPVP,
1953 env->priv);
1954 env->hstatus = set_field(env->hstatus, HSTATUS_SPV, true);
1956 htval = env->guest_phys_fault_addr;
1961 env->hstatus = set_field(env->hstatus, HSTATUS_SPV, false);
1962 htval = env->guest_phys_fault_addr;
1964 env->hstatus = set_field(env->hstatus, HSTATUS_GVA, write_gva);
1967 s = env->mstatus;
1969 s = set_field(s, MSTATUS_SPP, env->priv);
1971 env->mstatus = s;
1973 env->scause = cause | ((target_ulong)async << (sxlen - 1));
1974 env->sepc = env->pc;
1975 env->stval = tval;
1976 env->htval = htval;
1977 env->htinst = tinst;
1978 env->pc = (env->stvec >> 2 << 2) +
1979 ((async && (env->stvec & 3) == 1) ? cause * 4 : 0);
1982 /* handle the trap in M-mode */
1985 env->mstatus = set_field(env->mstatus, MSTATUS_MPELP, env->elp);
1989 if (env->virt_enabled) {
1992 env->mstatus = set_field(env->mstatus, MSTATUS_MPV,
1993 env->virt_enabled);
1994 if (env->virt_enabled && tval) {
1995 env->mstatus = set_field(env->mstatus, MSTATUS_GVA, 1);
1998 mtval2 = env->guest_phys_fault_addr;
2004 s = env->mstatus;
2006 s = set_field(s, MSTATUS_MPP, env->priv);
2008 env->mstatus = s;
2010 env->mcause = cause | ((target_ulong)async << (mxlen - 1));
2011 env->mepc = env->pc;
2012 env->mtval = tval;
2013 env->mtval2 = mtval2;
2014 env->mtinst = tinst;
2015 env->pc = (env->mtvec >> 2 << 2) +
2016 ((async && (env->mtvec & 3) == 1) ? cause * 4 : 0);
2025 env->elp = false;
2031 * RISC-V ISA Specification.
2034 env->two_stage_lookup = false;
2035 env->two_stage_indirect_lookup = false;