target/riscv/cpu.c

44 const uint32_t misa_bits[] = {RVI, RVE, RVM, RVA, RVF, RVD, RVV,
445     riscv_cpu_set_misa_ext(env, RVI | RVM | RVA | RVF | RVD | RVC | RVU);  in riscv_any_cpu_init()
500     riscv_cpu_set_misa_ext(env, RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU);  in rv64_sifive_u_cpu_init()
518     riscv_cpu_set_misa_ext(env, RVI | RVM | RVA | RVC | RVU);  in rv64_sifive_e_cpu_init()
629     riscv_cpu_set_misa_ext(env, RVI);  in rv64i_bare_cpu_init()
659     riscv_cpu_set_misa_ext(env, RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU);  in rv32_sifive_u_cpu_init()
677     riscv_cpu_set_misa_ext(env, RVI | RVM | RVA | RVC | RVU);  in rv32_sifive_e_cpu_init()
694     riscv_cpu_set_misa_ext(env, RVI | RVM | RVC | RVU);  in rv32_ibex_cpu_init()
711     riscv_cpu_set_misa_ext(env, RVI | RVM | RVA | RVF | RVC | RVU);  in rv32_imafcu_nommu_cpu_init()
726     riscv_cpu_set_misa_ext(env, RVI);  in rv32i_bare_cpu_init()
1403     MISA_EXT_INFO(RVI, "i", "Base integer instruction set"),
2213     .misa_ext = RVI | RVM | RVA | RVF | RVD | RVC | RVU,