target/riscv/cpu.c

469      * Bare CPUs do not default to the max available.  in set_satp_mode_default_map()
733     /* Initialized default priorities of local interrupts. */  in riscv_cpu_reset_hold()
781     /* Default NaN value: sign bit clear, frac msb set */  in riscv_cpu_reset_hold()
826     default:  in riscv_cpu_disas_set_info()
845             /* If unset by the user, we fallback to the default satp mode. */  in riscv_cpu_satp_mode_finalize()
1049         default:  in riscv_cpu_set_irq()
1109      * ISA. To keep compatibility we'll always default them to 'true'  in riscv_cpu_init()
1116     /* Default values for non-bool cpu properties */  in riscv_cpu_init()
1191     default:  in riscv_cpu_validate_misa_mxl()
1637     default:  in priv_spec_to_str()
2008     default:  in prop_marchid_set()
2641      * it with -x and default to 'false'.
2657     default:  in riscv_gdb_arch_name()
2953          * Support all available satp_mode settings. By default