Lines Matching +full:- +full:a
2 * Power ISA decode for Fixed-Point Facility instructions
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 * You should have received a copy of the GNU Lesser General Public
21 * Fixed-Point Load/Store Instructions
36 mop ^= ctx->default_tcg_memop_mask;
38 tcg_gen_qemu_st_tl(cpu_gpr[rt], ea, ctx->mem_idx, mop);
40 tcg_gen_qemu_ld_tl(cpu_gpr[rt], ea, ctx->mem_idx, mop);
48 static bool do_ldst_D(DisasContext *ctx, arg_D *a, bool update, bool store,
51 return do_ldst(ctx, a->rt, a->ra, tcg_constant_tl(a->si), update, store, mop);
54 static bool do_ldst_PLS_D(DisasContext *ctx, arg_PLS_D *a, bool update,
58 if (!resolve_PLS_D(ctx, &d, a)) {
64 static bool do_ldst_X(DisasContext *ctx, arg_X *a, bool update,
67 return do_ldst(ctx, a->rt, a->ra, cpu_gpr[a->rb], update, store, mop);
70 static bool do_ldst_quad(DisasContext *ctx, arg_D *a, bool store, bool prefixed)
79 if (!prefixed && !(ctx->insns_flags2 & PPC2_LSQ_ISA207)) {
83 if (ctx->le_mode) {
89 if (!store && unlikely(a->ra == a->rt)) {
95 ea = do_ea_calc(ctx, a->ra, tcg_constant_tl(a->si));
97 if (ctx->le_mode && prefixed) {
98 lo = cpu_gpr[a->rt];
99 hi = cpu_gpr[a->rt + 1];
101 lo = cpu_gpr[a->rt + 1];
102 hi = cpu_gpr[a->rt];
108 tcg_gen_qemu_st_i128(t16, ea, ctx->mem_idx, DEF_MEMOP(MO_128));
110 tcg_gen_qemu_ld_i128(t16, ea, ctx->mem_idx, DEF_MEMOP(MO_128));
120 static bool do_ldst_quad_PLS_D(DisasContext *ctx, arg_PLS_D *a, bool store)
123 if (!resolve_PLS_D(ctx, &d, a)) {
208 * Fixed-Point Compare Instructions
211 static bool do_cmp_X(DisasContext *ctx, arg_X_bfl *a, bool s)
213 if ((ctx->insns_flags & PPC_64B) == 0) {
215 * For 32-bit implementations, The Programming Environments Manual says
217 * invalid." It seems, however, that most 32-bit CPUs ignore invalid
223 if (a->l) {
224 if ((ctx->insns_flags2 & PPC2_BOOKE206)) {
226 * For 32-bit Book E v2.06 implementations (i.e. e500/e500mc),
233 s ? "" : "L", ctx->cia);
236 gen_op_cmp32(cpu_gpr[a->ra], cpu_gpr[a->rb], s, a->bf);
240 /* For 64-bit implementations, deal with bit L accordingly. */
241 if (a->l) {
242 gen_op_cmp(cpu_gpr[a->ra], cpu_gpr[a->rb], s, a->bf);
244 gen_op_cmp32(cpu_gpr[a->ra], cpu_gpr[a->rb], s, a->bf);
249 static bool do_cmp_D(DisasContext *ctx, arg_D_bf *a, bool s)
251 if ((ctx->insns_flags & PPC_64B) == 0) {
253 * For 32-bit implementations, The Programming Environments Manual says
255 * invalid." It seems, however, that most 32-bit CPUs ignore invalid
261 if (a->l) {
262 if ((ctx->insns_flags2 & PPC2_BOOKE206)) {
264 * For 32-bit Book E v2.06 implementations (i.e. e500/e500mc),
271 s ? "I" : "LI", ctx->cia);
274 gen_op_cmp32(cpu_gpr[a->ra], tcg_constant_tl(a->imm), s, a->bf);
278 /* For 64-bit implementations, deal with bit L accordingly. */
279 if (a->l) {
280 gen_op_cmp(cpu_gpr[a->ra], tcg_constant_tl(a->imm), s, a->bf);
282 gen_op_cmp32(cpu_gpr[a->ra], tcg_constant_tl(a->imm), s, a->bf);
292 static bool trans_CMPRB(DisasContext *ctx, arg_CMPRB *a)
298 TCGv_i32 crf = cpu_crf[a->bf];
301 tcg_gen_trunc_tl_i32(src1, cpu_gpr[a->ra]);
302 tcg_gen_trunc_tl_i32(src2, cpu_gpr[a->rb]);
312 if (a->l) {
324 static bool trans_CMPEQB(DisasContext *ctx, arg_CMPEQB *a)
329 gen_helper_CMPEQB(cpu_crf[a->bf], cpu_gpr[a->ra], cpu_gpr[a->rb]);
337 * Fixed-Point Arithmetic Instructions
340 static bool trans_ADDI(DisasContext *ctx, arg_D *a)
342 if (a->ra) {
343 tcg_gen_addi_tl(cpu_gpr[a->rt], cpu_gpr[a->ra], a->si);
345 tcg_gen_movi_tl(cpu_gpr[a->rt], a->si);
350 static bool trans_PADDI(DisasContext *ctx, arg_PLS_D *a)
353 if (!resolve_PLS_D(ctx, &d, a)) {
359 static bool trans_ADDIS(DisasContext *ctx, arg_D *a)
361 a->si <<= 16;
362 return trans_ADDI(ctx, a);
365 static bool trans_ADDPCIS(DisasContext *ctx, arg_DX *a)
368 tcg_gen_movi_tl(cpu_gpr[a->rt], ctx->base.pc_next + (a->d << 16));
372 static bool trans_ADDEX(DisasContext *ctx, arg_X *a)
375 gen_op_arith_add(ctx, cpu_gpr[a->rt], cpu_gpr[a->ra], cpu_gpr[a->rb],
380 static bool do_add_D(DisasContext *ctx, arg_D *a, bool add_ca, bool compute_ca,
383 gen_op_arith_add(ctx, cpu_gpr[a->rt], cpu_gpr[a->ra],
384 tcg_constant_tl(a->si), cpu_ca, cpu_ca32,
389 static bool do_add_XO(DisasContext *ctx, arg_XO *a, bool add_ca,
392 gen_op_arith_add(ctx, cpu_gpr[a->rt], cpu_gpr[a->ra], cpu_gpr[a->rb],
393 cpu_ca, cpu_ca32, add_ca, compute_ca, a->oe, a->rc);
397 static bool do_add_const_XO(DisasContext *ctx, arg_XO_ta *a, TCGv const_val,
400 gen_op_arith_add(ctx, cpu_gpr[a->rt], cpu_gpr[a->ra], const_val,
401 cpu_ca, cpu_ca32, add_ca, compute_ca, a->oe, a->rc);
408 TRANS(ADDME, do_add_const_XO, tcg_constant_tl(-1LL), true, true);
413 static bool trans_SUBFIC(DisasContext *ctx, arg_D *a)
415 gen_op_arith_subf(ctx, cpu_gpr[a->rt], cpu_gpr[a->ra],
416 tcg_constant_tl(a->si), false, true, false, false);
420 static bool do_subf_XO(DisasContext *ctx, arg_XO *a, bool add_ca,
423 gen_op_arith_subf(ctx, cpu_gpr[a->rt], cpu_gpr[a->ra], cpu_gpr[a->rb],
424 add_ca, compute_ca, a->oe, a->rc);
428 static bool do_subf_const_XO(DisasContext *ctx, arg_XO_ta *a, TCGv const_val,
431 gen_op_arith_subf(ctx, cpu_gpr[a->rt], cpu_gpr[a->ra], const_val,
432 add_ca, compute_ca, a->oe, a->rc);
439 TRANS(SUBFME, do_subf_const_XO, tcg_constant_tl(-1LL), true, true)
442 static bool trans_MULLI(DisasContext *ctx, arg_MULLI *a)
444 tcg_gen_muli_tl(cpu_gpr[a->rt], cpu_gpr[a->ra], a->si);
448 static bool trans_MULLW(DisasContext *ctx, arg_MULLW *a)
453 tcg_gen_ext32s_tl(t0, cpu_gpr[a->ra]);
454 tcg_gen_ext32s_tl(t1, cpu_gpr[a->rb]);
455 tcg_gen_mul_tl(cpu_gpr[a->rt], t0, t1);
456 if (unlikely(a->rc)) {
457 gen_set_Rc0(ctx, cpu_gpr[a->rt]);
462 static bool trans_MULLWO(DisasContext *ctx, arg_MULLWO *a)
468 tcg_gen_ext32s_i64(t0, cpu_gpr[a->ra]);
469 tcg_gen_ext32s_i64(t1, cpu_gpr[a->rb]);
470 tcg_gen_mul_i64(cpu_gpr[a->rt], t0, t1);
471 tcg_gen_sextract_i64(t0, cpu_gpr[a->rt], 31, 1);
472 tcg_gen_sari_i64(t1, cpu_gpr[a->rt], 32);
474 tcg_gen_muls2_i32(cpu_gpr[a->rt], t1, cpu_gpr[a->ra], cpu_gpr[a->rb]);
475 tcg_gen_sari_i32(t0, cpu_gpr[a->rt], 31);
483 if (unlikely(a->rc)) {
484 gen_set_Rc0(ctx, cpu_gpr[a->rt]);
489 static bool do_mulhw(DisasContext *ctx, arg_XO_tab_rc *a,
495 tcg_gen_trunc_tl_i32(t0, cpu_gpr[a->ra]);
496 tcg_gen_trunc_tl_i32(t1, cpu_gpr[a->rb]);
498 tcg_gen_extu_i32_tl(cpu_gpr[a->rt], t1);
499 if (unlikely(a->rc)) {
500 gen_set_Rc0(ctx, cpu_gpr[a->rt]);
508 static bool do_divw(DisasContext *ctx, arg_XO *a, int sign)
510 gen_op_arith_divw(ctx, cpu_gpr[a->rt], cpu_gpr[a->ra], cpu_gpr[a->rb],
511 sign, a->oe, a->rc);
515 static bool do_dive(DisasContext *ctx, arg_XO *a,
519 helper(cpu_gpr[a->rt], tcg_env, cpu_gpr[a->ra], cpu_gpr[a->rb],
520 tcg_constant_i32(a->oe));
521 if (unlikely(a->rc)) {
522 gen_set_Rc0(ctx, cpu_gpr[a->rt]);
532 static bool do_modw(DisasContext *ctx, arg_X *a, bool sign)
535 gen_op_arith_modw(ctx, cpu_gpr[a->rt], cpu_gpr[a->ra], cpu_gpr[a->rb],
543 static bool trans_NEG(DisasContext *ctx, arg_NEG *a)
545 if (a->oe) {
547 gen_op_arith_subf(ctx, cpu_gpr[a->rt], cpu_gpr[a->ra], zero,
548 false, false, true, a->rc);
550 tcg_gen_neg_tl(cpu_gpr[a->rt], cpu_gpr[a->ra]);
551 if (unlikely(a->rc)) {
552 gen_set_Rc0(ctx, cpu_gpr[a->rt]);
558 static bool trans_DARN(DisasContext *ctx, arg_DARN *a)
563 if (a->l > 2) {
564 tcg_gen_movi_i64(cpu_gpr[a->rt], -1);
566 translator_io_start(&ctx->base);
567 if (a->l == 0) {
568 gen_helper_DARN32(cpu_gpr[a->rt]);
570 /* Return 64-bit random for both CRN and RRN */
571 gen_helper_DARN64(cpu_gpr[a->rt]);
580 static bool trans_MULLD(DisasContext *ctx, arg_MULLD *a)
584 tcg_gen_mul_tl(cpu_gpr[a->rt], cpu_gpr[a->ra], cpu_gpr[a->rb]);
585 if (unlikely(a->rc)) {
586 gen_set_Rc0(ctx, cpu_gpr[a->rt]);
594 static bool trans_MULLDO(DisasContext *ctx, arg_MULLD *a)
601 tcg_gen_muls2_i64(t0, t1, cpu_gpr[a->ra], cpu_gpr[a->rb]);
602 tcg_gen_mov_i64(cpu_gpr[a->rt], t0);
611 if (unlikely(a->rc)) {
612 gen_set_Rc0(ctx, cpu_gpr[a->rt]);
620 static bool do_mulhd(DisasContext *ctx, arg_XO_tab_rc *a,
624 helper(lo, cpu_gpr[a->rt], cpu_gpr[a->ra], cpu_gpr[a->rb]);
625 if (unlikely(a->rc)) {
626 gen_set_Rc0(ctx, cpu_gpr[a->rt]);
634 static bool trans_MADDLD(DisasContext *ctx, arg_MADDLD *a)
641 tcg_gen_mul_i64(t1, cpu_gpr[a->vra], cpu_gpr[a->vrb]);
642 tcg_gen_add_i64(cpu_gpr[a->vrt], t1, cpu_gpr[a->rc]);
649 static bool trans_MADDHD(DisasContext *ctx, arg_MADDHD *a)
658 tcg_gen_muls2_i64(lo, hi, cpu_gpr[a->vra], cpu_gpr[a->vrb]);
659 tcg_gen_sari_i64(t1, cpu_gpr[a->rc], 63);
660 tcg_gen_add2_i64(t1, cpu_gpr[a->vrt], lo, hi, cpu_gpr[a->rc], t1);
667 static bool trans_MADDHDU(DisasContext *ctx, arg_MADDHDU *a)
676 tcg_gen_mulu2_i64(lo, hi, cpu_gpr[a->vra], cpu_gpr[a->vrb]);
677 tcg_gen_add2_i64(t1, cpu_gpr[a->vrt], lo, hi, cpu_gpr[a->rc],
685 static bool do_divd(DisasContext *ctx, arg_XO *a, bool sign)
689 gen_op_arith_divd(ctx, cpu_gpr[a->rt], cpu_gpr[a->ra], cpu_gpr[a->rb],
690 sign, a->oe, a->rc);
697 static bool do_modd(DisasContext *ctx, arg_X *a, bool sign)
702 gen_op_arith_modd(ctx, cpu_gpr[a->rt], cpu_gpr[a->ra], cpu_gpr[a->rb],
713 static bool trans_DIVDE(DisasContext *ctx, arg_DIVDE *a)
717 return do_dive(ctx, a, gen_helper_DIVDE);
723 static bool trans_DIVDEU(DisasContext *ctx, arg_DIVDEU *a)
727 return do_dive(ctx, a, gen_helper_DIVDEU);
738 * Fixed-Point Select Instructions
741 static bool trans_ISEL(DisasContext *ctx, arg_ISEL *a)
744 uint32_t bi = a->bc;
753 tcg_gen_movcond_tl(TCG_COND_NE, cpu_gpr[a->rt], t0, zr,
754 a->ra ? cpu_gpr[a->ra] : zr,
755 cpu_gpr[a->rb]);
760 * Fixed-Point Trap Instructions
763 static bool trans_TW(DisasContext *ctx, arg_TW *a)
767 if (check_unconditional_trap(ctx, a->rt)) {
770 t0 = tcg_constant_i32(a->rt);
771 gen_helper_TW(tcg_env, cpu_gpr[a->ra], cpu_gpr[a->rb], t0);
775 static bool trans_TWI(DisasContext *ctx, arg_TWI *a)
780 if (check_unconditional_trap(ctx, a->rt)) {
783 t0 = tcg_constant_tl(a->si);
784 t1 = tcg_constant_i32(a->rt);
785 gen_helper_TW(tcg_env, cpu_gpr[a->ra], t0, t1);
789 static bool trans_TD(DisasContext *ctx, arg_TD *a)
795 if (check_unconditional_trap(ctx, a->rt)) {
798 t0 = tcg_constant_i32(a->rt);
799 gen_helper_TD(tcg_env, cpu_gpr[a->ra], cpu_gpr[a->rb], t0);
806 static bool trans_TDI(DisasContext *ctx, arg_TDI *a)
813 if (check_unconditional_trap(ctx, a->rt)) {
816 t0 = tcg_constant_tl(a->si);
817 t1 = tcg_constant_i32(a->rt);
818 gen_helper_TD(tcg_env, cpu_gpr[a->ra], t0, t1);
825 static bool trans_INVALID(DisasContext *ctx, arg_INVALID *a)
831 static bool trans_PNOP(DisasContext *ctx, arg_PNOP *a)
836 static bool do_set_bool_cond(DisasContext *ctx, arg_X_bi *a, bool neg, bool rev)
839 uint32_t mask = 0x08 >> (a->bi & 0x03);
844 tcg_gen_extu_i32_tl(temp, cpu_crf[a->bi >> 2]);
847 tcg_gen_negsetcond_tl(cond, cpu_gpr[a->rt], temp, zero);
849 tcg_gen_setcond_tl(cond, cpu_gpr[a->rt], temp, zero);
860 * Fixed-Point Logical Instructions
863 static bool do_addi_(DisasContext *ctx, arg_D_ui *a, bool shift)
865 tcg_gen_andi_tl(cpu_gpr[a->ra], cpu_gpr[a->rt], shift ? a->ui << 16 : a->ui);
866 gen_set_Rc0(ctx, cpu_gpr[a->ra]);
870 static bool do_ori(DisasContext *ctx, arg_D_ui *a, bool shift)
872 if (a->rt == a->ra && a->ui == 0) {
876 tcg_gen_ori_tl(cpu_gpr[a->ra], cpu_gpr[a->rt], shift ? a->ui << 16 : a->ui);
880 static bool do_xori(DisasContext *ctx, arg_D_ui *a, bool shift)
882 if (a->rt == a->ra && a->ui == 0) {
886 tcg_gen_xori_tl(cpu_gpr[a->ra], cpu_gpr[a->rt], shift ? a->ui << 16 : a->ui);
890 static bool do_logical1(DisasContext *ctx, arg_X_sa_rc *a,
893 helper(cpu_gpr[a->ra], cpu_gpr[a->rs]);
894 if (unlikely(a->rc)) {
895 gen_set_Rc0(ctx, cpu_gpr[a->ra]);
900 static bool do_logical2(DisasContext *ctx, arg_X_rc *a,
903 helper(cpu_gpr[a->ra], cpu_gpr[a->rt], cpu_gpr[a->rb]);
904 if (unlikely(a->rc)) {
905 gen_set_Rc0(ctx, cpu_gpr[a->ra]);
910 static bool trans_OR(DisasContext *ctx, arg_OR *a)
913 if (a->rt != a->ra || a->rt != a->rb) {
914 if (a->rt != a->rb) {
915 tcg_gen_or_tl(cpu_gpr[a->ra], cpu_gpr[a->rt], cpu_gpr[a->rb]);
917 tcg_gen_mov_tl(cpu_gpr[a->ra], cpu_gpr[a->rt]);
919 if (unlikely(a->rc)) {
920 gen_set_Rc0(ctx, cpu_gpr[a->ra]);
922 } else if (unlikely(a->rc)) {
923 gen_set_Rc0(ctx, cpu_gpr[a->rt]);
925 } else if (a->rt != 0) { /* 0 is nop */
928 switch (a->rt) {
934 /* Set process priority to medium-low */
943 if (!ctx->pr) {
949 if (!ctx->pr) {
950 /* Set process priority to medium-hight */
955 if (!ctx->pr) {
961 if (ctx->hv && !ctx->pr) {
981 * encodings other than no-op, e.g., miso(rs=26), yield(27),
992 static bool trans_XOR(DisasContext *ctx, arg_XOR *a)
995 if (a->rt != a->rb) {
996 tcg_gen_xor_tl(cpu_gpr[a->ra], cpu_gpr[a->rt], cpu_gpr[a->rb]);
998 tcg_gen_movi_tl(cpu_gpr[a->ra], 0);
1000 if (unlikely(a->rc)) {
1001 gen_set_Rc0(ctx, cpu_gpr[a->ra]);
1006 static bool trans_CMPB(DisasContext *ctx, arg_CMPB *a)
1009 gen_helper_CMPB(cpu_gpr[a->ra], cpu_gpr[a->rt], cpu_gpr[a->rb]);
1013 static bool do_cntzw(DisasContext *ctx, arg_X_sa_rc *a,
1018 tcg_gen_trunc_tl_i32(t, cpu_gpr[a->rs]);
1020 tcg_gen_extu_i32_tl(cpu_gpr[a->ra], t);
1022 if (unlikely(a->rc)) {
1023 gen_set_Rc0(ctx, cpu_gpr[a->ra]);
1029 static bool do_cntzd(DisasContext *ctx, arg_X_sa_rc *a,
1032 helper(cpu_gpr[a->ra], cpu_gpr[a->rs], 64);
1033 if (unlikely(a->rc)) {
1034 gen_set_Rc0(ctx, cpu_gpr[a->ra]);
1040 static bool trans_CNTLZD(DisasContext *ctx, arg_CNTLZD *a)
1044 do_cntzd(ctx, a, tcg_gen_clzi_i64);
1051 static bool trans_CNTTZD(DisasContext *ctx, arg_CNTTZD *a)
1056 do_cntzd(ctx, a, tcg_gen_ctzi_i64);
1063 static bool trans_POPCNTB(DisasContext *ctx, arg_POPCNTB *a)
1066 gen_helper_POPCNTB(cpu_gpr[a->ra], cpu_gpr[a->rs]);
1070 static bool trans_POPCNTW(DisasContext *ctx, arg_POPCNTW *a)
1074 gen_helper_POPCNTW(cpu_gpr[a->ra], cpu_gpr[a->rs]);
1076 tcg_gen_ctpop_i32(cpu_gpr[a->ra], cpu_gpr[a->rs]);
1081 static bool trans_POPCNTD(DisasContext *ctx, arg_POPCNTD *a)
1086 tcg_gen_ctpop_i64(cpu_gpr[a->ra], cpu_gpr[a->rs]);
1093 static bool trans_PRTYW(DisasContext *ctx, arg_PRTYW *a)
1095 TCGv ra = cpu_gpr[a->ra];
1096 TCGv rs = cpu_gpr[a->rs];
1108 static bool trans_PRTYD(DisasContext *ctx, arg_PRTYD *a)
1110 TCGv ra = cpu_gpr[a->ra];
1111 TCGv rs = cpu_gpr[a->rs];
1126 static bool trans_BPERMD(DisasContext *ctx, arg_BPERMD *a)
1131 gen_helper_BPERMD(cpu_gpr[a->ra], cpu_gpr[a->rt], cpu_gpr[a->rb]);
1138 static bool trans_CFUGED(DisasContext *ctx, arg_X *a)
1143 gen_helper_CFUGED(cpu_gpr[a->ra], cpu_gpr[a->rt], cpu_gpr[a->rb]);
1159 tcg_gen_ctzi_i64(t0, t0, -1);
1161 tcg_gen_clzi_i64(t0, t0, -1);
1164 tcg_gen_setcondi_i64(TCG_COND_NE, t1, t0, -1);
1178 static bool trans_CNTLZDM(DisasContext *ctx, arg_X *a)
1183 do_cntzdm(cpu_gpr[a->ra], cpu_gpr[a->rt], cpu_gpr[a->rb], false);
1190 static bool trans_CNTTZDM(DisasContext *ctx, arg_X *a)
1195 do_cntzdm(cpu_gpr[a->ra], cpu_gpr[a->rt], cpu_gpr[a->rb], true);
1202 static bool trans_PDEPD(DisasContext *ctx, arg_X *a)
1207 gen_helper_PDEPD(cpu_gpr[a->ra], cpu_gpr[a->rt], cpu_gpr[a->rb]);
1214 static bool trans_PEXTD(DisasContext *ctx, arg_X *a)
1219 gen_helper_PEXTD(cpu_gpr[a->ra], cpu_gpr[a->rt], cpu_gpr[a->rb]);
1247 static bool trans_ADDG6S(DisasContext *ctx, arg_X *a)
1249 const target_ulong carry_bits = (target_ulong)-1 / 0xf;
1255 in1 = cpu_gpr[a->ra];
1256 in2 = cpu_gpr[a->rb];
1269 * The carry-out that we're looking for is the carry-in to
1270 * the next nibble. Shift the double-word down one nibble,
1277 tcg_gen_muli_tl(cpu_gpr[a->rt], carryl, 6);
1281 static bool trans_CDTBCD(DisasContext *ctx, arg_X_sa *a)
1284 gen_helper_CDTBCD(cpu_gpr[a->ra], cpu_gpr[a->rs]);
1288 static bool trans_CBCDTD(DisasContext *ctx, arg_X_sa *a)
1291 gen_helper_CBCDTD(cpu_gpr[a->ra], cpu_gpr[a->rs]);
1295 static bool do_hash(DisasContext *ctx, arg_X *a, bool priv,
1300 if (!(ctx->insns_flags2 & PPC2_ISA310)) {
1301 /* if version is before v3.1, this operation is a nop */
1310 if (unlikely(a->ra == 0)) {
1316 ea = do_ea_calc(ctx, a->ra, tcg_constant_tl(a->rt));
1317 helper(tcg_env, ea, cpu_gpr[a->ra], cpu_gpr[a->rb]);