359         qemu_printf("Cannot access KVM TLB\n");  in mmubooke_dump_mmu()
364     qemu_printf("\nTLB:\n");  in mmubooke_dump_mmu()
365     qemu_printf("Effective          Physical           Size PID   Prot     "  in mmubooke_dump_mmu()
390         qemu_printf("0x%016" PRIx64 " 0x%016" PRIx64 " %s %-5u %08x %08x\n",  in mmubooke_dump_mmu()
403     qemu_printf("\nTLB%d:\n", tlbn);  in mmubooke206_dump_one_tlb()
404     qemu_printf("Effective          Physical           Size TID   TS SRWX"  in mmubooke206_dump_one_tlb()
421         qemu_printf("0x%016" PRIx64 " 0x%016" PRIx64 " %4s %-5u %1u  S%c%c%c"  in mmubooke206_dump_one_tlb()
452         qemu_printf("Cannot access KVM TLB\n");  in mmubooke206_dump_mmu()
492         qemu_printf("%s BAT%d BATu " TARGET_FMT_lx  in mmu6xx_dump_BATs()
507     qemu_printf("HTAB base = 0x%"HWADDR_PRIx"\n", ppc_hash32_hpt_base(cpu));  in mmu6xx_dump_mmu()
508     qemu_printf("HTAB mask = 0x%"HWADDR_PRIx"\n", ppc_hash32_hpt_mask(cpu));  in mmu6xx_dump_mmu()
510     qemu_printf("\nSegment registers:\n");  in mmu6xx_dump_mmu()
514             qemu_printf("%02d T=%d Ks=%d Kp=%d BUID=0x%03x "  in mmu6xx_dump_mmu()
520             qemu_printf("%02d T=%d Ks=%d Kp=%d N=%d VSID=0x%06x\n", i,  in mmu6xx_dump_mmu()
527     qemu_printf("\nBATs:\n");  in mmu6xx_dump_mmu()
531     qemu_printf("\nTLBs                       [EPN    EPN + SIZE]\n");  in mmu6xx_dump_mmu()
539                 qemu_printf("%s TLB %02d/%02d way:%d %s ["  in mmu6xx_dump_mmu()