Lines Matching +full:close +full:- +full:pr
6 #include "mmu-hash64.h"
10 #include "power8-pmu.h"
15 target_ulong msr = env->msr; in post_load_update_msr()
21 env->msr ^= env->msr_mask & ~((1ULL << MSR_TGPR) | MSR_HVB); in post_load_update_msr()
30 v->u64[0] = qemu_get_be64(f); in get_avr()
31 v->u64[1] = qemu_get_be64(f); in get_avr()
41 qemu_put_be64(f, v->u64[0]); in put_avr()
42 qemu_put_be64(f, v->u64[1]); in put_avr()
63 v->VsrD(0) = qemu_get_be64(f); in get_fpr()
73 qemu_put_be64(f, v->VsrD(0)); in put_fpr()
94 v->VsrD(1) = qemu_get_be64(f); in get_vsr()
104 qemu_put_be64(f, v->VsrD(1)); in put_vsr()
123 CPUPPCState *env = &cpu->env; in cpu_pre_save()
126 env->spr[SPR_LR] = env->lr; in cpu_pre_save()
127 env->spr[SPR_CTR] = env->ctr; in cpu_pre_save()
128 env->spr[SPR_XER] = cpu_read_xer(env); in cpu_pre_save()
130 env->spr[SPR_CFAR] = env->cfar; in cpu_pre_save()
132 env->spr[SPR_BOOKE_SPEFSCR] = env->spe_fscr; in cpu_pre_save()
134 for (i = 0; (i < 4) && (i < env->nb_BATs); i++) { in cpu_pre_save()
135 env->spr[SPR_DBAT0U + 2 * i] = env->DBAT[0][i]; in cpu_pre_save()
136 env->spr[SPR_DBAT0U + 2 * i + 1] = env->DBAT[1][i]; in cpu_pre_save()
137 env->spr[SPR_IBAT0U + 2 * i] = env->IBAT[0][i]; in cpu_pre_save()
138 env->spr[SPR_IBAT0U + 2 * i + 1] = env->IBAT[1][i]; in cpu_pre_save()
140 for (i = 0; (i < 4) && ((i + 4) < env->nb_BATs); i++) { in cpu_pre_save()
141 env->spr[SPR_DBAT4U + 2 * i] = env->DBAT[0][i + 4]; in cpu_pre_save()
142 env->spr[SPR_DBAT4U + 2 * i + 1] = env->DBAT[1][i + 4]; in cpu_pre_save()
143 env->spr[SPR_IBAT4U + 2 * i] = env->IBAT[0][i + 4]; in cpu_pre_save()
144 env->spr[SPR_IBAT4U + 2 * i + 1] = env->IBAT[1][i + 4]; in cpu_pre_save()
148 env->hflags_compat_nmsr = 0; in cpu_pre_save()
155 env->spr[SPR_DECR] = cpu_ppc_load_decr(env); in cpu_pre_save()
162 * Determine if a given PVR is a "close enough" match to the CPU
163 * object. For TCG and KVM PR it would probably be sufficient to
176 if (pvr == pcc->pvr) { in pvr_match()
179 return pcc->pvr_match(pcc, pvr, true); in pvr_match()
185 CPUPPCState *env = &cpu->env; in cpu_post_load()
197 if (cpu->compat_pvr) { in cpu_post_load()
198 uint32_t compat_pvr = cpu->compat_pvr; in cpu_post_load()
202 cpu->compat_pvr = 0; in cpu_post_load()
211 if (!pvr_match(cpu, env->spr[SPR_PVR])) { in cpu_post_load()
212 return -EINVAL; in cpu_post_load()
225 * if that is the case. Otherwise, it checks if we're running in KVM PR. in cpu_post_load()
226 * If the guest kernel does not have the cap and we're not running KVM-PR in cpu_post_load()
227 * (so, it is running KVM-HV), we need to ensure that KVM_SET_SREGS will in cpu_post_load()
232 env->spr[SPR_PVR] = env->spr_cb[SPR_PVR].default_value; in cpu_post_load()
235 env->lr = env->spr[SPR_LR]; in cpu_post_load()
236 env->ctr = env->spr[SPR_CTR]; in cpu_post_load()
237 cpu_write_xer(env, env->spr[SPR_XER]); in cpu_post_load()
239 env->cfar = env->spr[SPR_CFAR]; in cpu_post_load()
241 env->spe_fscr = env->spr[SPR_BOOKE_SPEFSCR]; in cpu_post_load()
243 for (i = 0; (i < 4) && (i < env->nb_BATs); i++) { in cpu_post_load()
244 env->DBAT[0][i] = env->spr[SPR_DBAT0U + 2 * i]; in cpu_post_load()
245 env->DBAT[1][i] = env->spr[SPR_DBAT0U + 2 * i + 1]; in cpu_post_load()
246 env->IBAT[0][i] = env->spr[SPR_IBAT0U + 2 * i]; in cpu_post_load()
247 env->IBAT[1][i] = env->spr[SPR_IBAT0U + 2 * i + 1]; in cpu_post_load()
249 for (i = 0; (i < 4) && ((i + 4) < env->nb_BATs); i++) { in cpu_post_load()
250 env->DBAT[0][i + 4] = env->spr[SPR_DBAT4U + 2 * i]; in cpu_post_load()
251 env->DBAT[1][i + 4] = env->spr[SPR_DBAT4U + 2 * i + 1]; in cpu_post_load()
252 env->IBAT[0][i + 4] = env->spr[SPR_IBAT4U + 2 * i]; in cpu_post_load()
253 env->IBAT[1][i + 4] = env->spr[SPR_IBAT4U + 2 * i + 1]; in cpu_post_load()
256 if (!cpu->vhyp) { in cpu_post_load()
257 ppc_store_sdr1(env, env->spr[SPR_SDR1]); in cpu_post_load()
263 /* Re-set breaks based on regs */ in cpu_post_load()
270 * TCG needs to re-start the decrementer timer and/or raise the in cpu_post_load()
271 * interrupt. This works for level-triggered decrementer. Edge in cpu_post_load()
274 cpu_ppc_store_decr(env, env->spr[SPR_DECR]); in cpu_post_load()
285 return cpu->env.insns_flags & PPC_FLOAT; in fpu_needed()
304 return cpu->env.insns_flags & PPC_ALTIVEC; in altivec_needed()
311 ppc_store_vscr(&cpu->env, qemu_get_be32(f)); in get_vscr()
319 qemu_put_be32(f, ppc_get_vscr(&cpu->env)); in put_vscr()
359 return cpu->env.insns_flags2 & PPC2_VSX; in vsx_needed()
378 CPUPPCState *env = &cpu->env; in tm_needed()
379 return FIELD_EX64(env->msr, MSR, TS); in tm_needed()
410 return !mmu_is_64bit(cpu->env.mmu_model); in sr_needed()
433 v->esid = qemu_get_be64(f); in get_slbe()
434 v->vsid = qemu_get_be64(f); in get_slbe()
444 qemu_put_be64(f, v->esid); in put_slbe()
445 qemu_put_be64(f, v->vsid); in put_slbe()
465 /* We don't support any of the old segment table based 64-bit CPUs */ in slb_needed()
466 return mmu_is_64bit(cpu->env.mmu_model); in slb_needed()
472 CPUPPCState *env = &cpu->env; in slb_post_load()
479 for (i = 0; i < cpu->hash64_opts->slb_size; i++) { in slb_post_load()
480 if (ppc_store_slb(cpu, i, env->slb[i].esid, env->slb[i].vsid) < 0) { in slb_post_load()
482 return -1; in slb_post_load()
517 CPUPPCState *env = &cpu->env; in tlb6xx_needed()
519 return env->nb_tlb && (env->tlb_type == TLB_6XX); in tlb6xx_needed()
556 CPUPPCState *env = &cpu->env; in tlbemb_needed()
558 return env->nb_tlb && (env->tlb_type == TLB_EMB); in tlbemb_needed()
592 CPUPPCState *env = &cpu->env; in tlbmas_needed()
594 return env->nb_tlb && (env->tlb_type == TLB_MAS); in tlbmas_needed()
616 assert(!(cpu->compat_pvr && !cpu->vhyp)); in compat_needed()
617 return cpu->compat_pvr != 0; in compat_needed()
656 return (cpu->env.flags & POWERPC_FLAG_BHRB) != 0; in bhrb_needed()