Lines Matching refs:fpscr
165 env->fpscr = (env->fpscr & ~FP_FPRF) | fprf; \
177 env->fpscr |= FP_VX; in COMPUTE_FPRF()
179 env->fpscr |= FP_FX; in COMPUTE_FPRF()
180 if (env->fpscr & FP_VE) { in COMPUTE_FPRF()
182 env->fpscr |= FP_FEX; in COMPUTE_FPRF()
193 env->fpscr &= ~(FP_FR | FP_FI); in finish_invalid_op_arith()
194 if (!(env->fpscr & FP_VE)) { in finish_invalid_op_arith()
196 env->fpscr &= ~FP_FPCC; in finish_invalid_op_arith()
197 env->fpscr |= (FP_C | FP_FU); in finish_invalid_op_arith()
206 env->fpscr |= FP_VXSNAN; in float_invalid_op_vxsnan()
214 env->fpscr |= FP_VXISI; in float_invalid_op_vxisi()
222 env->fpscr |= FP_VXIDI; in float_invalid_op_vxidi()
230 env->fpscr |= FP_VXZDZ; in float_invalid_op_vxzdz()
238 env->fpscr |= FP_VXIMZ; in float_invalid_op_vximz()
246 env->fpscr |= FP_VXSQRT; in float_invalid_op_vxsqrt()
254 env->fpscr |= FP_VXVC; in float_invalid_op_vxvc()
256 env->fpscr &= ~FP_FPCC; in float_invalid_op_vxvc()
257 env->fpscr |= (FP_C | FP_FU); in float_invalid_op_vxvc()
260 env->fpscr |= FP_VX; in float_invalid_op_vxvc()
262 env->fpscr |= FP_FX; in float_invalid_op_vxvc()
264 if (env->fpscr & FP_VE) { in float_invalid_op_vxvc()
270 env->fpscr |= FP_FEX; in float_invalid_op_vxvc()
279 env->fpscr |= FP_VXCVI; in float_invalid_op_vxcvi()
280 env->fpscr &= ~(FP_FR | FP_FI); in float_invalid_op_vxcvi()
281 if (!(env->fpscr & FP_VE)) { in float_invalid_op_vxcvi()
283 env->fpscr &= ~FP_FPCC; in float_invalid_op_vxcvi()
284 env->fpscr |= (FP_C | FP_FU); in float_invalid_op_vxcvi()
292 env->fpscr |= FP_ZX; in float_zero_divide_excp()
293 env->fpscr &= ~(FP_FR | FP_FI); in float_zero_divide_excp()
295 env->fpscr |= FP_FX; in float_zero_divide_excp()
296 if (env->fpscr & FP_ZE) { in float_zero_divide_excp()
298 env->fpscr |= FP_FEX; in float_zero_divide_excp()
311 env->fpscr |= FP_OX; in float_overflow_excp()
313 env->fpscr |= FP_FX; in float_overflow_excp()
315 bool overflow_enabled = !!(env->fpscr & FP_OE); in float_overflow_excp()
318 env->fpscr |= FP_FEX; in float_overflow_excp()
331 env->fpscr |= FP_UX; in float_underflow_excp()
333 env->fpscr |= FP_FX; in float_underflow_excp()
334 if (env->fpscr & FP_UE) { in float_underflow_excp()
336 env->fpscr |= FP_FEX; in float_underflow_excp()
347 env->fpscr |= FP_XX; in float_inexact_excp()
349 env->fpscr |= FP_FX; in float_inexact_excp()
350 if (env->fpscr & FP_XE) { in float_inexact_excp()
352 env->fpscr |= FP_FEX; in float_inexact_excp()
362 if (env->fpscr & mask) { in helper_fpscr_clrbit()
363 ppc_store_fpscr(env, env->fpscr & ~(target_ulong)mask); in helper_fpscr_clrbit()
370 if (!(env->fpscr & mask)) { in helper_fpscr_setbit()
371 ppc_store_fpscr(env, env->fpscr | mask); in helper_fpscr_setbit()
386 val = (val & mask) | (env->fpscr & ~mask); in helper_store_fpscr()
393 target_ulong fpscr = env->fpscr; in do_fpscr_check_status() local
396 if ((fpscr & FP_OX) && (fpscr & FP_OE)) { in do_fpscr_check_status()
398 } else if ((fpscr & FP_UX) && (fpscr & FP_UE)) { in do_fpscr_check_status()
400 } else if ((fpscr & FP_XX) && (fpscr & FP_XE)) { in do_fpscr_check_status()
402 } else if ((fpscr & FP_ZX) && (fpscr & FP_ZE)) { in do_fpscr_check_status()
404 } else if (fpscr & FP_VE) { in do_fpscr_check_status()
405 if (fpscr & FP_VXSOFT) { in do_fpscr_check_status()
407 } else if (fpscr & FP_VXSNAN) { in do_fpscr_check_status()
409 } else if (fpscr & FP_VXISI) { in do_fpscr_check_status()
411 } else if (fpscr & FP_VXIDI) { in do_fpscr_check_status()
413 } else if (fpscr & FP_VXZDZ) { in do_fpscr_check_status()
415 } else if (fpscr & FP_VXIMZ) { in do_fpscr_check_status()
417 } else if (fpscr & FP_VXVC) { in do_fpscr_check_status()
419 } else if (fpscr & FP_VXSQRT) { in do_fpscr_check_status()
421 } else if (fpscr & FP_VXCVI) { in do_fpscr_check_status()
431 env->fpscr |= FP_FEX; in do_fpscr_check_status()
459 env->fpscr = FIELD_DP64(env->fpscr, FPSCR, FI, in do_float_check_status()
549 env->fpscr |= FP_VXSNAN; in float_invalid_cvt()
896 env->fpscr &= ~FP_FPCC; in helper_fcmpu()
897 env->fpscr |= ret << FPSCR_FPCC; in helper_fcmpu()
927 env->fpscr &= ~FP_FPCC; in helper_fcmpo()
928 env->fpscr |= ret << FPSCR_FPCC; in helper_fcmpo()
2152 vxvc &= !(env->fpscr & FP_VE); \
2193 env->fpscr &= ~FP_FPCC; in helper_xscmpexpdp()
2194 env->fpscr |= cc << FPSCR_FPCC; in helper_xscmpexpdp()
2222 env->fpscr &= ~FP_FPCC; in helper_xscmpexpqp()
2223 env->fpscr |= cc << FPSCR_FPCC; in helper_xscmpexpqp()
2253 if (!(env->fpscr & FP_VE) && ordered) { in do_scalar_cmp()
2268 env->fpscr &= ~FP_FPCC; in do_scalar_cmp()
2269 env->fpscr |= cc << FPSCR_FPCC; in do_scalar_cmp()
2318 if (!(env->fpscr & FP_VE) && ordered) { in do_scalar_cmpq()
2333 env->fpscr &= ~FP_FPCC; in do_scalar_cmpq()
2334 env->fpscr |= cc << FPSCR_FPCC; in do_scalar_cmpq()
2468 vex_flag = (env->fpscr & FP_VE) && vxsnan_flag; \
3173 env->fpscr &= ~FP_FPCC; \
3174 env->fpscr |= cc << FPSCR_FPCC; \
3190 env->fpscr &= ~FP_FPCC; in VSX_XS_TSTDC()
3191 env->fpscr |= cc << FPSCR_FPCC; in VSX_XS_TSTDC()
3210 rmode = env->fpscr & FP_RN; in helper_xsrqpi()
3264 rmode = env->fpscr & FP_RN; in helper_xsrqpxp()
3360 enable = env->fpscr & (FP_ENABLES | FP_FI | FP_FR); in vsxger_excp()
3361 env->fpscr &= ~(FP_ENABLES | FP_FI | FP_FR); in vsxger_excp()
3375 env->fpscr |= enable; in vsxger_excp()