Lines Matching refs:PPC_BIT_NR
41 #define PPC_BIT_NR(bit) (63 - (bit)) macro
423 #define MSR_SF PPC_BIT_NR(0) /* Sixty-four-bit mode hflags */
424 #define MSR_TAG PPC_BIT_NR(1) /* Tag-active mode (POWERx ?) */
425 #define MSR_ISF PPC_BIT_NR(2) /* Sixty-four-bit interrupt mode on 630 */
426 #define MSR_HV PPC_BIT_NR(3) /* hypervisor state hflags */
427 #define MSR_TS0 PPC_BIT_NR(29) /* Transactional state, 2 bits (Book3s) */
428 #define MSR_TS1 PPC_BIT_NR(30)
429 #define MSR_TM PPC_BIT_NR(31) /* Transactional Memory Available (Book3s) */
430 #define MSR_CM PPC_BIT_NR(32) /* Computation mode for BookE hflags */
431 #define MSR_ICM PPC_BIT_NR(33) /* Interrupt computation mode for BookE */
432 #define MSR_GS PPC_BIT_NR(35) /* guest state for BookE */
433 #define MSR_UCLE PPC_BIT_NR(37) /* User-mode cache lock enable for BookE */
434 #define MSR_VR PPC_BIT_NR(38) /* altivec available x hflags */
435 #define MSR_SPE PPC_BIT_NR(38) /* SPE enable for BookE x hflags */
436 #define MSR_VSX PPC_BIT_NR(40) /* Vector Scalar Extension (>= 2.06)x hflags */
437 #define MSR_S PPC_BIT_NR(41) /* Secure state */
438 #define MSR_KEY PPC_BIT_NR(44) /* key bit on 603e */
439 #define MSR_POW PPC_BIT_NR(45) /* Power management */
440 #define MSR_WE PPC_BIT_NR(45) /* Wait State Enable on 405 */
441 #define MSR_TGPR PPC_BIT_NR(46) /* TGPR usage on 602/603 x */
442 #define MSR_CE PPC_BIT_NR(46) /* Critical int. enable on embedded PPC x */
443 #define MSR_ILE PPC_BIT_NR(47) /* Interrupt little-endian mode */
444 #define MSR_EE PPC_BIT_NR(48) /* External interrupt enable */
445 #define MSR_PR PPC_BIT_NR(49) /* Problem state hflags */
446 #define MSR_FP PPC_BIT_NR(50) /* Floating point available hflags */
447 #define MSR_ME PPC_BIT_NR(51) /* Machine check interrupt enable */
448 #define MSR_FE0 PPC_BIT_NR(52) /* Floating point exception mode 0 */
449 #define MSR_SE PPC_BIT_NR(53) /* Single-step trace enable x hflags */
450 #define MSR_DWE PPC_BIT_NR(53) /* Debug wait enable on 405 x */
451 #define MSR_UBLE PPC_BIT_NR(53) /* User BTB lock enable on e500 x */
452 #define MSR_BE PPC_BIT_NR(54) /* Branch trace enable x hflags */
453 #define MSR_DE PPC_BIT_NR(54) /* Debug int. enable on embedded PPC x */
454 #define MSR_FE1 PPC_BIT_NR(55) /* Floating point exception mode 1 */
455 #define MSR_AL PPC_BIT_NR(56) /* AL bit on POWER */
456 #define MSR_EP PPC_BIT_NR(57) /* Exception prefix on 601 */
457 #define MSR_IR PPC_BIT_NR(58) /* Instruction relocate */
458 #define MSR_IS PPC_BIT_NR(58) /* Instruction address space (BookE) */
459 #define MSR_DR PPC_BIT_NR(59) /* Data relocate */
460 #define MSR_DS PPC_BIT_NR(59) /* Data address space (BookE) */
461 #define MSR_PE PPC_BIT_NR(60) /* Protection enable on 403 */
462 #define MSR_PX PPC_BIT_NR(61) /* Protection exclusive on 403 x */
463 #define MSR_PMM PPC_BIT_NR(61) /* Performance monitor mark on POWER x */
464 #define MSR_RI PPC_BIT_NR(62) /* Recoverable interrupt 1 */
465 #define MSR_LE PPC_BIT_NR(63) /* Little-endian mode 1 hflags */
539 #define MMCR0_BHRBA_NR PPC_BIT_NR(42) /* BHRB Available */
554 #define MMCRA_IFM_SHIFT PPC_BIT_NR(33)
638 #define HFSCR_MSGP PPC_BIT_NR(53) /* Privileged Message Send Facilities */
639 #define HFSCR_BHRB PPC_BIT_NR(59) /* BHRB Instructions */
821 #define FPSCR_DRN2 PPC_BIT_NR(29) /* Decimal Floating-Point rounding ctrl. */
822 #define FPSCR_DRN1 PPC_BIT_NR(30) /* Decimal Floating-Point rounding ctrl. */
823 #define FPSCR_DRN0 PPC_BIT_NR(31) /* Decimal Floating-Point rounding ctrl. */
824 #define FPSCR_FX PPC_BIT_NR(32) /* Floating-point exception summary */
825 #define FPSCR_FEX PPC_BIT_NR(33) /* Floating-point enabled exception summ.*/
826 #define FPSCR_VX PPC_BIT_NR(34) /* Floating-point invalid op. excp. summ.*/
827 #define FPSCR_OX PPC_BIT_NR(35) /* Floating-point overflow exception */
828 #define FPSCR_UX PPC_BIT_NR(36) /* Floating-point underflow exception */
829 #define FPSCR_ZX PPC_BIT_NR(37) /* Floating-point zero divide exception */
830 #define FPSCR_XX PPC_BIT_NR(38) /* Floating-point inexact exception */
831 #define FPSCR_VXSNAN PPC_BIT_NR(39) /* Floating-point invalid op. excp (sNan)*/
832 #define FPSCR_VXISI PPC_BIT_NR(40) /* Floating-point invalid op. excp (inf) */
833 #define FPSCR_VXIDI PPC_BIT_NR(41) /* Floating-point invalid op. excp (inf) */
834 #define FPSCR_VXZDZ PPC_BIT_NR(42) /* Floating-point invalid op. excp (zero)*/
835 #define FPSCR_VXIMZ PPC_BIT_NR(43) /* Floating-point invalid op. excp (inf) */
836 #define FPSCR_VXVC PPC_BIT_NR(44) /* Floating-point invalid op. excp (comp)*/
837 #define FPSCR_FR PPC_BIT_NR(45) /* Floating-point fraction rounded */
838 #define FPSCR_FI PPC_BIT_NR(46) /* Floating-point fraction inexact */
839 #define FPSCR_C PPC_BIT_NR(47) /* Floating-point result class descriptor*/
840 #define FPSCR_FL PPC_BIT_NR(48) /* Floating-point less than or negative */
841 #define FPSCR_FG PPC_BIT_NR(49) /* Floating-point greater than or neg. */
842 #define FPSCR_FE PPC_BIT_NR(50) /* Floating-point equal or zero */
843 #define FPSCR_FU PPC_BIT_NR(51) /* Floating-point unordered or NaN */
844 #define FPSCR_FPCC PPC_BIT_NR(51) /* Floating-point condition code */
845 #define FPSCR_FPRF PPC_BIT_NR(51) /* Floating-point result flags */
846 #define FPSCR_VXSOFT PPC_BIT_NR(53) /* Floating-point invalid op. excp (soft)*/
847 #define FPSCR_VXSQRT PPC_BIT_NR(54) /* Floating-point invalid op. excp (sqrt)*/
848 #define FPSCR_VXCVI PPC_BIT_NR(55) /* Floating-point invalid op. excp (int) */
849 #define FPSCR_VE PPC_BIT_NR(56) /* Floating-point invalid op. excp enable*/
850 #define FPSCR_OE PPC_BIT_NR(57) /* Floating-point overflow excp. enable */
851 #define FPSCR_UE PPC_BIT_NR(58) /* Floating-point underflow excp. enable */
852 #define FPSCR_ZE PPC_BIT_NR(59) /* Floating-point zero divide excp enable*/
853 #define FPSCR_XE PPC_BIT_NR(60) /* Floating-point inexact excp. enable */
854 #define FPSCR_NI PPC_BIT_NR(61) /* Floating-point non-IEEE mode */
855 #define FPSCR_RN1 PPC_BIT_NR(62)
856 #define FPSCR_RN0 PPC_BIT_NR(63) /* Floating-point rounding control */
1189 FIELD(DEXCR, PNH_##name, PPC_BIT_NR(num), 1) \
1190 FIELD(DEXCR, PRO_##name, PPC_BIT_NR(num + 32), 1) \
1191 FIELD(HDEXCR, HNU_##name, PPC_BIT_NR(num), 1) \
1192 FIELD(HDEXCR, ENF_##name, PPC_BIT_NR(num + 32), 1) \