Lines Matching +full:se +full:- +full:neg
4 * Copyright (c) 2003-2007 Jocelyn Mayer
24 #include "qemu/cpu-float.h"
25 #include "exec/cpu-defs.h"
26 #include "cpu-qom.h"
41 #define PPC_BIT_NR(bit) (63 - (bit))
43 #define PPC_BIT32_NR(bit) (31 - (bit))
46 #define PPC_BITMASK(bs, be) ((PPC_BIT(bs) - PPC_BIT(be)) | PPC_BIT(bs))
47 #define PPC_BITMASK32(bs, be) ((PPC_BIT32(bs) - PPC_BIT32(be)) | \
49 #define PPC_BITMASK8(bs, be) ((PPC_BIT8(bs) - PPC_BIT8(be)) | PPC_BIT8(bs))
58 #define MASK_TO_LSH(m) (__builtin_ffsll(m) - 1)
66 POWERPC_EXCP_NONE = -1,
75 POWERPC_EXCP_FPU = 7, /* Floating-point unavailable exception */
79 POWERPC_EXCP_FIT = 11, /* Fixed-interval timer interrupt */
85 POWERPC_EXCP_SPEU = 32, /* SPE/embedded floating-point unavailable */
86 POWERPC_EXCP_EFPDI = 33, /* Embedded floating-point data interrupt */
87 POWERPC_EXCP_EFPRI = 34, /* Embedded floating-point round interrupt */
108 /* Vectors 75-76 are 601 specific exceptions */
116 POWERPC_EXCP_FPA = 81, /* Floating-point assist exception */
159 POWERPC_EXCP_ALIGN_LE = 0x03, /* Multiple little-endian access */
163 POWERPC_EXCP_ALIGN_INSN = 0x07, /* Pref. insn x-ing 64-byte boundary */
285 #define PPC_INPUT(env) ((env)->bus_model)
302 /* SPR access micro-ops generations callbacks */
403 #define SEGMENT_MASK_256M (~((1ULL << SEGMENT_SHIFT_256M) - 1))
406 #define SEGMENT_MASK_1T (~((1ULL << SEGMENT_SHIFT_1T) - 1))
425 #define MSR_SF PPC_BIT_NR(0) /* Sixty-four-bit mode hflags */
426 #define MSR_TAG PPC_BIT_NR(1) /* Tag-active mode (POWERx ?) */
427 #define MSR_ISF PPC_BIT_NR(2) /* Sixty-four-bit interrupt mode on 630 */
435 #define MSR_UCLE PPC_BIT_NR(37) /* User-mode cache lock enable for BookE */
445 #define MSR_ILE PPC_BIT_NR(47) /* Interrupt little-endian mode */
451 #define MSR_SE PPC_BIT_NR(53) /* Single-step trace enable x hflags */
467 #define MSR_LE PPC_BIT_NR(63) /* Little-endian mode 1 hflags */
501 FIELD(MSR, SE, MSR_SE, 1)
520 * FE0 and FE1 bits are not side-by-side
535 #define MMCR0_FC14 PPC_BIT(58) /* PMC Freeze Counters 1-4 bit */
536 #define MMCR0_FC56 PPC_BIT(59) /* PMC Freeze Counters 5-6 bit */
561 #define MMCR1_PMC1EVT_EXTR (64 - MMCR1_PMC1SEL_START - MMCR1_EVT_SIZE)
563 #define MMCR1_PMC2EVT_EXTR (64 - MMCR1_PMC2SEL_START - MMCR1_EVT_SIZE)
565 #define MMCR1_PMC3EVT_EXTR (64 - MMCR1_PMC3SEL_START - MMCR1_EVT_SIZE)
567 #define MMCR1_PMC4EVT_EXTR (64 - MMCR1_PMC4SEL_START - MMCR1_EVT_SIZE)
575 /* External Event-based Exception Enable */
577 /* Performance Monitor Event-based Exception Enable */
579 /* External Event-based Exception Occurred */
581 /* Performance Monitor Event-based Exception Occurred */
590 #define LPCR_DPFD_SHIFT (63 - 11)
592 #define LPCR_VRMASD_SHIFT (63 - 16)
594 /* P9: Power-saving mode Exit Cause Enable (Upper Section) Mask */
595 #define LPCR_PECE_U_SHIFT (63 - 19)
598 #define LPCR_RMLS_SHIFT (63 - 37) /* RMLS (removed in ISA v3.0) */
602 #define LPCR_AIL_SHIFT (63 - 40) /* Alternate interrupt location */
617 /* P9: Power-saving mode Exit Cause Enable (Lower Section) Mask */
618 #define LPCR_PECE_L_SHIFT (63 - 51)
672 /* Not permitted due to no-execute or guard bit set */
688 #define SRR1_WAKESCOM 0x00080000 /* SCOM not in power-saving mode */
690 /* SRR1[46:47] power-saving exit mode */
699 #define FSCR_EBB (63 - 56) /* Event-Based Branch Facility */
700 #define FSCR_TAR (63 - 55) /* Target Address Register */
701 #define FSCR_SCV (63 - 51) /* System call vectored */
704 #define FSCR_IC_POS (63 - 7)
717 #define ESR_FP PPC_BIT(39) /* Floating-Point Operation */
732 #define TEXASR_FAILURE_PERSISTENT (63 - 7)
733 #define TEXASR_DISALLOWED (63 - 8)
734 #define TEXASR_NESTING_OVERFLOW (63 - 9)
735 #define TEXASR_FOOTPRINT_OVERFLOW (63 - 10)
736 #define TEXASR_SELF_INDUCED_CONFLICT (63 - 11)
737 #define TEXASR_NON_TRANSACTIONAL_CONFLICT (63 - 12)
738 #define TEXASR_TRANSACTION_CONFLICT (63 - 13)
739 #define TEXASR_TRANSLATION_INVALIDATION_CONFLICT (63 - 14)
740 #define TEXASR_IMPLEMENTATION_SPECIFIC (63 - 15)
741 #define TEXASR_INSTRUCTION_FETCH_CONFLICT (63 - 16)
742 #define TEXASR_ABORT (63 - 31)
743 #define TEXASR_SUSPENDED (63 - 32)
744 #define TEXASR_PRIVILEGE_HV (63 - 34)
745 #define TEXASR_PRIVILEGE_PR (63 - 35)
746 #define TEXASR_FAILURE_SUMMARY (63 - 36)
747 #define TEXASR_TFIAR_EXACT (63 - 37)
748 #define TEXASR_ROT (63 - 38)
749 #define TEXASR_TRANSACTION_LEVEL (63 - 52) /* 12 bits */
759 /* Flag for MSR bit 10 signification (SE/DWE/UBLE) */
782 /* Using "LPAR per core" mode (as opposed to per-thread) */
789 * Bits for env->hflags.
804 HFLAGS_BE = 9, /* MSR_BE -- from elsewhere on embedded ppc */
805 HFLAGS_SE = 10, /* MSR_SE -- from elsewhere on embedded ppc */
811 HFLAGS_PMC_OTHER = 18, /* PMC other than PMC5-6 is enabled */
817 HFLAGS_IMMU_IDX = 26, /* 26..28 -- the composite immu_idx */
818 HFLAGS_DMMU_IDX = 29, /* 29..31 -- the composite dmmu_idx */
823 #define FPSCR_DRN2 PPC_BIT_NR(29) /* Decimal Floating-Point rounding ctrl. */
824 #define FPSCR_DRN1 PPC_BIT_NR(30) /* Decimal Floating-Point rounding ctrl. */
825 #define FPSCR_DRN0 PPC_BIT_NR(31) /* Decimal Floating-Point rounding ctrl. */
826 #define FPSCR_FX PPC_BIT_NR(32) /* Floating-point exception summary */
827 #define FPSCR_FEX PPC_BIT_NR(33) /* Floating-point enabled exception summ.*/
828 #define FPSCR_VX PPC_BIT_NR(34) /* Floating-point invalid op. excp. summ.*/
829 #define FPSCR_OX PPC_BIT_NR(35) /* Floating-point overflow exception */
830 #define FPSCR_UX PPC_BIT_NR(36) /* Floating-point underflow exception */
831 #define FPSCR_ZX PPC_BIT_NR(37) /* Floating-point zero divide exception */
832 #define FPSCR_XX PPC_BIT_NR(38) /* Floating-point inexact exception */
833 #define FPSCR_VXSNAN PPC_BIT_NR(39) /* Floating-point invalid op. excp (sNan)*/
834 #define FPSCR_VXISI PPC_BIT_NR(40) /* Floating-point invalid op. excp (inf) */
835 #define FPSCR_VXIDI PPC_BIT_NR(41) /* Floating-point invalid op. excp (inf) */
836 #define FPSCR_VXZDZ PPC_BIT_NR(42) /* Floating-point invalid op. excp (zero)*/
837 #define FPSCR_VXIMZ PPC_BIT_NR(43) /* Floating-point invalid op. excp (inf) */
838 #define FPSCR_VXVC PPC_BIT_NR(44) /* Floating-point invalid op. excp (comp)*/
839 #define FPSCR_FR PPC_BIT_NR(45) /* Floating-point fraction rounded */
840 #define FPSCR_FI PPC_BIT_NR(46) /* Floating-point fraction inexact */
841 #define FPSCR_C PPC_BIT_NR(47) /* Floating-point result class descriptor*/
842 #define FPSCR_FL PPC_BIT_NR(48) /* Floating-point less than or negative */
843 #define FPSCR_FG PPC_BIT_NR(49) /* Floating-point greater than or neg. */
844 #define FPSCR_FE PPC_BIT_NR(50) /* Floating-point equal or zero */
845 #define FPSCR_FU PPC_BIT_NR(51) /* Floating-point unordered or NaN */
846 #define FPSCR_FPCC PPC_BIT_NR(51) /* Floating-point condition code */
847 #define FPSCR_FPRF PPC_BIT_NR(51) /* Floating-point result flags */
848 #define FPSCR_VXSOFT PPC_BIT_NR(53) /* Floating-point invalid op. excp (soft)*/
849 #define FPSCR_VXSQRT PPC_BIT_NR(54) /* Floating-point invalid op. excp (sqrt)*/
850 #define FPSCR_VXCVI PPC_BIT_NR(55) /* Floating-point invalid op. excp (int) */
851 #define FPSCR_VE PPC_BIT_NR(56) /* Floating-point invalid op. excp enable*/
852 #define FPSCR_OE PPC_BIT_NR(57) /* Floating-point overflow excp. enable */
853 #define FPSCR_UE PPC_BIT_NR(58) /* Floating-point underflow excp. enable */
854 #define FPSCR_ZE PPC_BIT_NR(59) /* Floating-point zero divide excp enable*/
855 #define FPSCR_XE PPC_BIT_NR(60) /* Floating-point inexact excp. enable */
856 #define FPSCR_NI PPC_BIT_NR(61) /* Floating-point non-IEEE mode */
858 #define FPSCR_RN0 PPC_BIT_NR(63) /* Floating-point rounding control */
910 /* the exception bits which can be cleared by mcrfs - includes FX */
922 #define VSCR_NJ 16 /* Vector non-java */
1246 /* used to speed-up TLB assist handlers */
1271 int tlb_per_way; /* Speed-up helper: used to avoid divisions at run time */
1278 bool tlb_dirty; /* Set to non-zero when modifying TLB */
1279 bool kvm_sw_tlb; /* non-zero if KVM SW TLB API is active */
1289 /* Composite status for PMC[1-6] enabled and counting insns or cycles. */
1296 /* Non-zero if and only if VSCR_SAT should be set */
1380 * exception on a transition from 0 to 1 (watchdog or fixed-interval timer)
1416 if ((POWERPC_CPU(cs)->env.chip_index == \
1417 POWERPC_CPU(cs_sibling)->env.chip_index) && \
1418 (POWERPC_CPU(cs)->env.core_index == \
1419 POWERPC_CPU(cs_sibling)->env.core_index))
1423 env->fit_period[0] = (a_); \
1424 env->fit_period[1] = (b_); \
1425 env->fit_period[2] = (c_); \
1426 env->fit_period[3] = (d_); \
1431 env->wdt_period[0] = (a_); \
1432 env->wdt_period[1] = (b_); \
1433 env->wdt_period[2] = (c_); \
1434 env->wdt_period[3] = (d_); \
1495 uint64_t lpcr_pm; /* Power-saving mode Exit Cause Enable bits */
1516 return !POWERPC_CPU(cs)->env.has_smt_siblings; in ppc_cpu_core_single_threaded()
1521 return !(POWERPC_CPU(cs)->env.flags & POWERPC_FLAG_SMT_1LPAR) || in ppc_cpu_lpar_single_threaded()
1551 #define TYPE_PPC_VIRTUAL_HYPERVISOR "ppc-virtual-hypervisor"
1557 return cpu->vhyp_class->cpu_in_nested(cpu); in DECLARE_OBJ_CHECKERS()
1598 /* Time-base and decrementer management */
1642 gprv = env->gpr[gprn]; in ppc_dump_gpr()
1643 if (env->flags & POWERPC_FLAG_SPE) { in ppc_dump_gpr()
1649 gprv |= (uint64_t)env->gprh[gprn] << 32; in ppc_dump_gpr()
1668 return (env->hflags >> (ifetch ? HFLAGS_IMMU_IDX : HFLAGS_DMMU_IDX)) & 7; in ppc_env_mmu_index()
1690 #include "exec/cpu-all.h"
1716 #define xer_so (env->so)
1717 #define xer_cmp ((env->xer >> XER_CMP) & 0xFF)
1718 #define xer_bc ((env->xer >> XER_BC) & 0x7F)
2297 #define L1CSR0_CUL 0x00000400 /* (D-)Cache Unable to Lock */
2298 #define L1CSR0_DCLFR 0x00000100 /* D-Cache Lock Flash Reset */
2303 #define L1CSR1_ICUL 0x00000400 /* I-Cache Unable to Lock */
2304 #define L1CSR1_ICLFR 0x00000100 /* I-Cache Lock Flash Reset */
2314 #define HID0_DEEPNAP (1 << 24) /* pre-2.06 */
2315 #define HID0_DOZE (1 << 23) /* pre-2.06 */
2316 #define HID0_NAP (1 << 22) /* pre-2.06 */
2349 /* Fixed-point unit extensions */
2359 /* Floating-point unit extensions */
2362 /* New floating-point extensions (PowerPC 2.0x) */
2376 /* PowerPC 2.03 SPE single-precision floating-point extension */
2378 /* PowerPC 2.03 SPE double-precision floating-point extension */
2479 /* Byte-reversed, indexed, double-word load and store */
2667 PPC_INTERRUPT_EBB = 0x80000, /* Event-based Branch exception */
2730 #define is_isa300(ctx) (!!(ctx->insns_flags2 & PPC2_ISA300))
2735 * All 64-bit server processors compliant with arch 2.x, ie. 970 and newer,
2738 #define is_book3s_arch2x(ctx) (!!((ctx)->insns_flags & PPC_SEGMENT_64B))
2747 *pc = env->nip; in cpu_get_tb_cpu_state()
2749 *flags = env->hflags; in cpu_get_tb_cpu_state()
2770 uintptr_t tlbl = (uintptr_t)env->tlb.tlbm; in booke206_tlbm_id()
2772 return (tlbml - tlbl) / sizeof(env->tlb.tlbm[0]); in booke206_tlbm_id()
2777 uint32_t tlbncfg = env->spr[SPR_BOOKE_TLB0CFG + tlbn]; in booke206_tlb_size()
2784 uint32_t tlbncfg = env->spr[SPR_BOOKE_TLB0CFG + tlbn]; in booke206_tlb_ways()
2810 return tlbid & (booke206_tlb_ways(env, tlbn) - 1); in booke206_tlbm_to_way()
2822 way &= ways - 1; in booke206_get_tlbm()
2824 ea &= (1 << (tlb_bits - ways_bits)) - 1; in booke206_get_tlbm()
2836 return &env->tlb.tlbm[r]; in booke206_get_tlbm()
2844 if ((env->spr[SPR_MMUCFG] & MMUCFG_MAVN) == MMUCFG_MAVN_V2) { in booke206_tlbnps()
2846 ret = env->spr[SPR_BOOKE_TLB0PS + tlbn]; in booke206_tlbnps()
2848 uint32_t tlbncfg = env->spr[SPR_BOOKE_TLB0CFG + tlbn]; in booke206_tlbnps()
2864 int32_t tsize = -1; in booke206_fixed_size_tlbn()
2867 if ((env->spr[SPR_BOOKE_TLB0PS + tlbn]) & (1ULL << i)) { in booke206_fixed_size_tlbn()
2868 if (tsize == -1) { in booke206_fixed_size_tlbn()
2877 assert(tsize != -1); in booke206_fixed_size_tlbn()
2878 tlb->mas1 &= ~MAS1_TSIZE_MASK; in booke206_fixed_size_tlbn()
2879 tlb->mas1 |= ((uint32_t)tsize) << MAS1_TSIZE_SHIFT; in booke206_fixed_size_tlbn()
2884 return cpu->env.tlb_type == TLB_6XX; in ppc_is_split_tlb()
2890 if (env->mmu_model == POWERPC_MMU_BOOKE206) { in msr_is_64bit()
2904 (start + nregs > 32 && (rx >= start || rx < start + nregs - 32)); in lsw_reg_in_range()
2921 #define VsrB(i) u8[15 - (i)]
2922 #define VsrSB(i) s8[15 - (i)]
2923 #define VsrH(i) u16[7 - (i)]
2924 #define VsrSH(i) s16[7 - (i)]
2925 #define VsrW(i) u32[3 - (i)]
2926 #define VsrSW(i) s32[3 - (i)]
2927 #define VsrD(i) u64[1 - (i)]
2928 #define VsrSD(i) s64[1 - (i)]
2929 #define VsrHF(i) f16[7 - (i)]
2930 #define VsrSF(i) f32[3 - (i)]
2931 #define VsrDF(i) f64[1 - (i)]
2982 return cpu->env.spr_cb[spr].name != NULL; in ppc_has_spr()
2990 CPUPPCState *env = &cpu->env; in ppc_interrupts_little_endian()
2993 if (hv && env->has_hv_mode) { in ppc_interrupts_little_endian()
2995 ile = !!(env->spr[SPR_HID0] & HID0_POWER9_HILE); in ppc_interrupts_little_endian()
2997 ile = !!(env->spr[SPR_HID0] & HID0_HILE); in ppc_interrupts_little_endian()
3000 } else if (pcc->lpcr_mask & LPCR_ILE) { in ppc_interrupts_little_endian()
3001 ile = !!(env->spr[SPR_LPCR] & LPCR_ILE); in ppc_interrupts_little_endian()
3003 ile = FIELD_EX64(env->msr, MSR, ILE); in ppc_interrupts_little_endian()
3045 .name = stringify(_name) "-family-" TYPE_POWERPC_CPU, \