Lines Matching +full:tcs +full:- +full:offset
2 * MIPS emulation for QEMU - main translation routines
4 * Copyright (c) 2004-2005 Jocelyn Mayer
9 * Copyright (c) 2020 Philippe Mathieu-Daudé
28 #include "exec/helper-proto.h"
29 #include "exec/translation-block.h"
36 #include "exec/helper-info.c.inc"
41 * Many system-only helpers are not reachable for user-only.
153 /* PC-relative address computation / loads */
157 /* PC-relative address computation / loads */
369 /* MIPS DSP GPR-Based Shift Sub-class */
372 /* MIPS DSP Multiply Sub-class insns */
376 /* DSP Bit/Manipulation Sub-class */
379 /* MIPS DSP Append Sub-class */
382 /* MIPS DSP Accumulator and DSPControl Access Sub-class */
503 /* MIPS DSP Arithmetic Sub-class */
522 /* MIPS DSP Multiply Sub-class insns */
533 /* MIPS DSP Arithmetic Sub-class */
546 /* MIPS DSP Multiply Sub-class insns */
555 /* MIPS DSP Arithmetic Sub-class */
569 /* DSP Bit/Manipulation Sub-class */
579 /* MIPS DSP Arithmetic Sub-class */
587 /* DSP Compare-Pick Sub-class */
607 /* MIPS DSP GPR-Based Shift Sub-class */
634 /* MIPS DSP Multiply Sub-class insns */
661 /* DSP Bit/Manipulation Sub-class */
667 /* MIPS DSP Append Sub-class */
675 /* MIPS DSP Accumulator and DSPControl Access Sub-class */
697 /* MIPS DSP Arithmetic Sub-class */
715 /* DSP Bit/Manipulation Sub-class */
726 /* MIPS DSP Multiply Sub-class insns */
732 /* MIPS DSP Arithmetic Sub-class */
758 /* DSP Compare-Pick Sub-class */
778 /* MIPS DSP Arithmetic Sub-class */
791 /* DSP Append Sub-class */
800 /* MIPS DSP Accumulator and DSPControl Access Sub-class */
826 /* DSP Bit/Manipulation Sub-class */
832 /* MIPS DSP Multiply Sub-class insns */
863 /* MIPS DSP GPR-Based Shift Sub-class */
1111 * +--------+----------------------------------------+
1113 * +--------+----------------------------------------+
1118 * -------+-------+-------+-------+-------+-------+-------+-------+-------
1138 * +--------+-------------------------------+--------+
1140 * +--------+-------------------------------+--------+
1145 * -------+-------+-------+-------+-------+-------+-------+-------+-------
1171 * For CPUs using 128-bit GPR registers, we put the lower halves in cpu_gpr[])
1280 LOG_DISAS("hflags %08x saved %08x\n", ctx->hflags, ctx->saved_hflags); in save_cpu_state()
1281 if (do_save_pc && ctx->base.pc_next != ctx->saved_pc) { in save_cpu_state()
1282 gen_save_pc(ctx->base.pc_next); in save_cpu_state()
1283 ctx->saved_pc = ctx->base.pc_next; in save_cpu_state()
1285 if (ctx->hflags != ctx->saved_hflags) { in save_cpu_state()
1286 tcg_gen_movi_i32(hflags, ctx->hflags); in save_cpu_state()
1287 ctx->saved_hflags = ctx->hflags; in save_cpu_state()
1288 switch (ctx->hflags & MIPS_HFLAG_BMASK_BASE) { in save_cpu_state()
1294 tcg_gen_movi_tl(btarget, ctx->btarget); in save_cpu_state()
1302 ctx->saved_hflags = ctx->hflags; in restore_cpu_state()
1303 switch (ctx->hflags & MIPS_HFLAG_BMASK_BASE) { in restore_cpu_state()
1309 ctx->btarget = env->btarget; in restore_cpu_state()
1319 ctx->base.is_jmp = DISAS_NORETURN; in generate_exception_err()
1350 if (ctx->hflags & MIPS_HFLAG_FRE) { in gen_load_fpr32()
1359 if (ctx->hflags & MIPS_HFLAG_FRE) { in gen_store_fpr32()
1369 if (ctx->hflags & MIPS_HFLAG_F64) { in gen_load_fpr32h()
1378 if (ctx->hflags & MIPS_HFLAG_F64) { in gen_store_fpr32h()
1389 if (ctx->hflags & MIPS_HFLAG_F64) { in gen_load_fpr64()
1398 if (ctx->hflags & MIPS_HFLAG_F64) { in gen_store_fpr64()
1424 if (ctx->hflags & MIPS_HFLAG_AWRAP) { in gen_op_addr_add()
1435 if (ctx->hflags & MIPS_HFLAG_AWRAP) { in gen_op_addr_addi()
1443 target_long offset) in addr_add() argument
1445 target_long sum = base + offset; in addr_add()
1448 if (ctx->hflags & MIPS_HFLAG_AWRAP) { in addr_add()
1455 /* Sign-extract the low 32-bits to a target_long. */
1465 /* Sign-extract the high 32-bits to a target_long. */
1477 if (unlikely(!(ctx->hflags & MIPS_HFLAG_CP0))) { in check_cp0_enabled()
1486 if (unlikely(!(ctx->hflags & MIPS_HFLAG_FPU))) { in check_cp1_enabled()
1498 if (unlikely(!(ctx->hflags & MIPS_HFLAG_COP1X))) { in check_cop1x()
1504 * Verify that the processor is running with 64-bit floating-point
1509 if (unlikely(~ctx->hflags & MIPS_HFLAG_F64)) { in check_cp1_64bitmode()
1518 * even-odd pair of adjacent coprocessor general registers. When the FR bit
1527 if (unlikely(!(ctx->hflags & MIPS_HFLAG_F64) && (regs & 1))) { in check_cp1_registers()
1538 if (unlikely(!(ctx->hflags & MIPS_HFLAG_DSP))) { in check_dsp()
1539 if (ctx->insn_flags & ASE_DSP) { in check_dsp()
1549 if (unlikely(!(ctx->hflags & MIPS_HFLAG_DSP_R2))) { in check_dsp_r2()
1550 if (ctx->insn_flags & ASE_DSP) { in check_dsp_r2()
1560 if (unlikely(!(ctx->hflags & MIPS_HFLAG_DSP_R3))) { in check_dsp_r3()
1561 if (ctx->insn_flags & ASE_DSP) { in check_dsp_r3()
1575 if (unlikely(!(ctx->insn_flags & flags))) { in check_insn()
1587 if (unlikely(ctx->insn_flags & flags)) { in check_insn_opc_removed()
1609 * CPU does not support 64-bit paired-single (PS) floating point data type.
1613 if (unlikely(!ctx->ps)) { in check_ps()
1621 return ctx->hflags & MIPS_HFLAG_64; in decode_64bit_enabled()
1626 * 64-bit or 64-bit instructions are not enabled.
1638 if (unlikely(!ctx->mvh)) { in check_mvh()
1650 if (unlikely(ctx->CP0_Config5 & (1 << CP0C5_XNP))) { in check_xnp()
1662 if (unlikely(!(ctx->CP0_Config3 & (1 << CP0C3_PW)))) { in check_pw()
1674 if (unlikely(!(ctx->CP0_Config3 & (1 << CP0C3_MT)))) { in check_mt()
1688 if (unlikely(!(ctx->hflags & MIPS_HFLAG_CP0))) { in check_cp0_mt()
1691 if (unlikely(!(ctx->CP0_Config3 & (1 << CP0C3_MT)))) { in check_cp0_mt()
1704 if (unlikely(ctx->CP0_Config5 & (1 << CP0C5_NMS))) { in check_nms()
1716 if (unlikely((ctx->CP0_Config5 & (1 << CP0C5_NMS)) && in check_nms_dl_il_sl_tl_l2c()
1717 !(ctx->CP0_Config1 & (1 << CP0C1_DL)) && in check_nms_dl_il_sl_tl_l2c()
1718 !(ctx->CP0_Config1 & (1 << CP0C1_IL)) && in check_nms_dl_il_sl_tl_l2c()
1719 !(ctx->CP0_Config2 & (1 << CP0C2_SL)) && in check_nms_dl_il_sl_tl_l2c()
1720 !(ctx->CP0_Config2 & (1 << CP0C2_TL)) && in check_nms_dl_il_sl_tl_l2c()
1721 !(ctx->CP0_Config5 & (1 << CP0C5_L2C)))) { in check_nms_dl_il_sl_tl_l2c()
1732 if (unlikely(!(ctx->CP0_Config5 & (1 << CP0C5_EVA)))) { in check_eva()
1740 * calling interface for 32 and 64-bit FPRs. No sense in changing
1930 tcg_gen_qemu_ld_tl(ret, arg1, ctx->mem_idx, memop); \
1948 void gen_base_offset_addr(DisasContext *ctx, TCGv addr, int base, int offset) in gen_base_offset_addr() argument
1951 tcg_gen_movi_tl(addr, offset); in gen_base_offset_addr()
1952 } else if (offset == 0) { in gen_base_offset_addr()
1955 tcg_gen_movi_tl(addr, offset); in gen_base_offset_addr()
1973 target_ulong pc = ctx->base.pc_next; in pc_relative_pc()
1975 if (ctx->hflags & MIPS_HFLAG_BMASK) { in pc_relative_pc()
1976 int branch_bytes = ctx->hflags & MIPS_HFLAG_BDS16 ? 2 : 4; in pc_relative_pc()
1978 pc -= branch_bytes; in pc_relative_pc()
1989 int sizem1 = memop_size(mop) - 1; in gen_lxl()
2006 tcg_gen_shl_tl(t1, tcg_constant_tl(-1), t1); in gen_lxl()
2016 int sizem1 = size - 1; in gen_lxr()
2033 tcg_gen_xori_tl(t1, t1, size * 8 - 1); in gen_lxr()
2044 tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, mo_endian(ctx) | mop); in gen_lx()
2050 int rt, int base, int offset) in gen_ld() argument
2053 int mem_idx = ctx->mem_idx; in gen_ld()
2055 if (rt == 0 && ctx->insn_flags & (INSN_LOONGSON2E | INSN_LOONGSON2F | in gen_ld()
2066 gen_base_offset_addr(ctx, t0, base, offset); in gen_ld()
2072 ctx->default_tcg_memop_mask); in gen_ld()
2077 ctx->default_tcg_memop_mask); in gen_ld()
2115 ctx->default_tcg_memop_mask); in gen_ld()
2123 ctx->default_tcg_memop_mask); in gen_ld()
2131 ctx->default_tcg_memop_mask); in gen_ld()
2181 int base, int offset) in gen_st() argument
2185 int mem_idx = ctx->mem_idx; in gen_st()
2187 gen_base_offset_addr(ctx, t0, base, offset); in gen_st()
2193 ctx->default_tcg_memop_mask); in gen_st()
2207 ctx->default_tcg_memop_mask); in gen_st()
2214 ctx->default_tcg_memop_mask); in gen_st()
2239 static void gen_st_cond(DisasContext *ctx, int rt, int base, int offset, in gen_st_cond() argument
2249 gen_base_offset_addr(ctx, addr, base, offset); in gen_st_cond()
2259 eva ? MIPS_HFLAG_UM : ctx->mem_idx, tcg_mo); in gen_st_cond()
2278 tcg_gen_qemu_ld_i32(fp0, t0, ctx->mem_idx, mo_endian(ctx) | MO_SL | in gen_flt_ldst()
2279 ctx->default_tcg_memop_mask); in gen_flt_ldst()
2287 tcg_gen_qemu_st_i32(fp0, t0, ctx->mem_idx, mo_endian(ctx) | MO_UL | in gen_flt_ldst()
2288 ctx->default_tcg_memop_mask); in gen_flt_ldst()
2294 tcg_gen_qemu_ld_i64(fp0, t0, ctx->mem_idx, mo_endian(ctx) | MO_UQ | in gen_flt_ldst()
2295 ctx->default_tcg_memop_mask); in gen_flt_ldst()
2303 tcg_gen_qemu_st_i64(fp0, t0, ctx->mem_idx, mo_endian(ctx) | MO_UQ | in gen_flt_ldst()
2304 ctx->default_tcg_memop_mask); in gen_flt_ldst()
2319 if (ctx->CP0_Config1 & (1 << CP0C1_FP)) { in gen_cop1_ldst()
2445 if (rs != 0 && (ctx->insn_flags & ISA_MIPS_R6)) { in gen_logic_imm()
2970 target_long offset; in gen_pcrel() local
2976 offset = sextract32(ctx->opcode << 2, 0, 21); in gen_pcrel()
2977 addr = addr_add(ctx, pc, offset); in gen_pcrel()
2982 offset = sextract32(ctx->opcode << 2, 0, 21); in gen_pcrel()
2983 addr = addr_add(ctx, pc, offset); in gen_pcrel()
2984 gen_r6_ld(addr, rs, ctx->mem_idx, mo_endian(ctx) | MO_SL); in gen_pcrel()
2989 offset = sextract32(ctx->opcode << 2, 0, 21); in gen_pcrel()
2990 addr = addr_add(ctx, pc, offset); in gen_pcrel()
2991 gen_r6_ld(addr, rs, ctx->mem_idx, mo_endian(ctx) | MO_UL); in gen_pcrel()
2998 offset = sextract32(ctx->opcode, 0, 16) << 16; in gen_pcrel()
2999 addr = addr_add(ctx, pc, offset); in gen_pcrel()
3005 offset = sextract32(ctx->opcode, 0, 16) << 16; in gen_pcrel()
3006 addr = ~0xFFFF & addr_add(ctx, pc, offset); in gen_pcrel()
3016 offset = sextract32(ctx->opcode << 3, 0, 21); in gen_pcrel()
3017 addr = addr_add(ctx, (pc & ~0x7), offset); in gen_pcrel()
3018 gen_r6_ld(addr, rs, ctx->mem_idx, mo_endian(ctx) | MO_UQ); in gen_pcrel()
3053 tcg_gen_setcondi_tl(TCG_COND_EQ, t3, t1, -1); in gen_r6_muldiv()
3069 tcg_gen_setcondi_tl(TCG_COND_EQ, t3, t1, -1); in gen_r6_muldiv()
3143 tcg_gen_setcondi_tl(TCG_COND_EQ, t2, t0, -1LL << 63); in gen_r6_muldiv()
3144 tcg_gen_setcondi_tl(TCG_COND_EQ, t3, t1, -1LL); in gen_r6_muldiv()
3156 tcg_gen_setcondi_tl(TCG_COND_EQ, t2, t0, -1LL << 63); in gen_r6_muldiv()
3157 tcg_gen_setcondi_tl(TCG_COND_EQ, t3, t1, -1LL); in gen_r6_muldiv()
3224 tcg_gen_setcondi_tl(TCG_COND_EQ, t3, t1, -1); in gen_div1_tx79()
3279 tcg_gen_setcondi_tl(TCG_COND_EQ, t3, t1, -1); in gen_muldiv()
3330 tcg_gen_setcondi_tl(TCG_COND_EQ, t2, t0, -1LL << 63); in gen_muldiv()
3331 tcg_gen_setcondi_tl(TCG_COND_EQ, t3, t1, -1LL); in gen_muldiv()
3425 * architectures are special three-operand variants with the syntax
3431 * (rd, LO, HI) <- rs * rt
3439 * (rd, LO, HI) <- (LO, HI) + rs * rt
3441 * where the low-order 32-bits of the result is placed into both the
3442 * GPR rd and the special register LO. The high-order 32-bits of the
3572 tcg_gen_subi_tl(t0, t0, TARGET_LONG_BITS - 32); in gen_cl()
3592 opc = MASK_LMMI(ctx->opcode); in gen_loongson_multimedia()
3829 tcg_gen_andi_i64(t1, t1, shift_max - 1); in gen_loongson_multimedia()
3839 * Since SRA is UndefinedResult without sign-extended inputs, in gen_loongson_multimedia()
3845 /* We want to shift in zeros for SRL; zero-extend first. */ in gen_loongson_multimedia()
3930 int cc = (ctx->opcode >> 8) & 0x7; in gen_loongson_multimedia()
3955 int lsq_rt1 = ctx->opcode & 0x1f; in gen_loongson_lswc2()
3956 int lsq_offset = sextract32(ctx->opcode, 6, 9) << 4; in gen_loongson_lswc2()
3958 int shf_offset = sextract32(ctx->opcode, 6, 8); in gen_loongson_lswc2()
3962 switch (MASK_LOONGSON_GSLSQ(ctx->opcode)) { in gen_loongson_lswc2()
3967 tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, mo_endian(ctx) | MO_UQ | in gen_loongson_lswc2()
3968 ctx->default_tcg_memop_mask); in gen_loongson_lswc2()
3970 tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, mo_endian(ctx) | MO_UQ | in gen_loongson_lswc2()
3971 ctx->default_tcg_memop_mask); in gen_loongson_lswc2()
3979 tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, mo_endian(ctx) | MO_UQ | in gen_loongson_lswc2()
3980 ctx->default_tcg_memop_mask); in gen_loongson_lswc2()
3982 tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, mo_endian(ctx) | MO_UQ | in gen_loongson_lswc2()
3983 ctx->default_tcg_memop_mask); in gen_loongson_lswc2()
3991 tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, mo_endian(ctx) | MO_UQ | in gen_loongson_lswc2()
3992 ctx->default_tcg_memop_mask); in gen_loongson_lswc2()
3995 tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, mo_endian(ctx) | MO_UQ | in gen_loongson_lswc2()
3996 ctx->default_tcg_memop_mask); in gen_loongson_lswc2()
4003 tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, mo_endian(ctx) | MO_UQ | in gen_loongson_lswc2()
4004 ctx->default_tcg_memop_mask); in gen_loongson_lswc2()
4007 tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, mo_endian(ctx) | MO_UQ | in gen_loongson_lswc2()
4008 ctx->default_tcg_memop_mask); in gen_loongson_lswc2()
4012 switch (MASK_LOONGSON_GSSHFLS(ctx->opcode)) { in gen_loongson_lswc2()
4020 gen_lxl(ctx, t1, t0, ctx->mem_idx, mo_endian(ctx) | MO_UL); in gen_loongson_lswc2()
4031 gen_lxr(ctx, t1, t0, ctx->mem_idx, mo_endian(ctx) | MO_UL); in gen_loongson_lswc2()
4041 gen_lxl(ctx, t1, t0, ctx->mem_idx, mo_endian(ctx) | MO_UQ); in gen_loongson_lswc2()
4049 gen_lxr(ctx, t1, t0, ctx->mem_idx, mo_endian(ctx) | MO_UQ); in gen_loongson_lswc2()
4060 switch (MASK_LOONGSON_GSSHFLS(ctx->opcode)) { in gen_loongson_lswc2()
4068 gen_helper_0e2i(swl, t1, t0, ctx->mem_idx); in gen_loongson_lswc2()
4077 gen_helper_0e2i(swr, t1, t0, ctx->mem_idx); in gen_loongson_lswc2()
4085 gen_helper_0e2i(sdl, t1, t0, ctx->mem_idx); in gen_loongson_lswc2()
4092 gen_helper_0e2i(sdr, t1, t0, ctx->mem_idx); in gen_loongson_lswc2()
4112 int offset = sextract32(ctx->opcode, 3, 8); in gen_loongson_lsdc2() local
4113 uint32_t opc = MASK_LOONGSON_LSDC2(ctx->opcode); in gen_loongson_lsdc2()
4117 /* Pre-conditions */ in gen_loongson_lsdc2()
4158 gen_base_offset_addr(ctx, t0, rs, offset); in gen_loongson_lsdc2()
4163 tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_SB); in gen_loongson_lsdc2()
4167 tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, mo_endian(ctx) | MO_SW | in gen_loongson_lsdc2()
4168 ctx->default_tcg_memop_mask); in gen_loongson_lsdc2()
4172 gen_base_offset_addr(ctx, t0, rs, offset); in gen_loongson_lsdc2()
4176 tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, mo_endian(ctx) | MO_SL | in gen_loongson_lsdc2()
4177 ctx->default_tcg_memop_mask); in gen_loongson_lsdc2()
4182 gen_base_offset_addr(ctx, t0, rs, offset); in gen_loongson_lsdc2()
4186 tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, mo_endian(ctx) | MO_UQ | in gen_loongson_lsdc2()
4187 ctx->default_tcg_memop_mask); in gen_loongson_lsdc2()
4192 gen_base_offset_addr(ctx, t0, rs, offset); in gen_loongson_lsdc2()
4197 tcg_gen_qemu_ld_i32(fp0, t0, ctx->mem_idx, mo_endian(ctx) | MO_SL | in gen_loongson_lsdc2()
4198 ctx->default_tcg_memop_mask); in gen_loongson_lsdc2()
4203 gen_base_offset_addr(ctx, t0, rs, offset); in gen_loongson_lsdc2()
4207 tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, mo_endian(ctx) | MO_UQ | in gen_loongson_lsdc2()
4208 ctx->default_tcg_memop_mask); in gen_loongson_lsdc2()
4215 tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_SB); in gen_loongson_lsdc2()
4220 tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, mo_endian(ctx) | MO_UW | in gen_loongson_lsdc2()
4221 ctx->default_tcg_memop_mask); in gen_loongson_lsdc2()
4226 tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, mo_endian(ctx) | MO_UL | in gen_loongson_lsdc2()
4227 ctx->default_tcg_memop_mask); in gen_loongson_lsdc2()
4233 tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, mo_endian(ctx) | MO_UQ | in gen_loongson_lsdc2()
4234 ctx->default_tcg_memop_mask); in gen_loongson_lsdc2()
4240 tcg_gen_qemu_st_i32(fp0, t0, ctx->mem_idx, mo_endian(ctx) | MO_UL | in gen_loongson_lsdc2()
4241 ctx->default_tcg_memop_mask); in gen_loongson_lsdc2()
4247 tcg_gen_qemu_st_i64(t1, t0, ctx->mem_idx, mo_endian(ctx) | MO_UQ | in gen_loongson_lsdc2()
4248 ctx->default_tcg_memop_mask); in gen_loongson_lsdc2()
4354 if (ctx->base.pc_next != ctx->saved_pc) { in gen_trap()
4355 gen_save_pc(ctx->base.pc_next); in gen_trap()
4357 if (ctx->hflags != ctx->saved_hflags) { in gen_trap()
4358 tcg_gen_movi_i32(hflags, ctx->hflags); in gen_trap()
4367 if (translator_use_goto_tb(&ctx->base, dest)) { in gen_goto_tb()
4370 tcg_gen_exit_tb(ctx->base.tb, n); in gen_goto_tb()
4380 int rs, int rt, int32_t offset, in gen_compute_branch() argument
4383 target_ulong btgt = -1; in gen_compute_branch()
4389 if (ctx->hflags & MIPS_HFLAG_BMASK) { in gen_compute_branch()
4392 VADDR_PRIx "\n", ctx->base.pc_next); in gen_compute_branch()
4410 btgt = ctx->base.pc_next + insn_bytes + offset; in gen_compute_branch()
4429 btgt = ctx->base.pc_next + insn_bytes + offset; in gen_compute_branch()
4439 btgt = ctx->base.pc_next + insn_bytes + offset; in gen_compute_branch()
4445 int jal_mask = ctx->hflags & MIPS_HFLAG_M16 ? 0xF8000000 in gen_compute_branch()
4447 btgt = ((ctx->base.pc_next + insn_bytes) & jal_mask) in gen_compute_branch()
4448 | (uint32_t)offset; in gen_compute_branch()
4453 btgt = ((ctx->base.pc_next + insn_bytes) & (int32_t)0xF0000000) | in gen_compute_branch()
4454 (uint32_t)offset; in gen_compute_branch()
4459 if (offset != 0 && offset != 16) { in gen_compute_branch()
4485 ctx->hflags |= MIPS_HFLAG_B; in gen_compute_branch()
4491 ctx->hflags |= MIPS_HFLAG_B; in gen_compute_branch()
4504 btgt = ctx->base.pc_next + insn_bytes + delayslot_size; in gen_compute_branch()
4505 ctx->hflags |= MIPS_HFLAG_B; in gen_compute_branch()
4508 tcg_gen_movi_tl(cpu_gpr[31], ctx->base.pc_next + 8); in gen_compute_branch()
4510 ctx->base.pc_next += 4; in gen_compute_branch()
4516 ctx->base.pc_next += 4; in gen_compute_branch()
4519 ctx->hflags |= MIPS_HFLAG_B; in gen_compute_branch()
4522 ctx->hflags |= MIPS_HFLAG_BX; in gen_compute_branch()
4526 ctx->hflags |= MIPS_HFLAG_B; in gen_compute_branch()
4529 ctx->hflags |= MIPS_HFLAG_BR; in gen_compute_branch()
4533 ctx->hflags |= MIPS_HFLAG_BR; in gen_compute_branch()
4598 ctx->hflags |= MIPS_HFLAG_BC; in gen_compute_branch()
4604 ctx->hflags |= MIPS_HFLAG_BL; in gen_compute_branch()
4613 ctx->btarget = btgt; in gen_compute_branch()
4617 ctx->hflags |= MIPS_HFLAG_BDS16; in gen_compute_branch()
4620 ctx->hflags |= MIPS_HFLAG_BDS32; in gen_compute_branch()
4626 int lowbit = !!(ctx->hflags & MIPS_HFLAG_M16); in gen_compute_branch()
4629 ctx->base.pc_next + post_delay + lowbit); in gen_compute_branch()
4634 ctx->hflags |= MIPS_HFLAG_B16; in gen_compute_branch()
4657 * so this is a simple sign-extension. in gen_bitops()
4682 tcg_gen_deposit_tl(t0, t0, t1, lsb, msb - lsb + 1); in gen_bitops()
4697 tcg_gen_deposit_tl(t0, t0, t1, lsb, msb - lsb + 1); in gen_bitops()
4810 tcg_gen_shri_i64(t2, t2, 32 - bits); in gen_align_bits()
4817 tcg_gen_shri_tl(t1, t1, 64 - bits); in gen_align_bits()
4938 CP0_CHECK(ctx->hflags & MIPS_HFLAG_ELPA); in gen_mfhc0()
4949 CP0_CHECK(ctx->hflags & MIPS_HFLAG_ELPA); in gen_mfhc0()
4961 ctx->CP0_LLAddr_shift); in gen_mfhc0()
4965 CP0_CHECK(ctx->mrp); in gen_mfhc0()
4984 CP0_CHECK(ctx->mi); in gen_mfhc0()
5020 uint64_t mask = ctx->PAMask >> 36; in gen_mthc0()
5026 CP0_CHECK(ctx->hflags & MIPS_HFLAG_ELPA); in gen_mthc0()
5038 CP0_CHECK(ctx->hflags & MIPS_HFLAG_ELPA); in gen_mthc0()
5051 * LLAddr is read-only (the only exception is bit 0 if LLB is in gen_mthc0()
5059 CP0_CHECK(ctx->mrp); in gen_mthc0()
5078 CP0_CHECK(ctx->mi); in gen_mthc0()
5113 if (ctx->insn_flags & ISA_MIPS_R6) { in gen_mfc0_unimplemented()
5151 CP0_CHECK(ctx->vp); in gen_mfc0()
5162 CP0_CHECK(!(ctx->insn_flags & ISA_MIPS_R6)); in gen_mfc0()
5213 if (ctx->rxi) { in gen_mfc0()
5270 if (ctx->rxi) { in gen_mfc0()
5281 CP0_CHECK(ctx->vp); in gen_mfc0()
5302 CP0_CHECK(ctx->ulri); in gen_mfc0()
5309 CP0_CHECK(ctx->mi); in gen_mfc0()
5329 CP0_CHECK(ctx->sc); in gen_mfc0()
5335 CP0_CHECK(ctx->sc); in gen_mfc0()
5341 CP0_CHECK(ctx->sc); in gen_mfc0()
5424 CP0_CHECK(ctx->bi); in gen_mfc0()
5429 CP0_CHECK(ctx->bp); in gen_mfc0()
5434 CP0_CHECK(ctx->bi); in gen_mfc0()
5447 translator_io_start(&ctx->base); in gen_mfc0()
5455 gen_save_pc(ctx->base.pc_next + 4); in gen_mfc0()
5456 ctx->base.is_jmp = DISAS_EXIT; in gen_mfc0()
5545 CP0_CHECK(ctx->cmgcr); in gen_mfc0()
5600 CP0_CHECK(ctx->mrp); in gen_mfc0()
5605 CP0_CHECK(ctx->mrp); in gen_mfc0()
5623 CP0_CHECK(ctx->CP0_Config1 & (1 << CP0C1_WR)); in gen_mfc0()
5641 CP0_CHECK(ctx->CP0_Config1 & (1 << CP0C1_WR)); in gen_mfc0()
5665 CP0_CHECK(!(ctx->insn_flags & ISA_MIPS_R6)); in gen_mfc0()
5852 CP0_CHECK(ctx->kscrexist & (1 << sel)); in gen_mfc0()
5854 offsetof(CPUMIPSState, CP0_KScratch[sel - 2])); in gen_mfc0()
5883 icount = translator_io_start(&ctx->base); in gen_mtc0()
5908 CP0_CHECK(ctx->vp); in gen_mtc0()
6015 CP0_CHECK(ctx->vp); in gen_mtc0()
6035 CP0_CHECK(ctx->ulri); in gen_mtc0()
6041 CP0_CHECK(ctx->mi); in gen_mtc0()
6059 ctx->base.is_jmp = DISAS_STOP; in gen_mtc0()
6062 CP0_CHECK(ctx->sc); in gen_mtc0()
6067 CP0_CHECK(ctx->sc); in gen_mtc0()
6072 CP0_CHECK(ctx->sc); in gen_mtc0()
6140 ctx->base.is_jmp = DISAS_STOP; in gen_mtc0()
6206 gen_save_pc(ctx->base.pc_next + 4); in gen_mtc0()
6207 ctx->base.is_jmp = DISAS_EXIT; in gen_mtc0()
6214 ctx->base.is_jmp = DISAS_STOP; in gen_mtc0()
6221 ctx->base.is_jmp = DISAS_STOP; in gen_mtc0()
6228 ctx->base.is_jmp = DISAS_STOP; in gen_mtc0()
6245 gen_save_pc(ctx->base.pc_next + 4); in gen_mtc0()
6246 ctx->base.is_jmp = DISAS_EXIT; in gen_mtc0()
6284 ctx->base.is_jmp = DISAS_STOP; in gen_mtc0()
6294 ctx->base.is_jmp = DISAS_STOP; in gen_mtc0()
6300 ctx->base.is_jmp = DISAS_STOP; in gen_mtc0()
6305 ctx->base.is_jmp = DISAS_STOP; in gen_mtc0()
6311 ctx->base.is_jmp = DISAS_STOP; in gen_mtc0()
6334 CP0_CHECK(ctx->mrp); in gen_mtc0()
6339 CP0_CHECK(ctx->mrp); in gen_mtc0()
6357 CP0_CHECK(ctx->CP0_Config1 & (1 << CP0C1_WR)); in gen_mtc0()
6375 CP0_CHECK(ctx->CP0_Config1 & (1 << CP0C1_WR)); in gen_mtc0()
6398 CP0_CHECK(!(ctx->insn_flags & ISA_MIPS_R6)); in gen_mtc0()
6417 gen_save_pc(ctx->base.pc_next + 4); in gen_mtc0()
6418 ctx->base.is_jmp = DISAS_EXIT; in gen_mtc0()
6426 ctx->base.is_jmp = DISAS_STOP; in gen_mtc0()
6433 ctx->base.is_jmp = DISAS_STOP; in gen_mtc0()
6437 ctx->base.is_jmp = DISAS_STOP; in gen_mtc0()
6442 ctx->base.is_jmp = DISAS_STOP; in gen_mtc0()
6448 ctx->base.is_jmp = DISAS_STOP; in gen_mtc0()
6455 ctx->base.is_jmp = DISAS_STOP; in gen_mtc0()
6515 ctx->base.is_jmp = DISAS_STOP; in gen_mtc0()
6596 CP0_CHECK(ctx->kscrexist & (1 << sel)); in gen_mtc0()
6598 offsetof(CPUMIPSState, CP0_KScratch[sel - 2])); in gen_mtc0()
6616 gen_save_pc(ctx->base.pc_next + 4); in gen_mtc0()
6617 ctx->base.is_jmp = DISAS_EXIT; in gen_mtc0()
6658 CP0_CHECK(ctx->vp); in gen_dmfc0()
6669 CP0_CHECK(!(ctx->insn_flags & ISA_MIPS_R6)); in gen_dmfc0()
6768 CP0_CHECK(ctx->vp); in gen_dmfc0()
6788 CP0_CHECK(ctx->ulri); in gen_dmfc0()
6794 CP0_CHECK(ctx->mi); in gen_dmfc0()
6814 CP0_CHECK(ctx->sc); in gen_dmfc0()
6819 CP0_CHECK(ctx->sc); in gen_dmfc0()
6824 CP0_CHECK(ctx->sc); in gen_dmfc0()
6905 CP0_CHECK(ctx->bi); in gen_dmfc0()
6910 CP0_CHECK(ctx->bp); in gen_dmfc0()
6915 CP0_CHECK(ctx->bi); in gen_dmfc0()
6928 translator_io_start(&ctx->base); in gen_dmfc0()
6935 gen_save_pc(ctx->base.pc_next + 4); in gen_dmfc0()
6936 ctx->base.is_jmp = DISAS_EXIT; in gen_dmfc0()
7022 CP0_CHECK(ctx->cmgcr); in gen_dmfc0()
7076 CP0_CHECK(ctx->mrp); in gen_dmfc0()
7081 CP0_CHECK(ctx->mrp); in gen_dmfc0()
7099 CP0_CHECK(ctx->CP0_Config1 & (1 << CP0C1_WR)); in gen_dmfc0()
7117 CP0_CHECK(ctx->CP0_Config1 & (1 << CP0C1_WR)); in gen_dmfc0()
7138 CP0_CHECK(!(ctx->insn_flags & ISA_MIPS_R6)); in gen_dmfc0()
7320 CP0_CHECK(ctx->kscrexist & (1 << sel)); in gen_dmfc0()
7322 offsetof(CPUMIPSState, CP0_KScratch[sel - 2])); in gen_dmfc0()
7350 icount = translator_io_start(&ctx->base); in gen_dmtc0()
7375 CP0_CHECK(ctx->vp); in gen_dmtc0()
7482 CP0_CHECK(ctx->vp); in gen_dmtc0()
7502 CP0_CHECK(ctx->ulri); in gen_dmtc0()
7508 CP0_CHECK(ctx->mi); in gen_dmtc0()
7528 CP0_CHECK(ctx->sc); in gen_dmtc0()
7533 CP0_CHECK(ctx->sc); in gen_dmtc0()
7538 CP0_CHECK(ctx->sc); in gen_dmtc0()
7606 ctx->base.is_jmp = DISAS_STOP; in gen_dmtc0()
7645 ctx->base.is_jmp = DISAS_STOP; in gen_dmtc0()
7668 ctx->base.is_jmp = DISAS_STOP; in gen_dmtc0()
7676 gen_save_pc(ctx->base.pc_next + 4); in gen_dmtc0()
7677 ctx->base.is_jmp = DISAS_EXIT; in gen_dmtc0()
7684 ctx->base.is_jmp = DISAS_STOP; in gen_dmtc0()
7691 ctx->base.is_jmp = DISAS_STOP; in gen_dmtc0()
7698 ctx->base.is_jmp = DISAS_STOP; in gen_dmtc0()
7715 gen_save_pc(ctx->base.pc_next + 4); in gen_dmtc0()
7716 ctx->base.is_jmp = DISAS_EXIT; in gen_dmtc0()
7754 ctx->base.is_jmp = DISAS_STOP; in gen_dmtc0()
7764 ctx->base.is_jmp = DISAS_STOP; in gen_dmtc0()
7770 ctx->base.is_jmp = DISAS_STOP; in gen_dmtc0()
7780 ctx->base.is_jmp = DISAS_STOP; in gen_dmtc0()
7795 CP0_CHECK(ctx->mrp); in gen_dmtc0()
7800 CP0_CHECK(ctx->mrp); in gen_dmtc0()
7818 CP0_CHECK(ctx->CP0_Config1 & (1 << CP0C1_WR)); in gen_dmtc0()
7836 CP0_CHECK(ctx->CP0_Config1 & (1 << CP0C1_WR)); in gen_dmtc0()
7857 CP0_CHECK(!(ctx->insn_flags & ISA_MIPS_R6)); in gen_dmtc0()
7876 gen_save_pc(ctx->base.pc_next + 4); in gen_dmtc0()
7877 ctx->base.is_jmp = DISAS_EXIT; in gen_dmtc0()
7884 ctx->base.is_jmp = DISAS_STOP; in gen_dmtc0()
7891 ctx->base.is_jmp = DISAS_STOP; in gen_dmtc0()
7898 ctx->base.is_jmp = DISAS_STOP; in gen_dmtc0()
7905 ctx->base.is_jmp = DISAS_STOP; in gen_dmtc0()
7912 ctx->base.is_jmp = DISAS_STOP; in gen_dmtc0()
7972 ctx->base.is_jmp = DISAS_STOP; in gen_dmtc0()
8053 CP0_CHECK(ctx->kscrexist & (1 << sel)); in gen_dmtc0()
8055 offsetof(CPUMIPSState, CP0_KScratch[sel - 2])); in gen_dmtc0()
8073 gen_save_pc(ctx->base.pc_next + 4); in gen_dmtc0()
8074 ctx->base.is_jmp = DISAS_EXIT; in gen_dmtc0()
8087 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); in gen_mftr()
8090 if ((env->CP0_VPEConf0 & (1 << CP0VPEC0_MVP)) == 0 && in gen_mftr()
8091 ((env->tcs[other_tc].CP0_TCBind & (0xf << CP0TCBd_CurVPE)) != in gen_mftr()
8092 (env->active_tc.CP0_TCBind & (0xf << CP0TCBd_CurVPE)))) { in gen_mftr()
8093 tcg_gen_movi_tl(t0, -1); in gen_mftr()
8094 } else if ((env->CP0_VPEControl & (0xff << CP0VPECo_TargTC)) > in gen_mftr()
8095 (env->mvp->CP0_MVPConf0 & (0xff << CP0MVPC0_PTC))) { in gen_mftr()
8096 tcg_gen_movi_tl(t0, -1); in gen_mftr()
8311 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); in gen_mttr()
8315 if ((env->CP0_VPEConf0 & (1 << CP0VPEC0_MVP)) == 0 && in gen_mttr()
8316 ((env->tcs[other_tc].CP0_TCBind & (0xf << CP0TCBd_CurVPE)) != in gen_mttr()
8317 (env->active_tc.CP0_TCBind & (0xf << CP0TCBd_CurVPE)))) { in gen_mttr()
8320 } else if ((env->CP0_VPEControl & (0xff << CP0VPECo_TargTC)) > in gen_mttr()
8321 (env->mvp->CP0_MVPConf0 & (0xff << CP0MVPC0_PTC))) { in gen_mttr()
8491 ctx->base.is_jmp = DISAS_STOP; in gen_mttr()
8521 gen_mfc0(ctx, cpu_gpr[rt], rd, ctx->opcode & 0x7); in gen_cp0()
8529 gen_mtc0(ctx, t0, rd, ctx->opcode & 0x7); in gen_cp0()
8540 gen_dmfc0(ctx, cpu_gpr[rt], rd, ctx->opcode & 0x7); in gen_cp0()
8549 gen_dmtc0(ctx, t0, rd, ctx->opcode & 0x7); in gen_cp0()
8560 gen_mfhc0(ctx, cpu_gpr[rt], rd, ctx->opcode & 0x7); in gen_cp0()
8568 gen_mthc0(ctx, t0, rd, ctx->opcode & 0x7); in gen_cp0()
8578 gen_mftr(env, ctx, rt, rd, (ctx->opcode >> 5) & 1, in gen_cp0()
8579 ctx->opcode & 0x7, (ctx->opcode >> 4) & 1); in gen_cp0()
8584 gen_mttr(env, ctx, rd, rt, (ctx->opcode >> 5) & 1, in gen_cp0()
8585 ctx->opcode & 0x7, (ctx->opcode >> 4) & 1); in gen_cp0()
8590 if (!env->tlb->helper_tlbwi) { in gen_cp0()
8597 if (ctx->ie >= 2) { in gen_cp0()
8598 if (!env->tlb->helper_tlbinv) { in gen_cp0()
8606 if (ctx->ie >= 2) { in gen_cp0()
8607 if (!env->tlb->helper_tlbinvf) { in gen_cp0()
8615 if (!env->tlb->helper_tlbwr) { in gen_cp0()
8622 if (!env->tlb->helper_tlbp) { in gen_cp0()
8629 if (!env->tlb->helper_tlbr) { in gen_cp0()
8635 if ((ctx->insn_flags & ISA_MIPS_R6) && in gen_cp0()
8636 (ctx->hflags & MIPS_HFLAG_BMASK)) { in gen_cp0()
8639 int bit_shift = (ctx->hflags & MIPS_HFLAG_M16) ? 16 : 6; in gen_cp0()
8640 if (ctx->opcode & (1 << bit_shift)) { in gen_cp0()
8651 ctx->base.is_jmp = DISAS_EXIT; in gen_cp0()
8657 if ((ctx->insn_flags & ISA_MIPS_R6) && in gen_cp0()
8658 (ctx->hflags & MIPS_HFLAG_BMASK)) { in gen_cp0()
8661 if (!(ctx->hflags & MIPS_HFLAG_DM)) { in gen_cp0()
8666 ctx->base.is_jmp = DISAS_EXIT; in gen_cp0()
8672 if ((ctx->insn_flags & ISA_MIPS_R6) && in gen_cp0()
8673 (ctx->hflags & MIPS_HFLAG_BMASK)) { in gen_cp0()
8677 ctx->base.pc_next += 4; in gen_cp0()
8679 ctx->base.pc_next -= 4; in gen_cp0()
8681 ctx->base.is_jmp = DISAS_NORETURN; in gen_cp0()
8695 int32_t cc, int32_t offset) in gen_compute_branch1() argument
8700 if ((ctx->insn_flags & ISA_MIPS_R6) && (ctx->hflags & MIPS_HFLAG_BMASK)) { in gen_compute_branch1()
8709 btarget = ctx->base.pc_next + 4 + offset; in gen_compute_branch1()
8734 ctx->hflags |= MIPS_HFLAG_BL; in gen_compute_branch1()
8784 ctx->hflags |= MIPS_HFLAG_BC; in gen_compute_branch1()
8791 ctx->btarget = btarget; in gen_compute_branch1()
8792 ctx->hflags |= MIPS_HFLAG_BDS32; in gen_compute_branch1()
8797 int32_t ft, int32_t offset, in gen_compute_branch1_r6() argument
8803 if (ctx->hflags & MIPS_HFLAG_BMASK) { in gen_compute_branch1_r6()
8806 VADDR_PRIx "\n", ctx->base.pc_next); in gen_compute_branch1_r6()
8815 btarget = addr_add(ctx, ctx->base.pc_next + 4, offset); in gen_compute_branch1_r6()
8820 ctx->hflags |= MIPS_HFLAG_BC; in gen_compute_branch1_r6()
8824 ctx->hflags |= MIPS_HFLAG_BC; in gen_compute_branch1_r6()
8834 ctx->btarget = btarget; in gen_compute_branch1_r6()
8838 ctx->hflags |= MIPS_HFLAG_BDS16; in gen_compute_branch1_r6()
8841 ctx->hflags |= MIPS_HFLAG_BDS32; in gen_compute_branch1_r6()
9092 ctx->base.is_jmp = DISAS_STOP; in gen_cp1()
9292 uint32_t func = ctx->opcode & 0x3f; in gen_farith()
9352 if (ctx->abs2008) { in gen_farith()
9373 if (ctx->abs2008) { in gen_farith()
9388 if (ctx->nan2008) { in gen_farith()
9403 if (ctx->nan2008) { in gen_farith()
9418 if (ctx->nan2008) { in gen_farith()
9433 if (ctx->nan2008) { in gen_farith()
9446 if (ctx->nan2008) { in gen_farith()
9459 if (ctx->nan2008) { in gen_farith()
9472 if (ctx->nan2008) { in gen_farith()
9485 if (ctx->nan2008) { in gen_farith()
9602 if (ctx->insn_flags & ISA_MIPS_R6) { in gen_farith()
9626 if (ctx->insn_flags & ISA_MIPS_R6) { in gen_farith()
9648 if (ctx->insn_flags & ISA_MIPS_R6) { in gen_farith()
9669 if (ctx->insn_flags & ISA_MIPS_R6) { in gen_farith()
9707 if (ctx->nan2008) { in gen_farith()
9722 if (ctx->nan2008) { in gen_farith()
9760 if (ctx->opcode & (1 << 6)) { in gen_farith()
9761 gen_cmpabs_s(ctx, func - 48, ft, fs, cc); in gen_farith()
9763 gen_cmp_s(ctx, func - 48, ft, fs, cc); in gen_farith()
9830 if (ctx->abs2008) { in gen_farith()
9853 if (ctx->abs2008) { in gen_farith()
9867 if (ctx->nan2008) { in gen_farith()
9881 if (ctx->nan2008) { in gen_farith()
9895 if (ctx->nan2008) { in gen_farith()
9909 if (ctx->nan2008) { in gen_farith()
9924 if (ctx->nan2008) { in gen_farith()
9939 if (ctx->nan2008) { in gen_farith()
9954 if (ctx->nan2008) { in gen_farith()
9969 if (ctx->nan2008) { in gen_farith()
10088 if (ctx->insn_flags & ISA_MIPS_R6) { in gen_farith()
10111 if (ctx->insn_flags & ISA_MIPS_R6) { in gen_farith()
10132 if (ctx->insn_flags & ISA_MIPS_R6) { in gen_farith()
10153 if (ctx->insn_flags & ISA_MIPS_R6) { in gen_farith()
10192 if (ctx->opcode & (1 << 6)) { in gen_farith()
10193 gen_cmpabs_d(ctx, func - 48, ft, fs, cc); in gen_farith()
10195 gen_cmp_d(ctx, func - 48, ft, fs, cc); in gen_farith()
10216 if (ctx->nan2008) { in gen_farith()
10230 if (ctx->nan2008) { in gen_farith()
10550 if (ctx->opcode & (1 << 6)) { in gen_farith()
10551 gen_cmpabs_ps(ctx, func - 48, ft, fs, cc); in gen_farith()
10553 gen_cmp_ps(ctx, func - 48, ft, fs, cc); in gen_farith()
10580 tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, mo_endian(ctx) | MO_SL); in gen_flt3_ldst()
10590 tcg_gen_qemu_ld_i64(fp0, t0, ctx->mem_idx, mo_endian(ctx) | MO_UQ); in gen_flt3_ldst()
10600 tcg_gen_qemu_ld_i64(fp0, t0, ctx->mem_idx, mo_endian(ctx) | MO_UQ); in gen_flt3_ldst()
10609 tcg_gen_qemu_st_i32(fp0, t0, ctx->mem_idx, mo_endian(ctx) | MO_UL); in gen_flt3_ldst()
10618 tcg_gen_qemu_st_i64(fp0, t0, ctx->mem_idx, mo_endian(ctx) | MO_UQ); in gen_flt3_ldst()
10627 tcg_gen_qemu_st_i64(fp0, t0, ctx->mem_idx, mo_endian(ctx) | MO_UQ); in gen_flt3_ldst()
10873 translator_io_start(&ctx->base); in gen_rdhwr()
10881 gen_save_pc(ctx->base.pc_next + 4); in gen_rdhwr()
10882 ctx->base.is_jmp = DISAS_EXIT; in gen_rdhwr()
10912 if ((ctx->hflags & MIPS_HFLAG_CP0) || in gen_rdhwr()
10913 (ctx->hflags & MIPS_HFLAG_HWRENA_ULR)) { in gen_rdhwr()
10931 ctx->hflags &= ~MIPS_HFLAG_BMASK; in clear_branch_hflags()
10932 if (ctx->base.is_jmp == DISAS_NEXT) { in clear_branch_hflags()
10936 * It is not safe to save ctx->hflags as hflags may be changed in clear_branch_hflags()
10945 if (ctx->hflags & MIPS_HFLAG_BMASK) { in gen_branch()
10946 int proc_hflags = ctx->hflags & MIPS_HFLAG_BMASK; in gen_branch()
10949 ctx->base.is_jmp = DISAS_NORETURN; in gen_branch()
10952 gen_goto_tb(ctx, 0, ctx->base.pc_next + insn_bytes); in gen_branch()
10959 gen_goto_tb(ctx, 0, ctx->btarget); in gen_branch()
10963 gen_goto_tb(ctx, 0, ctx->btarget); in gen_branch()
10971 gen_goto_tb(ctx, 1, ctx->base.pc_next + insn_bytes); in gen_branch()
10973 gen_goto_tb(ctx, 0, ctx->btarget); in gen_branch()
10978 if (ctx->insn_flags & (ASE_MIPS16 | ASE_MICROMIPS)) { in gen_branch()
11003 int rs, int rt, int32_t offset) in gen_compute_compact_branch() argument
11008 int m16_lowbit = (ctx->hflags & MIPS_HFLAG_M16) != 0; in gen_compute_compact_branch()
11010 if (ctx->hflags & MIPS_HFLAG_BMASK) { in gen_compute_compact_branch()
11013 VADDR_PRIx "\n", ctx->base.pc_next); in gen_compute_compact_branch()
11027 ctx->btarget = addr_add(ctx, ctx->base.pc_next + 4, offset); in gen_compute_compact_branch()
11030 tcg_gen_movi_tl(cpu_gpr[31], ctx->base.pc_next + 4 + m16_lowbit); in gen_compute_compact_branch()
11038 ctx->btarget = addr_add(ctx, ctx->base.pc_next + 4, offset); in gen_compute_compact_branch()
11045 tcg_gen_movi_tl(cpu_gpr[31], ctx->base.pc_next + 4 + m16_lowbit); in gen_compute_compact_branch()
11050 ctx->btarget = addr_add(ctx, ctx->base.pc_next + 4, offset); in gen_compute_compact_branch()
11054 ctx->btarget = addr_add(ctx, ctx->base.pc_next + 4, offset); in gen_compute_compact_branch()
11062 ctx->btarget = addr_add(ctx, ctx->base.pc_next + 4, offset); in gen_compute_compact_branch()
11068 gen_op_addr_addi(ctx, btarget, tbase, offset); in gen_compute_compact_branch()
11081 tcg_gen_movi_tl(cpu_gpr[31], ctx->base.pc_next + 4 + m16_lowbit); in gen_compute_compact_branch()
11084 ctx->hflags |= MIPS_HFLAG_BR; in gen_compute_compact_branch()
11087 tcg_gen_movi_tl(cpu_gpr[31], ctx->base.pc_next + 4 + m16_lowbit); in gen_compute_compact_branch()
11090 ctx->hflags |= MIPS_HFLAG_B; in gen_compute_compact_branch()
11218 gen_goto_tb(ctx, 1, ctx->btarget); in gen_compute_compact_branch()
11221 ctx->hflags |= MIPS_HFLAG_FBNSLOT; in gen_compute_compact_branch()
11230 if (extended && (ctx->hflags & MIPS_HFLAG_BMASK)) { in gen_addiupc()
11243 int16_t offset) in gen_cache_operation() argument
11247 gen_base_offset_addr(ctx, t1, base, offset); in gen_cache_operation()
11256 bool is_user = (ctx->hflags & MIPS_HFLAG_KSU) == MIPS_HFLAG_UM; in is_uhi()
11274 tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, mo_endian(ctx) | MO_SL); in gen_ldxs()
11314 * Values for microMIPS fmt field. Variable-width, depending on which
11805 op2 = MASK_SHLL_QB(ctx->opcode); in gen_mipsdsp_shift()
11904 op2 = MASK_SHLL_OB(ctx->opcode); in gen_mipsdsp_shift()
12349 imm = (ctx->opcode >> 16) & 0xFF; in gen_mipsdsp_bitinsn()
12370 imm = (ctx->opcode >> 16) & 0x03FF; in gen_mipsdsp_bitinsn()
12394 imm = (ctx->opcode >> 16) & 0xFF; in gen_mipsdsp_bitinsn()
12406 imm = (ctx->opcode >> 16) & 0x03FF; in gen_mipsdsp_bitinsn()
12418 imm = (ctx->opcode >> 16) & 0x03FF; in gen_mipsdsp_bitinsn()
12657 switch (MASK_APPEND(ctx->opcode)) { in gen_mipsdsp_append()
12660 tcg_gen_deposit_tl(cpu_gpr[rt], t0, cpu_gpr[rt], sa, 32 - sa); in gen_mipsdsp_append()
12668 tcg_gen_shli_tl(t0, t0, 32 - sa); in gen_mipsdsp_append()
12678 tcg_gen_shri_tl(t0, t0, 8 * (4 - sa)); in gen_mipsdsp_append()
12691 switch (MASK_DAPPEND(ctx->opcode)) { in gen_mipsdsp_append()
12694 tcg_gen_deposit_tl(cpu_gpr[rt], t0, cpu_gpr[rt], sa, 64 - sa); in gen_mipsdsp_append()
12699 tcg_gen_shli_tl(t0, t0, 64 - (0x20 | sa)); in gen_mipsdsp_append()
12705 tcg_gen_shli_tl(t0, t0, 64 - sa); in gen_mipsdsp_append()
12713 tcg_gen_shri_tl(t0, t0, 8 * (8 - sa)); in gen_mipsdsp_append()
12806 imm = (ctx->opcode >> 20) & 0x3F; in gen_mipsdsp_accinsn()
12820 imm = (ctx->opcode >> 11) & 0x3FF; in gen_mipsdsp_accinsn()
12825 imm = (ctx->opcode >> 16) & 0x03FF; in gen_mipsdsp_accinsn()
12841 int shift = (ctx->opcode >> 19) & 0x7F; in gen_mipsdsp_accinsn()
12842 int ac = (ctx->opcode >> 11) & 0x03; in gen_mipsdsp_accinsn()
12850 int ac = (ctx->opcode >> 11) & 0x03; in gen_mipsdsp_accinsn()
12950 rs = (ctx->opcode >> 21) & 0x1f; in decode_opc_special_r6()
12951 rt = (ctx->opcode >> 16) & 0x1f; in decode_opc_special_r6()
12952 rd = (ctx->opcode >> 11) & 0x1f; in decode_opc_special_r6()
12953 sa = (ctx->opcode >> 6) & 0x1f; in decode_opc_special_r6()
12955 op1 = MASK_SPECIAL(ctx->opcode); in decode_opc_special_r6()
12961 op2 = MASK_R6_MULDIV(ctx->opcode); in decode_opc_special_r6()
12996 if (is_uhi(ctx, extract32(ctx->opcode, 6, 20))) { in decode_opc_special_r6()
12997 ctx->base.is_jmp = DISAS_SEMIHOST; in decode_opc_special_r6()
12999 if (ctx->hflags & MIPS_HFLAG_SBRI) { in decode_opc_special_r6()
13025 op2 = MASK_R6_MULDIV(ctx->opcode); in decode_opc_special_r6()
13054 int rs = extract32(ctx->opcode, 21, 5); in decode_opc_special_tx79()
13055 int rt = extract32(ctx->opcode, 16, 5); in decode_opc_special_tx79()
13056 int rd = extract32(ctx->opcode, 11, 5); in decode_opc_special_tx79()
13057 uint32_t op1 = MASK_SPECIAL(ctx->opcode); in decode_opc_special_tx79()
13104 rs = (ctx->opcode >> 21) & 0x1f; in decode_opc_special_legacy()
13105 rt = (ctx->opcode >> 16) & 0x1f; in decode_opc_special_legacy()
13106 rd = (ctx->opcode >> 11) & 0x1f; in decode_opc_special_legacy()
13108 op1 = MASK_SPECIAL(ctx->opcode); in decode_opc_special_legacy()
13126 if (env->CP0_Config1 & (1 << CP0C1_FP)) { in decode_opc_special_legacy()
13128 gen_movci(ctx, rd, rs, (ctx->opcode >> 18) & 0x7, in decode_opc_special_legacy()
13129 (ctx->opcode >> 16) & 1); in decode_opc_special_legacy()
13177 rs = (ctx->opcode >> 21) & 0x1f; in decode_opc_special()
13178 rt = (ctx->opcode >> 16) & 0x1f; in decode_opc_special()
13179 rd = (ctx->opcode >> 11) & 0x1f; in decode_opc_special()
13180 sa = (ctx->opcode >> 6) & 0x1f; in decode_opc_special()
13182 op1 = MASK_SPECIAL(ctx->opcode); in decode_opc_special()
13187 if ((ctx->insn_flags & ISA_MIPS_R6) && in decode_opc_special()
13188 (ctx->hflags & MIPS_HFLAG_BMASK)) { in decode_opc_special()
13198 switch ((ctx->opcode >> 21) & 0x1f) { in decode_opc_special()
13200 /* rotr is decoded as srl on non-R2 CPUs */ in decode_opc_special()
13201 if (ctx->insn_flags & ISA_MIPS_R2) { in decode_opc_special()
13224 switch ((ctx->opcode >> 6) & 0x1f) { in decode_opc_special()
13226 /* rotrv is decoded as srlv on non-R2 CPUs */ in decode_opc_special()
13227 if (ctx->insn_flags & ISA_MIPS_R2) { in decode_opc_special()
13259 gen_trap(ctx, op1, rs, rt, -1, extract32(ctx->opcode, 6, 10)); in decode_opc_special()
13274 generate_exception_break(ctx, extract32(ctx->opcode, 6, 20)); in decode_opc_special()
13278 gen_sync(extract32(ctx->opcode, 6, 5)); in decode_opc_special()
13292 switch ((ctx->opcode >> 21) & 0x1f) { in decode_opc_special()
13294 /* drotr is decoded as dsrl on non-R2 CPUs */ in decode_opc_special()
13295 if (ctx->insn_flags & ISA_MIPS_R2) { in decode_opc_special()
13310 switch ((ctx->opcode >> 21) & 0x1f) { in decode_opc_special()
13312 /* drotr32 is decoded as dsrl32 on non-R2 CPUs */ in decode_opc_special()
13313 if (ctx->insn_flags & ISA_MIPS_R2) { in decode_opc_special()
13342 switch ((ctx->opcode >> 6) & 0x1f) { in decode_opc_special()
13344 /* drotrv is decoded as dsrlv on non-R2 CPUs */ in decode_opc_special()
13345 if (ctx->insn_flags & ISA_MIPS_R2) { in decode_opc_special()
13361 if (ctx->insn_flags & ISA_MIPS_R6) { in decode_opc_special()
13363 } else if (ctx->insn_flags & INSN_R5900) { in decode_opc_special()
13377 rs = (ctx->opcode >> 21) & 0x1f; in decode_opc_special2_legacy()
13378 rt = (ctx->opcode >> 16) & 0x1f; in decode_opc_special2_legacy()
13379 rd = (ctx->opcode >> 11) & 0x1f; in decode_opc_special2_legacy()
13381 op1 = MASK_SPECIAL2(ctx->opcode); in decode_opc_special2_legacy()
13399 if (is_uhi(ctx, extract32(ctx->opcode, 6, 20))) { in decode_opc_special2_legacy()
13400 ctx->base.is_jmp = DISAS_SEMIHOST; in decode_opc_special2_legacy()
13454 rs = (ctx->opcode >> 21) & 0x1f; in decode_opc_special3_r6()
13455 rt = (ctx->opcode >> 16) & 0x1f; in decode_opc_special3_r6()
13456 rd = (ctx->opcode >> 11) & 0x1f; in decode_opc_special3_r6()
13457 sa = (ctx->opcode >> 6) & 0x1f; in decode_opc_special3_r6()
13458 imm = (int16_t)ctx->opcode >> 7; in decode_opc_special3_r6()
13460 op1 = MASK_SPECIAL3(ctx->opcode); in decode_opc_special3_r6()
13464 /* hint codes 24-31 are reserved and signal RI */ in decode_opc_special3_r6()
13471 if (ctx->hflags & MIPS_HFLAG_ITC_CACHE) { in decode_opc_special3_r6()
13487 op2 = MASK_BSHFL(ctx->opcode); in decode_opc_special3_r6()
13503 if (unlikely(ctx->gi <= 1)) { in decode_opc_special3_r6()
13507 switch ((ctx->opcode >> 6) & 3) { in decode_opc_special3_r6()
13512 gen_helper_0e1i(ginvt, cpu_gpr[rs], extract32(ctx->opcode, 8, 2)); in decode_opc_special3_r6()
13534 op2 = MASK_DBSHFL(ctx->opcode); in decode_opc_special3_r6()
13566 rs = (ctx->opcode >> 21) & 0x1f; in decode_opc_special3_legacy()
13567 rt = (ctx->opcode >> 16) & 0x1f; in decode_opc_special3_legacy()
13568 rd = (ctx->opcode >> 11) & 0x1f; in decode_opc_special3_legacy()
13570 op1 = MASK_SPECIAL3(ctx->opcode); in decode_opc_special3_legacy()
13577 if ((ctx->insn_flags & ASE_DSP_R2) && (op1 == OPC_MUL_PH_DSP)) { in decode_opc_special3_legacy()
13578 op2 = MASK_ADDUH_QB(ctx->opcode); in decode_opc_special3_legacy()
13611 op2 = MASK_LX(ctx->opcode); in decode_opc_special3_legacy()
13634 op2 = MASK_ABSQ_S_PH(ctx->opcode); in decode_opc_special3_legacy()
13665 op2 = MASK_ADDU_QB(ctx->opcode); in decode_opc_special3_legacy()
13703 op2 = MASK_CMPU_EQ_QB(ctx->opcode); in decode_opc_special3_legacy()
13745 op2 = MASK_DPA_W_PH(ctx->opcode); in decode_opc_special3_legacy()
13778 op2 = MASK_INSV(ctx->opcode); in decode_opc_special3_legacy()
13808 op2 = MASK_EXTR_W(ctx->opcode); in decode_opc_special3_legacy()
13841 op2 = MASK_ABSQ_S_QH(ctx->opcode); in decode_opc_special3_legacy()
13877 op2 = MASK_ADDU_OB(ctx->opcode); in decode_opc_special3_legacy()
13916 op2 = MASK_CMPU_EQ_OB(ctx->opcode); in decode_opc_special3_legacy()
13964 op2 = MASK_DEXTR_W(ctx->opcode); in decode_opc_special3_legacy()
13998 op2 = MASK_DPAQ_W_QH(ctx->opcode); in decode_opc_special3_legacy()
14037 op2 = MASK_INSV(ctx->opcode); in decode_opc_special3_legacy()
14080 uint32_t opc = MASK_MMI(ctx->opcode); in decode_mmi()
14081 int rs = extract32(ctx->opcode, 21, 5); in decode_mmi()
14082 int rt = extract32(ctx->opcode, 16, 5); in decode_mmi()
14083 int rd = extract32(ctx->opcode, 11, 5); in decode_mmi()
14105 static void gen_mmi_sq(DisasContext *ctx, int base, int rt, int offset) in gen_mmi_sq() argument
14111 * The TX79-specific instruction Store Quadword
14113 * +--------+-------+-------+------------------------+
14114 * | 011111 | base | rt | offset | SQ
14115 * +--------+-------+-------+------------------------+
14120 * +--------+-------+-------+-------+-------+--------+
14122 * +--------+-------+-------+-------+-------+--------+
14127 * offset is odd. Therefore all valid SQ instructions can execute normally.
14133 int base = extract32(ctx->opcode, 21, 5); in decode_mmi_sq()
14134 int rt = extract32(ctx->opcode, 16, 5); in decode_mmi_sq()
14135 int offset = extract32(ctx->opcode, 0, 16); in decode_mmi_sq() local
14138 uint32_t op1 = MASK_SPECIAL3(ctx->opcode); in decode_mmi_sq()
14139 uint32_t op2 = extract32(ctx->opcode, 6, 5); in decode_mmi_sq()
14142 int rd = extract32(ctx->opcode, 11, 5); in decode_mmi_sq()
14149 gen_mmi_sq(ctx, base, rt, offset); in decode_mmi_sq()
14160 rs = (ctx->opcode >> 21) & 0x1f; in decode_opc_special3()
14161 rt = (ctx->opcode >> 16) & 0x1f; in decode_opc_special3()
14162 rd = (ctx->opcode >> 11) & 0x1f; in decode_opc_special3()
14163 sa = (ctx->opcode >> 6) & 0x1f; in decode_opc_special3()
14164 imm = sextract32(ctx->opcode, 7, 9); in decode_opc_special3()
14166 op1 = MASK_SPECIAL3(ctx->opcode); in decode_opc_special3()
14173 if (ctx->eva) { in decode_opc_special3()
14201 if (ctx->hflags & MIPS_HFLAG_ITC_CACHE) { in decode_opc_special3()
14219 op2 = MASK_BSHFL(ctx->opcode); in decode_opc_special3()
14247 op2 = MASK_DBSHFL(ctx->opcode); in decode_opc_special3()
14264 op2 = MASK_DBSHFL(ctx->opcode); in decode_opc_special3()
14271 gen_rdhwr(ctx, rt, rd, extract32(ctx->opcode, 6, 3)); in decode_opc_special3()
14295 if (ctx->insn_flags & ISA_MIPS_R6) { in decode_opc_special3()
14305 int32_t offset; in decode_opc_legacy() local
14310 op = MASK_OP_MAJOR(ctx->opcode); in decode_opc_legacy()
14311 rs = (ctx->opcode >> 21) & 0x1f; in decode_opc_legacy()
14312 rt = (ctx->opcode >> 16) & 0x1f; in decode_opc_legacy()
14313 rd = (ctx->opcode >> 11) & 0x1f; in decode_opc_legacy()
14314 sa = (ctx->opcode >> 6) & 0x1f; in decode_opc_legacy()
14315 imm = (int16_t)ctx->opcode; in decode_opc_legacy()
14322 if ((ctx->insn_flags & INSN_R5900) && (ctx->insn_flags & ASE_MMI)) { in decode_opc_legacy()
14327 if (TARGET_LONG_BITS == 32 && (ctx->insn_flags & ASE_MXU)) { in decode_opc_legacy()
14328 if (decode_ase_mxu(ctx, ctx->opcode)) { in decode_opc_legacy()
14336 if (ctx->insn_flags & INSN_R5900) { in decode_opc_legacy()
14346 op1 = MASK_REGIMM(ctx->opcode); in decode_opc_legacy()
14357 gen_compute_branch(ctx, op1, 4, rs, -1, imm << 2, 4); in decode_opc_legacy()
14361 if (ctx->insn_flags & ISA_MIPS_R6) { in decode_opc_legacy()
14364 gen_compute_branch(ctx, op1, 4, 0, -1, imm << 2, 4); in decode_opc_legacy()
14369 gen_compute_branch(ctx, op1, 4, rs, -1, imm << 2, 4); in decode_opc_legacy()
14380 gen_trap(ctx, op1, rs, -1, imm, 0); in decode_opc_legacy()
14392 ctx->base.is_jmp = DISAS_STOP; in decode_opc_legacy()
14399 gen_compute_branch(ctx, op1, 4, -1, -2, (int32_t)imm << 2, 4); in decode_opc_legacy()
14425 op1 = MASK_CP0(ctx->opcode); in decode_opc_legacy()
14458 gen_cp0(env, ctx, MASK_C0(ctx->opcode), rt, rd); in decode_opc_legacy()
14467 op2 = MASK_MFMC0(ctx->opcode); in decode_opc_legacy()
14491 if (ctx->vp) { in decode_opc_legacy()
14498 if (ctx->vp) { in decode_opc_legacy()
14512 ctx->base.is_jmp = DISAS_STOP; in decode_opc_legacy()
14523 gen_save_pc(ctx->base.pc_next + 4); in decode_opc_legacy()
14524 ctx->base.is_jmp = DISAS_EXIT; in decode_opc_legacy()
14549 if (ctx->insn_flags & ISA_MIPS_R6) { in decode_opc_legacy()
14573 offset = (int32_t)(ctx->opcode & 0x3FFFFFF) << 2; in decode_opc_legacy()
14574 gen_compute_branch(ctx, op, 4, rs, rt, offset, 4); in decode_opc_legacy()
14578 if (ctx->insn_flags & ISA_MIPS_R6) { in decode_opc_legacy()
14591 if (ctx->insn_flags & ISA_MIPS_R6) { in decode_opc_legacy()
14634 if (ctx->insn_flags & INSN_R5900) { in decode_opc_legacy()
14657 if (ctx->insn_flags & INSN_R5900) { in decode_opc_legacy()
14665 if (ctx->hflags & MIPS_HFLAG_ITC_CACHE) { in decode_opc_legacy()
14684 op1 = MASK_CP1(ctx->opcode); in decode_opc_legacy()
14710 if (ctx->insn_flags & ISA_MIPS_R6) { in decode_opc_legacy()
14712 gen_compute_branch1_r6(ctx, MASK_CP1(ctx->opcode), in decode_opc_legacy()
14720 gen_compute_branch1(ctx, MASK_BC1(ctx->opcode), in decode_opc_legacy()
14727 gen_compute_branch1_r6(ctx, MASK_CP1(ctx->opcode), in decode_opc_legacy()
14741 gen_compute_branch1(ctx, MASK_BC1(ctx->opcode), in decode_opc_legacy()
14750 gen_farith(ctx, ctx->opcode & FOP(0x3f, 0x1f), rt, rd, sa, in decode_opc_legacy()
14756 int r6_op = ctx->opcode & FOP(0x3f, 0x1f); in decode_opc_legacy()
14758 if (ctx->insn_flags & ISA_MIPS_R6) { in decode_opc_legacy()
14782 gen_r6_cmp_s(ctx, ctx->opcode & 0x1f, rt, rd, sa); in decode_opc_legacy()
14806 gen_r6_cmp_d(ctx, ctx->opcode & 0x1f, rt, rd, sa); in decode_opc_legacy()
14809 gen_farith(ctx, ctx->opcode & FOP(0x3f, 0x1f), in decode_opc_legacy()
14815 gen_farith(ctx, ctx->opcode & FOP(0x3f, 0x1f), rt, rd, sa, in decode_opc_legacy()
14827 /* Compact branches [R6] and COP2 [non-R6] */ in decode_opc_legacy()
14830 if (ctx->insn_flags & ISA_MIPS_R6) { in decode_opc_legacy()
14833 sextract32(ctx->opcode << 2, 0, 28)); in decode_opc_legacy()
14834 } else if (ctx->insn_flags & ASE_LEXT) { in decode_opc_legacy()
14844 if (ctx->insn_flags & ISA_MIPS_R6) { in decode_opc_legacy()
14848 sextract32(ctx->opcode << 2, 0, 23)); in decode_opc_legacy()
14853 } else if (ctx->insn_flags & ASE_LEXT) { in decode_opc_legacy()
14868 if (ctx->CP0_Config1 & (1 << CP0C1_FP)) { in decode_opc_legacy()
14870 op1 = MASK_CP3(ctx->opcode); in decode_opc_legacy()
14918 if (ctx->insn_flags & INSN_R5900) { in decode_opc_legacy()
14939 if (ctx->insn_flags & INSN_R5900) { in decode_opc_legacy()
14946 if (ctx->insn_flags & ISA_MIPS_R6) { in decode_opc_legacy()
14963 if (ctx->insn_flags & ISA_MIPS_R6) { in decode_opc_legacy()
14972 if (ctx->insn_flags & ISA_MIPS_R6) { in decode_opc_legacy()
14990 offset = (int32_t)(ctx->opcode & 0x3FFFFFF) << 2; in decode_opc_legacy()
14991 gen_compute_branch(ctx, op, 4, rs, rt, offset, 4); in decode_opc_legacy()
14999 gen_pcrel(ctx, ctx->opcode, ctx->base.pc_next, rs); in decode_opc_legacy()
15011 if (ctx->base.pc_next & 0x3) { in decode_opc()
15012 env->CP0_BadVAddr = ctx->base.pc_next; in decode_opc()
15018 if ((ctx->hflags & MIPS_HFLAG_BMASK_BASE) == MIPS_HFLAG_BL) { in decode_opc()
15022 tcg_gen_movi_i32(hflags, ctx->hflags & ~MIPS_HFLAG_BMASK); in decode_opc()
15023 gen_goto_tb(ctx, 1, ctx->base.pc_next + 4); in decode_opc()
15027 /* Transition to the auto-generated decoder. */ in decode_opc()
15030 if (cpu_supports_isa(env, INSN_R5900) && decode_ext_txx9(ctx, ctx->opcode)) { in decode_opc()
15033 if (cpu_supports_isa(env, INSN_VR54XX) && decode_ext_vr54xx(ctx, ctx->opcode)) { in decode_opc()
15036 if (TARGET_LONG_BITS == 64 && decode_ext_loongson(ctx, ctx->opcode)) { in decode_opc()
15040 if (ase_lcsr_available(env) && decode_ase_lcsr(ctx, ctx->opcode)) { in decode_opc()
15043 if (cpu_supports_isa(env, INSN_OCTEON) && decode_ext_octeon(ctx, ctx->opcode)) { in decode_opc()
15049 if (ase_msa_available(env) && decode_ase_msa(ctx, ctx->opcode)) { in decode_opc()
15054 if (cpu_supports_isa(env, ISA_MIPS_R6) && decode_isa_rel6(ctx, ctx->opcode)) { in decode_opc()
15070 ctx->page_start = ctx->base.pc_first & TARGET_PAGE_MASK; in mips_tr_init_disas_context()
15071 ctx->saved_pc = -1; in mips_tr_init_disas_context()
15072 ctx->insn_flags = env->insn_flags; in mips_tr_init_disas_context()
15073 ctx->CP0_Config0 = env->CP0_Config0; in mips_tr_init_disas_context()
15074 ctx->CP0_Config1 = env->CP0_Config1; in mips_tr_init_disas_context()
15075 ctx->CP0_Config2 = env->CP0_Config2; in mips_tr_init_disas_context()
15076 ctx->CP0_Config3 = env->CP0_Config3; in mips_tr_init_disas_context()
15077 ctx->CP0_Config5 = env->CP0_Config5; in mips_tr_init_disas_context()
15078 ctx->btarget = 0; in mips_tr_init_disas_context()
15079 ctx->kscrexist = (env->CP0_Config4 >> CP0C4_KScrExist) & 0xff; in mips_tr_init_disas_context()
15080 ctx->rxi = (env->CP0_Config3 >> CP0C3_RXI) & 1; in mips_tr_init_disas_context()
15081 ctx->ie = (env->CP0_Config4 >> CP0C4_IE) & 3; in mips_tr_init_disas_context()
15082 ctx->bi = (env->CP0_Config3 >> CP0C3_BI) & 1; in mips_tr_init_disas_context()
15083 ctx->bp = (env->CP0_Config3 >> CP0C3_BP) & 1; in mips_tr_init_disas_context()
15084 ctx->PAMask = env->PAMask; in mips_tr_init_disas_context()
15085 ctx->mvh = (env->CP0_Config5 >> CP0C5_MVH) & 1; in mips_tr_init_disas_context()
15086 ctx->eva = (env->CP0_Config5 >> CP0C5_EVA) & 1; in mips_tr_init_disas_context()
15087 ctx->sc = (env->CP0_Config3 >> CP0C3_SC) & 1; in mips_tr_init_disas_context()
15088 ctx->CP0_LLAddr_shift = env->CP0_LLAddr_shift; in mips_tr_init_disas_context()
15089 ctx->cmgcr = (env->CP0_Config3 >> CP0C3_CMGCR) & 1; in mips_tr_init_disas_context()
15091 ctx->hflags = (uint32_t)ctx->base.tb->flags; /* FIXME: maybe use 64 bits? */ in mips_tr_init_disas_context()
15092 ctx->ulri = (env->CP0_Config3 >> CP0C3_ULRI) & 1; in mips_tr_init_disas_context()
15093 ctx->ps = ((env->active_fpu.fcr0 >> FCR0_PS) & 1) || in mips_tr_init_disas_context()
15094 (env->insn_flags & (INSN_LOONGSON2E | INSN_LOONGSON2F)); in mips_tr_init_disas_context()
15095 ctx->vp = (env->CP0_Config5 >> CP0C5_VP) & 1; in mips_tr_init_disas_context()
15096 ctx->mrp = (env->CP0_Config5 >> CP0C5_MRP) & 1; in mips_tr_init_disas_context()
15097 ctx->nan2008 = (env->active_fpu.fcr31 >> FCR31_NAN2008) & 1; in mips_tr_init_disas_context()
15098 ctx->abs2008 = (env->active_fpu.fcr31 >> FCR31_ABS2008) & 1; in mips_tr_init_disas_context()
15099 ctx->mi = (env->CP0_Config5 >> CP0C5_MI) & 1; in mips_tr_init_disas_context()
15100 ctx->gi = (env->CP0_Config5 >> CP0C5_GI) & 3; in mips_tr_init_disas_context()
15101 ctx->crcp = (env->CP0_Config5 >> CP0C5_CRCP) & 1; in mips_tr_init_disas_context()
15104 ctx->mem_idx = MIPS_HFLAG_UM; in mips_tr_init_disas_context()
15106 ctx->mem_idx = hflags_mmu_index(ctx->hflags); in mips_tr_init_disas_context()
15108 ctx->default_tcg_memop_mask = (!(ctx->insn_flags & ISA_NANOMIPS32) && in mips_tr_init_disas_context()
15109 (ctx->insn_flags & (ISA_MIPS_R6 | in mips_tr_init_disas_context()
15118 if ((tb_cflags(ctx->base.tb) & CF_SINGLE_STEP) && in mips_tr_init_disas_context()
15119 (ctx->hflags & MIPS_HFLAG_BMASK)) { in mips_tr_init_disas_context()
15120 ctx->base.max_insns = 2; in mips_tr_init_disas_context()
15123 LOG_DISAS("\ntb %p idx %d hflags %04x\n", ctx->base.tb, ctx->mem_idx, in mips_tr_init_disas_context()
15124 ctx->hflags); in mips_tr_init_disas_context()
15135 tcg_gen_insn_start(ctx->base.pc_next, ctx->hflags & MIPS_HFLAG_BMASK, in mips_tr_insn_start()
15136 ctx->btarget); in mips_tr_insn_start()
15146 is_slot = ctx->hflags & MIPS_HFLAG_BMASK; in mips_tr_translate_insn()
15147 if (ctx->insn_flags & ISA_NANOMIPS32) { in mips_tr_translate_insn()
15148 ctx->opcode = translator_lduw(env, &ctx->base, ctx->base.pc_next); in mips_tr_translate_insn()
15150 } else if (!(ctx->hflags & MIPS_HFLAG_M16)) { in mips_tr_translate_insn()
15151 ctx->opcode = translator_ldl(env, &ctx->base, ctx->base.pc_next); in mips_tr_translate_insn()
15154 } else if (ctx->insn_flags & ASE_MICROMIPS) { in mips_tr_translate_insn()
15155 ctx->opcode = translator_lduw(env, &ctx->base, ctx->base.pc_next); in mips_tr_translate_insn()
15157 } else if (ctx->insn_flags & ASE_MIPS16) { in mips_tr_translate_insn()
15158 ctx->opcode = translator_lduw(env, &ctx->base, ctx->base.pc_next); in mips_tr_translate_insn()
15162 g_assert(ctx->base.is_jmp == DISAS_NORETURN); in mips_tr_translate_insn()
15166 if (ctx->hflags & MIPS_HFLAG_BMASK) { in mips_tr_translate_insn()
15167 if (!(ctx->hflags & (MIPS_HFLAG_BDS16 | MIPS_HFLAG_BDS32 | in mips_tr_translate_insn()
15175 if ((ctx->hflags & MIPS_HFLAG_M16) && in mips_tr_translate_insn()
15176 (ctx->hflags & MIPS_HFLAG_FBNSLOT)) { in mips_tr_translate_insn()
15187 if (ctx->base.is_jmp == DISAS_SEMIHOST) { in mips_tr_translate_insn()
15190 ctx->base.pc_next += insn_bytes; in mips_tr_translate_insn()
15192 if (ctx->base.is_jmp != DISAS_NEXT) { in mips_tr_translate_insn()
15198 * See mips_tr_init_disas_context about single-stepping a branch in mips_tr_translate_insn()
15201 if (ctx->base.pc_next - ctx->page_start >= TARGET_PAGE_SIZE in mips_tr_translate_insn()
15202 && !(tb_cflags(ctx->base.tb) & CF_SINGLE_STEP)) { in mips_tr_translate_insn()
15203 ctx->base.is_jmp = DISAS_TOO_MANY; in mips_tr_translate_insn()
15211 switch (ctx->base.is_jmp) { in mips_tr_tb_stop()
15213 gen_save_pc(ctx->base.pc_next); in mips_tr_tb_stop()
15219 gen_goto_tb(ctx, 0, ctx->base.pc_next); in mips_tr_tb_stop()
15316 env->active_tc.PC = data[0]; in mips_restore_state_to_opc()
15317 env->hflags &= ~MIPS_HFLAG_BMASK; in mips_restore_state_to_opc()
15318 env->hflags |= data[1]; in mips_restore_state_to_opc()
15319 switch (env->hflags & MIPS_HFLAG_BMASK_BASE) { in mips_restore_state_to_opc()
15325 env->btarget = data[2]; in mips_restore_state_to_opc()