Lines Matching +full:library +full:- +full:sel
2 * MIPS emulation for QEMU - main translation routines
4 * Copyright (c) 2004-2005 Jocelyn Mayer
9 * Copyright (c) 2020 Philippe Mathieu-Daudé
11 * This library is free software; you can redistribute it and/or
16 * This library is distributed in the hope that it will be useful,
22 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
28 #include "exec/helper-proto.h"
29 #include "exec/translation-block.h"
35 #include "exec/helper-info.c.inc"
40 * Many sysemu-only helpers are not reachable for user-only.
152 /* PC-relative address computation / loads */
156 /* PC-relative address computation / loads */
368 /* MIPS DSP GPR-Based Shift Sub-class */
371 /* MIPS DSP Multiply Sub-class insns */
375 /* DSP Bit/Manipulation Sub-class */
378 /* MIPS DSP Append Sub-class */
381 /* MIPS DSP Accumulator and DSPControl Access Sub-class */
502 /* MIPS DSP Arithmetic Sub-class */
521 /* MIPS DSP Multiply Sub-class insns */
532 /* MIPS DSP Arithmetic Sub-class */
545 /* MIPS DSP Multiply Sub-class insns */
554 /* MIPS DSP Arithmetic Sub-class */
568 /* DSP Bit/Manipulation Sub-class */
578 /* MIPS DSP Arithmetic Sub-class */
586 /* DSP Compare-Pick Sub-class */
606 /* MIPS DSP GPR-Based Shift Sub-class */
633 /* MIPS DSP Multiply Sub-class insns */
660 /* DSP Bit/Manipulation Sub-class */
666 /* MIPS DSP Append Sub-class */
674 /* MIPS DSP Accumulator and DSPControl Access Sub-class */
696 /* MIPS DSP Arithmetic Sub-class */
714 /* DSP Bit/Manipulation Sub-class */
725 /* MIPS DSP Multiply Sub-class insns */
731 /* MIPS DSP Arithmetic Sub-class */
757 /* DSP Compare-Pick Sub-class */
777 /* MIPS DSP Arithmetic Sub-class */
790 /* DSP Append Sub-class */
799 /* MIPS DSP Accumulator and DSPControl Access Sub-class */
825 /* DSP Bit/Manipulation Sub-class */
831 /* MIPS DSP Multiply Sub-class insns */
862 /* MIPS DSP GPR-Based Shift Sub-class */
1110 * +--------+----------------------------------------+
1112 * +--------+----------------------------------------+
1117 * -------+-------+-------+-------+-------+-------+-------+-------+-------
1137 * +--------+-------------------------------+--------+
1139 * +--------+-------------------------------+--------+
1144 * -------+-------+-------+-------+-------+-------+-------+-------+-------
1170 * For CPUs using 128-bit GPR registers, we put the lower halves in cpu_gpr[])
1279 LOG_DISAS("hflags %08x saved %08x\n", ctx->hflags, ctx->saved_hflags); in save_cpu_state()
1280 if (do_save_pc && ctx->base.pc_next != ctx->saved_pc) { in save_cpu_state()
1281 gen_save_pc(ctx->base.pc_next); in save_cpu_state()
1282 ctx->saved_pc = ctx->base.pc_next; in save_cpu_state()
1284 if (ctx->hflags != ctx->saved_hflags) { in save_cpu_state()
1285 tcg_gen_movi_i32(hflags, ctx->hflags); in save_cpu_state()
1286 ctx->saved_hflags = ctx->hflags; in save_cpu_state()
1287 switch (ctx->hflags & MIPS_HFLAG_BMASK_BASE) { in save_cpu_state()
1293 tcg_gen_movi_tl(btarget, ctx->btarget); in save_cpu_state()
1301 ctx->saved_hflags = ctx->hflags; in restore_cpu_state()
1302 switch (ctx->hflags & MIPS_HFLAG_BMASK_BASE) { in restore_cpu_state()
1308 ctx->btarget = env->btarget; in restore_cpu_state()
1318 ctx->base.is_jmp = DISAS_NORETURN; in generate_exception_err()
1349 if (ctx->hflags & MIPS_HFLAG_FRE) { in gen_load_fpr32()
1358 if (ctx->hflags & MIPS_HFLAG_FRE) { in gen_store_fpr32()
1368 if (ctx->hflags & MIPS_HFLAG_F64) { in gen_load_fpr32h()
1377 if (ctx->hflags & MIPS_HFLAG_F64) { in gen_store_fpr32h()
1388 if (ctx->hflags & MIPS_HFLAG_F64) { in gen_load_fpr64()
1397 if (ctx->hflags & MIPS_HFLAG_F64) { in gen_store_fpr64()
1423 if (ctx->hflags & MIPS_HFLAG_AWRAP) { in gen_op_addr_add()
1434 if (ctx->hflags & MIPS_HFLAG_AWRAP) { in gen_op_addr_addi()
1447 if (ctx->hflags & MIPS_HFLAG_AWRAP) { in addr_add()
1454 /* Sign-extract the low 32-bits to a target_long. */
1464 /* Sign-extract the high 32-bits to a target_long. */
1476 if (unlikely(!(ctx->hflags & MIPS_HFLAG_CP0))) { in check_cp0_enabled()
1485 if (unlikely(!(ctx->hflags & MIPS_HFLAG_FPU))) { in check_cp1_enabled()
1497 if (unlikely(!(ctx->hflags & MIPS_HFLAG_COP1X))) { in check_cop1x()
1503 * Verify that the processor is running with 64-bit floating-point
1508 if (unlikely(~ctx->hflags & MIPS_HFLAG_F64)) { in check_cp1_64bitmode()
1517 * even-odd pair of adjacent coprocessor general registers. When the FR bit
1526 if (unlikely(!(ctx->hflags & MIPS_HFLAG_F64) && (regs & 1))) { in check_cp1_registers()
1537 if (unlikely(!(ctx->hflags & MIPS_HFLAG_DSP))) { in check_dsp()
1538 if (ctx->insn_flags & ASE_DSP) { in check_dsp()
1548 if (unlikely(!(ctx->hflags & MIPS_HFLAG_DSP_R2))) { in check_dsp_r2()
1549 if (ctx->insn_flags & ASE_DSP) { in check_dsp_r2()
1559 if (unlikely(!(ctx->hflags & MIPS_HFLAG_DSP_R3))) { in check_dsp_r3()
1560 if (ctx->insn_flags & ASE_DSP) { in check_dsp_r3()
1574 if (unlikely(!(ctx->insn_flags & flags))) { in check_insn()
1586 if (unlikely(ctx->insn_flags & flags)) { in check_insn_opc_removed()
1608 * CPU does not support 64-bit paired-single (PS) floating point data type.
1612 if (unlikely(!ctx->ps)) { in check_ps()
1620 return ctx->hflags & MIPS_HFLAG_64; in decode_64bit_enabled()
1625 * 64-bit or 64-bit instructions are not enabled.
1637 if (unlikely(!ctx->mvh)) { in check_mvh()
1649 if (unlikely(ctx->CP0_Config5 & (1 << CP0C5_XNP))) { in check_xnp()
1661 if (unlikely(!(ctx->CP0_Config3 & (1 << CP0C3_PW)))) { in check_pw()
1673 if (unlikely(!(ctx->CP0_Config3 & (1 << CP0C3_MT)))) { in check_mt()
1687 if (unlikely(!(ctx->hflags & MIPS_HFLAG_CP0))) { in check_cp0_mt()
1690 if (unlikely(!(ctx->CP0_Config3 & (1 << CP0C3_MT)))) { in check_cp0_mt()
1703 if (unlikely(ctx->CP0_Config5 & (1 << CP0C5_NMS))) { in check_nms()
1715 if (unlikely((ctx->CP0_Config5 & (1 << CP0C5_NMS)) && in check_nms_dl_il_sl_tl_l2c()
1716 !(ctx->CP0_Config1 & (1 << CP0C1_DL)) && in check_nms_dl_il_sl_tl_l2c()
1717 !(ctx->CP0_Config1 & (1 << CP0C1_IL)) && in check_nms_dl_il_sl_tl_l2c()
1718 !(ctx->CP0_Config2 & (1 << CP0C2_SL)) && in check_nms_dl_il_sl_tl_l2c()
1719 !(ctx->CP0_Config2 & (1 << CP0C2_TL)) && in check_nms_dl_il_sl_tl_l2c()
1720 !(ctx->CP0_Config5 & (1 << CP0C5_L2C)))) { in check_nms_dl_il_sl_tl_l2c()
1731 if (unlikely(!(ctx->CP0_Config5 & (1 << CP0C5_EVA)))) { in check_eva()
1739 * calling interface for 32 and 64-bit FPRs. No sense in changing
1929 tcg_gen_qemu_ld_tl(ret, arg1, ctx->mem_idx, memop); \
1961 target_ulong pc = ctx->base.pc_next; in pc_relative_pc()
1963 if (ctx->hflags & MIPS_HFLAG_BMASK) { in pc_relative_pc()
1964 int branch_bytes = ctx->hflags & MIPS_HFLAG_BDS16 ? 2 : 4; in pc_relative_pc()
1966 pc -= branch_bytes; in pc_relative_pc()
1977 int sizem1 = memop_size(mop) - 1; in gen_lxl()
1994 tcg_gen_shl_tl(t1, tcg_constant_tl(-1), t1); in gen_lxl()
2004 int sizem1 = size - 1; in gen_lxr()
2021 tcg_gen_xori_tl(t1, t1, size * 8 - 1); in gen_lxr()
2032 int mem_idx = ctx->mem_idx; in gen_ld()
2034 if (rt == 0 && ctx->insn_flags & (INSN_LOONGSON2E | INSN_LOONGSON2F | in gen_ld()
2051 ctx->default_tcg_memop_mask); in gen_ld()
2056 ctx->default_tcg_memop_mask); in gen_ld()
2094 ctx->default_tcg_memop_mask); in gen_ld()
2102 ctx->default_tcg_memop_mask); in gen_ld()
2110 ctx->default_tcg_memop_mask); in gen_ld()
2164 int mem_idx = ctx->mem_idx; in gen_st()
2172 ctx->default_tcg_memop_mask); in gen_st()
2186 ctx->default_tcg_memop_mask); in gen_st()
2193 ctx->default_tcg_memop_mask); in gen_st()
2238 eva ? MIPS_HFLAG_UM : ctx->mem_idx, tcg_mo); in gen_st_cond()
2257 tcg_gen_qemu_ld_i32(fp0, t0, ctx->mem_idx, mo_endian(ctx) | MO_SL | in gen_flt_ldst()
2258 ctx->default_tcg_memop_mask); in gen_flt_ldst()
2266 tcg_gen_qemu_st_i32(fp0, t0, ctx->mem_idx, mo_endian(ctx) | MO_UL | in gen_flt_ldst()
2267 ctx->default_tcg_memop_mask); in gen_flt_ldst()
2273 tcg_gen_qemu_ld_i64(fp0, t0, ctx->mem_idx, mo_endian(ctx) | MO_UQ | in gen_flt_ldst()
2274 ctx->default_tcg_memop_mask); in gen_flt_ldst()
2282 tcg_gen_qemu_st_i64(fp0, t0, ctx->mem_idx, mo_endian(ctx) | MO_UQ | in gen_flt_ldst()
2283 ctx->default_tcg_memop_mask); in gen_flt_ldst()
2298 if (ctx->CP0_Config1 & (1 << CP0C1_FP)) { in gen_cop1_ldst()
2424 if (rs != 0 && (ctx->insn_flags & ISA_MIPS_R6)) { in gen_logic_imm()
2955 offset = sextract32(ctx->opcode << 2, 0, 21); in gen_pcrel()
2961 offset = sextract32(ctx->opcode << 2, 0, 21); in gen_pcrel()
2963 gen_r6_ld(addr, rs, ctx->mem_idx, mo_endian(ctx) | MO_SL); in gen_pcrel()
2968 offset = sextract32(ctx->opcode << 2, 0, 21); in gen_pcrel()
2970 gen_r6_ld(addr, rs, ctx->mem_idx, mo_endian(ctx) | MO_UL); in gen_pcrel()
2977 offset = sextract32(ctx->opcode, 0, 16) << 16; in gen_pcrel()
2984 offset = sextract32(ctx->opcode, 0, 16) << 16; in gen_pcrel()
2995 offset = sextract32(ctx->opcode << 3, 0, 21); in gen_pcrel()
2997 gen_r6_ld(addr, rs, ctx->mem_idx, mo_endian(ctx) | MO_UQ); in gen_pcrel()
3032 tcg_gen_setcondi_tl(TCG_COND_EQ, t3, t1, -1); in gen_r6_muldiv()
3048 tcg_gen_setcondi_tl(TCG_COND_EQ, t3, t1, -1); in gen_r6_muldiv()
3122 tcg_gen_setcondi_tl(TCG_COND_EQ, t2, t0, -1LL << 63); in gen_r6_muldiv()
3123 tcg_gen_setcondi_tl(TCG_COND_EQ, t3, t1, -1LL); in gen_r6_muldiv()
3135 tcg_gen_setcondi_tl(TCG_COND_EQ, t2, t0, -1LL << 63); in gen_r6_muldiv()
3136 tcg_gen_setcondi_tl(TCG_COND_EQ, t3, t1, -1LL); in gen_r6_muldiv()
3203 tcg_gen_setcondi_tl(TCG_COND_EQ, t3, t1, -1); in gen_div1_tx79()
3258 tcg_gen_setcondi_tl(TCG_COND_EQ, t3, t1, -1); in gen_muldiv()
3309 tcg_gen_setcondi_tl(TCG_COND_EQ, t2, t0, -1LL << 63); in gen_muldiv()
3310 tcg_gen_setcondi_tl(TCG_COND_EQ, t3, t1, -1LL); in gen_muldiv()
3404 * architectures are special three-operand variants with the syntax
3410 * (rd, LO, HI) <- rs * rt
3418 * (rd, LO, HI) <- (LO, HI) + rs * rt
3420 * where the low-order 32-bits of the result is placed into both the
3421 * GPR rd and the special register LO. The high-order 32-bits of the
3551 tcg_gen_subi_tl(t0, t0, TARGET_LONG_BITS - 32); in gen_cl()
3571 opc = MASK_LMMI(ctx->opcode); in gen_loongson_multimedia()
3808 tcg_gen_andi_i64(t1, t1, shift_max - 1); in gen_loongson_multimedia()
3818 * Since SRA is UndefinedResult without sign-extended inputs, in gen_loongson_multimedia()
3824 /* We want to shift in zeros for SRL; zero-extend first. */ in gen_loongson_multimedia()
3909 int cc = (ctx->opcode >> 8) & 0x7; in gen_loongson_multimedia()
3934 int lsq_rt1 = ctx->opcode & 0x1f; in gen_loongson_lswc2()
3935 int lsq_offset = sextract32(ctx->opcode, 6, 9) << 4; in gen_loongson_lswc2()
3937 int shf_offset = sextract32(ctx->opcode, 6, 8); in gen_loongson_lswc2()
3941 switch (MASK_LOONGSON_GSLSQ(ctx->opcode)) { in gen_loongson_lswc2()
3946 tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, mo_endian(ctx) | MO_UQ | in gen_loongson_lswc2()
3947 ctx->default_tcg_memop_mask); in gen_loongson_lswc2()
3949 tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, mo_endian(ctx) | MO_UQ | in gen_loongson_lswc2()
3950 ctx->default_tcg_memop_mask); in gen_loongson_lswc2()
3958 tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, mo_endian(ctx) | MO_UQ | in gen_loongson_lswc2()
3959 ctx->default_tcg_memop_mask); in gen_loongson_lswc2()
3961 tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, mo_endian(ctx) | MO_UQ | in gen_loongson_lswc2()
3962 ctx->default_tcg_memop_mask); in gen_loongson_lswc2()
3970 tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, mo_endian(ctx) | MO_UQ | in gen_loongson_lswc2()
3971 ctx->default_tcg_memop_mask); in gen_loongson_lswc2()
3974 tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, mo_endian(ctx) | MO_UQ | in gen_loongson_lswc2()
3975 ctx->default_tcg_memop_mask); in gen_loongson_lswc2()
3982 tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, mo_endian(ctx) | MO_UQ | in gen_loongson_lswc2()
3983 ctx->default_tcg_memop_mask); in gen_loongson_lswc2()
3986 tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, mo_endian(ctx) | MO_UQ | in gen_loongson_lswc2()
3987 ctx->default_tcg_memop_mask); in gen_loongson_lswc2()
3991 switch (MASK_LOONGSON_GSSHFLS(ctx->opcode)) { in gen_loongson_lswc2()
3999 gen_lxl(ctx, t1, t0, ctx->mem_idx, mo_endian(ctx) | MO_UL); in gen_loongson_lswc2()
4010 gen_lxr(ctx, t1, t0, ctx->mem_idx, mo_endian(ctx) | MO_UL); in gen_loongson_lswc2()
4020 gen_lxl(ctx, t1, t0, ctx->mem_idx, mo_endian(ctx) | MO_UQ); in gen_loongson_lswc2()
4028 gen_lxr(ctx, t1, t0, ctx->mem_idx, mo_endian(ctx) | MO_UQ); in gen_loongson_lswc2()
4039 switch (MASK_LOONGSON_GSSHFLS(ctx->opcode)) { in gen_loongson_lswc2()
4047 gen_helper_0e2i(swl, t1, t0, ctx->mem_idx); in gen_loongson_lswc2()
4056 gen_helper_0e2i(swr, t1, t0, ctx->mem_idx); in gen_loongson_lswc2()
4064 gen_helper_0e2i(sdl, t1, t0, ctx->mem_idx); in gen_loongson_lswc2()
4071 gen_helper_0e2i(sdr, t1, t0, ctx->mem_idx); in gen_loongson_lswc2()
4091 int offset = sextract32(ctx->opcode, 3, 8); in gen_loongson_lsdc2()
4092 uint32_t opc = MASK_LOONGSON_LSDC2(ctx->opcode); in gen_loongson_lsdc2()
4096 /* Pre-conditions */ in gen_loongson_lsdc2()
4142 tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_SB); in gen_loongson_lsdc2()
4146 tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, mo_endian(ctx) | MO_SW | in gen_loongson_lsdc2()
4147 ctx->default_tcg_memop_mask); in gen_loongson_lsdc2()
4155 tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, mo_endian(ctx) | MO_SL | in gen_loongson_lsdc2()
4156 ctx->default_tcg_memop_mask); in gen_loongson_lsdc2()
4165 tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, mo_endian(ctx) | MO_UQ | in gen_loongson_lsdc2()
4166 ctx->default_tcg_memop_mask); in gen_loongson_lsdc2()
4176 tcg_gen_qemu_ld_i32(fp0, t0, ctx->mem_idx, mo_endian(ctx) | MO_SL | in gen_loongson_lsdc2()
4177 ctx->default_tcg_memop_mask); in gen_loongson_lsdc2()
4186 tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, mo_endian(ctx) | MO_UQ | in gen_loongson_lsdc2()
4187 ctx->default_tcg_memop_mask); in gen_loongson_lsdc2()
4194 tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_SB); in gen_loongson_lsdc2()
4199 tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, mo_endian(ctx) | MO_UW | in gen_loongson_lsdc2()
4200 ctx->default_tcg_memop_mask); in gen_loongson_lsdc2()
4205 tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, mo_endian(ctx) | MO_UL | in gen_loongson_lsdc2()
4206 ctx->default_tcg_memop_mask); in gen_loongson_lsdc2()
4212 tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, mo_endian(ctx) | MO_UQ | in gen_loongson_lsdc2()
4213 ctx->default_tcg_memop_mask); in gen_loongson_lsdc2()
4219 tcg_gen_qemu_st_i32(fp0, t0, ctx->mem_idx, mo_endian(ctx) | MO_UL | in gen_loongson_lsdc2()
4220 ctx->default_tcg_memop_mask); in gen_loongson_lsdc2()
4226 tcg_gen_qemu_st_i64(t1, t0, ctx->mem_idx, mo_endian(ctx) | MO_UQ | in gen_loongson_lsdc2()
4227 ctx->default_tcg_memop_mask); in gen_loongson_lsdc2()
4333 if (ctx->base.pc_next != ctx->saved_pc) { in gen_trap()
4334 gen_save_pc(ctx->base.pc_next); in gen_trap()
4336 if (ctx->hflags != ctx->saved_hflags) { in gen_trap()
4337 tcg_gen_movi_i32(hflags, ctx->hflags); in gen_trap()
4346 if (translator_use_goto_tb(&ctx->base, dest)) { in gen_goto_tb()
4349 tcg_gen_exit_tb(ctx->base.tb, n); in gen_goto_tb()
4362 target_ulong btgt = -1; in gen_compute_branch()
4368 if (ctx->hflags & MIPS_HFLAG_BMASK) { in gen_compute_branch()
4371 VADDR_PRIx "\n", ctx->base.pc_next); in gen_compute_branch()
4389 btgt = ctx->base.pc_next + insn_bytes + offset; in gen_compute_branch()
4408 btgt = ctx->base.pc_next + insn_bytes + offset; in gen_compute_branch()
4418 btgt = ctx->base.pc_next + insn_bytes + offset; in gen_compute_branch()
4424 int jal_mask = ctx->hflags & MIPS_HFLAG_M16 ? 0xF8000000 in gen_compute_branch()
4426 btgt = ((ctx->base.pc_next + insn_bytes) & jal_mask) in gen_compute_branch()
4432 btgt = ((ctx->base.pc_next + insn_bytes) & (int32_t)0xF0000000) | in gen_compute_branch()
4464 ctx->hflags |= MIPS_HFLAG_B; in gen_compute_branch()
4470 ctx->hflags |= MIPS_HFLAG_B; in gen_compute_branch()
4483 btgt = ctx->base.pc_next + insn_bytes + delayslot_size; in gen_compute_branch()
4484 ctx->hflags |= MIPS_HFLAG_B; in gen_compute_branch()
4487 tcg_gen_movi_tl(cpu_gpr[31], ctx->base.pc_next + 8); in gen_compute_branch()
4489 ctx->base.pc_next += 4; in gen_compute_branch()
4495 ctx->base.pc_next += 4; in gen_compute_branch()
4498 ctx->hflags |= MIPS_HFLAG_B; in gen_compute_branch()
4501 ctx->hflags |= MIPS_HFLAG_BX; in gen_compute_branch()
4505 ctx->hflags |= MIPS_HFLAG_B; in gen_compute_branch()
4508 ctx->hflags |= MIPS_HFLAG_BR; in gen_compute_branch()
4512 ctx->hflags |= MIPS_HFLAG_BR; in gen_compute_branch()
4577 ctx->hflags |= MIPS_HFLAG_BC; in gen_compute_branch()
4583 ctx->hflags |= MIPS_HFLAG_BL; in gen_compute_branch()
4592 ctx->btarget = btgt; in gen_compute_branch()
4596 ctx->hflags |= MIPS_HFLAG_BDS16; in gen_compute_branch()
4599 ctx->hflags |= MIPS_HFLAG_BDS32; in gen_compute_branch()
4605 int lowbit = !!(ctx->hflags & MIPS_HFLAG_M16); in gen_compute_branch()
4608 ctx->base.pc_next + post_delay + lowbit); in gen_compute_branch()
4613 ctx->hflags |= MIPS_HFLAG_B16; in gen_compute_branch()
4636 * so this is a simple sign-extension. in gen_bitops()
4661 tcg_gen_deposit_tl(t0, t0, t1, lsb, msb - lsb + 1); in gen_bitops()
4676 tcg_gen_deposit_tl(t0, t0, t1, lsb, msb - lsb + 1); in gen_bitops()
4789 tcg_gen_shri_i64(t2, t2, 32 - bits); in gen_align_bits()
4796 tcg_gen_shri_tl(t1, t1, 64 - bits); in gen_align_bits()
4909 static void gen_mfhc0(DisasContext *ctx, TCGv arg, int reg, int sel) in gen_mfhc0() argument
4915 switch (sel) { in gen_mfhc0()
4917 CP0_CHECK(ctx->hflags & MIPS_HFLAG_ELPA); in gen_mfhc0()
4926 switch (sel) { in gen_mfhc0()
4928 CP0_CHECK(ctx->hflags & MIPS_HFLAG_ELPA); in gen_mfhc0()
4937 switch (sel) { in gen_mfhc0()
4940 ctx->CP0_LLAddr_shift); in gen_mfhc0()
4944 CP0_CHECK(ctx->mrp); in gen_mfhc0()
4953 switch (sel) { in gen_mfhc0()
4963 CP0_CHECK(ctx->mi); in gen_mfhc0()
4964 gen_mfhc0_load64(arg, offsetof(CPUMIPSState, CP0_WatchHi[sel]), 0); in gen_mfhc0()
4972 switch (sel) { in gen_mfhc0()
4987 trace_mips_translate_c0("mfhc0", register_name, reg, sel); in gen_mfhc0()
4991 qemu_log_mask(LOG_UNIMP, "mfhc0 %s (reg %d sel %d)\n", in gen_mfhc0()
4992 register_name, reg, sel); in gen_mfhc0()
4996 static void gen_mthc0(DisasContext *ctx, TCGv arg, int reg, int sel) in gen_mthc0() argument
4999 uint64_t mask = ctx->PAMask >> 36; in gen_mthc0()
5003 switch (sel) { in gen_mthc0()
5005 CP0_CHECK(ctx->hflags & MIPS_HFLAG_ELPA); in gen_mthc0()
5015 switch (sel) { in gen_mthc0()
5017 CP0_CHECK(ctx->hflags & MIPS_HFLAG_ELPA); in gen_mthc0()
5027 switch (sel) { in gen_mthc0()
5030 * LLAddr is read-only (the only exception is bit 0 if LLB is in gen_mthc0()
5038 CP0_CHECK(ctx->mrp); in gen_mthc0()
5047 switch (sel) { in gen_mthc0()
5057 CP0_CHECK(ctx->mi); in gen_mthc0()
5058 gen_helper_0e1i(mthc0_watchhi, arg, sel); in gen_mthc0()
5066 switch (sel) { in gen_mthc0()
5082 trace_mips_translate_c0("mthc0", register_name, reg, sel); in gen_mthc0()
5086 qemu_log_mask(LOG_UNIMP, "mthc0 %s (reg %d sel %d)\n", in gen_mthc0()
5087 register_name, reg, sel); in gen_mthc0()
5092 if (ctx->insn_flags & ISA_MIPS_R6) { in gen_mfc0_unimplemented()
5099 static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel) in gen_mfc0() argument
5103 if (sel != 0) { in gen_mfc0()
5109 switch (sel) { in gen_mfc0()
5130 CP0_CHECK(ctx->vp); in gen_mfc0()
5139 switch (sel) { in gen_mfc0()
5141 CP0_CHECK(!(ctx->insn_flags & ISA_MIPS_R6)); in gen_mfc0()
5185 switch (sel) { in gen_mfc0()
5192 if (ctx->rxi) { in gen_mfc0()
5242 switch (sel) { in gen_mfc0()
5249 if (ctx->rxi) { in gen_mfc0()
5260 CP0_CHECK(ctx->vp); in gen_mfc0()
5269 switch (sel) { in gen_mfc0()
5281 CP0_CHECK(ctx->ulri); in gen_mfc0()
5288 CP0_CHECK(ctx->mi); in gen_mfc0()
5297 switch (sel) { in gen_mfc0()
5308 CP0_CHECK(ctx->sc); in gen_mfc0()
5314 CP0_CHECK(ctx->sc); in gen_mfc0()
5320 CP0_CHECK(ctx->sc); in gen_mfc0()
5345 switch (sel) { in gen_mfc0()
5385 switch (sel) { in gen_mfc0()
5396 switch (sel) { in gen_mfc0()
5403 CP0_CHECK(ctx->bi); in gen_mfc0()
5408 CP0_CHECK(ctx->bp); in gen_mfc0()
5413 CP0_CHECK(ctx->bi); in gen_mfc0()
5423 switch (sel) { in gen_mfc0()
5426 translator_io_start(&ctx->base); in gen_mfc0()
5434 gen_save_pc(ctx->base.pc_next + 4); in gen_mfc0()
5435 ctx->base.is_jmp = DISAS_EXIT; in gen_mfc0()
5443 switch (sel) { in gen_mfc0()
5454 switch (sel) { in gen_mfc0()
5465 switch (sel) { in gen_mfc0()
5490 switch (sel) { in gen_mfc0()
5500 switch (sel) { in gen_mfc0()
5511 switch (sel) { in gen_mfc0()
5524 CP0_CHECK(ctx->cmgcr); in gen_mfc0()
5534 switch (sel) { in gen_mfc0()
5573 switch (sel) { in gen_mfc0()
5579 CP0_CHECK(ctx->mrp); in gen_mfc0()
5584 CP0_CHECK(ctx->mrp); in gen_mfc0()
5593 switch (sel) { in gen_mfc0()
5602 CP0_CHECK(ctx->CP0_Config1 & (1 << CP0C1_WR)); in gen_mfc0()
5603 gen_helper_1e0i(mfc0_watchlo, arg, sel); in gen_mfc0()
5611 switch (sel) { in gen_mfc0()
5620 CP0_CHECK(ctx->CP0_Config1 & (1 << CP0C1_WR)); in gen_mfc0()
5621 gen_helper_1e0i(mfc0_watchhi, arg, sel); in gen_mfc0()
5629 switch (sel) { in gen_mfc0()
5643 /* Officially reserved, but sel 0 is used for R1x000 framemask */ in gen_mfc0()
5644 CP0_CHECK(!(ctx->insn_flags & ISA_MIPS_R6)); in gen_mfc0()
5645 switch (sel) { in gen_mfc0()
5659 switch (sel) { in gen_mfc0()
5694 switch (sel) { in gen_mfc0()
5706 switch (sel) { in gen_mfc0()
5744 switch (sel) { in gen_mfc0()
5754 switch (sel) { in gen_mfc0()
5764 switch (sel) { in gen_mfc0()
5788 switch (sel) { in gen_mfc0()
5808 switch (sel) { in gen_mfc0()
5819 switch (sel) { in gen_mfc0()
5831 CP0_CHECK(ctx->kscrexist & (1 << sel)); in gen_mfc0()
5833 offsetof(CPUMIPSState, CP0_KScratch[sel - 2])); in gen_mfc0()
5844 trace_mips_translate_c0("mfc0", register_name, reg, sel); in gen_mfc0()
5848 qemu_log_mask(LOG_UNIMP, "mfc0 %s (reg %d sel %d)\n", in gen_mfc0()
5849 register_name, reg, sel); in gen_mfc0()
5853 static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel) in gen_mtc0() argument
5858 if (sel != 0) { in gen_mtc0()
5862 icount = translator_io_start(&ctx->base); in gen_mtc0()
5866 switch (sel) { in gen_mtc0()
5887 CP0_CHECK(ctx->vp); in gen_mtc0()
5896 switch (sel) { in gen_mtc0()
5943 switch (sel) { in gen_mtc0()
5988 switch (sel) { in gen_mtc0()
5994 CP0_CHECK(ctx->vp); in gen_mtc0()
6003 switch (sel) { in gen_mtc0()
6014 CP0_CHECK(ctx->ulri); in gen_mtc0()
6020 CP0_CHECK(ctx->mi); in gen_mtc0()
6029 switch (sel) { in gen_mtc0()
6038 ctx->base.is_jmp = DISAS_STOP; in gen_mtc0()
6041 CP0_CHECK(ctx->sc); in gen_mtc0()
6046 CP0_CHECK(ctx->sc); in gen_mtc0()
6051 CP0_CHECK(ctx->sc); in gen_mtc0()
6075 switch (sel) { in gen_mtc0()
6115 switch (sel) { in gen_mtc0()
6119 ctx->base.is_jmp = DISAS_STOP; in gen_mtc0()
6127 switch (sel) { in gen_mtc0()
6149 switch (sel) { in gen_mtc0()
6159 switch (sel) { in gen_mtc0()
6169 switch (sel) { in gen_mtc0()
6180 switch (sel) { in gen_mtc0()
6185 gen_save_pc(ctx->base.pc_next + 4); in gen_mtc0()
6186 ctx->base.is_jmp = DISAS_EXIT; in gen_mtc0()
6193 ctx->base.is_jmp = DISAS_STOP; in gen_mtc0()
6200 ctx->base.is_jmp = DISAS_STOP; in gen_mtc0()
6207 ctx->base.is_jmp = DISAS_STOP; in gen_mtc0()
6215 switch (sel) { in gen_mtc0()
6224 gen_save_pc(ctx->base.pc_next + 4); in gen_mtc0()
6225 ctx->base.is_jmp = DISAS_EXIT; in gen_mtc0()
6233 switch (sel) { in gen_mtc0()
6243 switch (sel) { in gen_mtc0()
6258 switch (sel) { in gen_mtc0()
6263 ctx->base.is_jmp = DISAS_STOP; in gen_mtc0()
6273 ctx->base.is_jmp = DISAS_STOP; in gen_mtc0()
6279 ctx->base.is_jmp = DISAS_STOP; in gen_mtc0()
6284 ctx->base.is_jmp = DISAS_STOP; in gen_mtc0()
6290 ctx->base.is_jmp = DISAS_STOP; in gen_mtc0()
6307 switch (sel) { in gen_mtc0()
6313 CP0_CHECK(ctx->mrp); in gen_mtc0()
6318 CP0_CHECK(ctx->mrp); in gen_mtc0()
6327 switch (sel) { in gen_mtc0()
6336 CP0_CHECK(ctx->CP0_Config1 & (1 << CP0C1_WR)); in gen_mtc0()
6337 gen_helper_0e1i(mtc0_watchlo, arg, sel); in gen_mtc0()
6345 switch (sel) { in gen_mtc0()
6354 CP0_CHECK(ctx->CP0_Config1 & (1 << CP0C1_WR)); in gen_mtc0()
6355 gen_helper_0e1i(mtc0_watchhi, arg, sel); in gen_mtc0()
6363 switch (sel) { in gen_mtc0()
6376 /* Officially reserved, but sel 0 is used for R1x000 framemask */ in gen_mtc0()
6377 CP0_CHECK(!(ctx->insn_flags & ISA_MIPS_R6)); in gen_mtc0()
6378 switch (sel) { in gen_mtc0()
6392 switch (sel) { in gen_mtc0()
6396 gen_save_pc(ctx->base.pc_next + 4); in gen_mtc0()
6397 ctx->base.is_jmp = DISAS_EXIT; in gen_mtc0()
6405 ctx->base.is_jmp = DISAS_STOP; in gen_mtc0()
6412 ctx->base.is_jmp = DISAS_STOP; in gen_mtc0()
6416 ctx->base.is_jmp = DISAS_STOP; in gen_mtc0()
6421 ctx->base.is_jmp = DISAS_STOP; in gen_mtc0()
6427 ctx->base.is_jmp = DISAS_STOP; in gen_mtc0()
6434 ctx->base.is_jmp = DISAS_STOP; in gen_mtc0()
6442 switch (sel) { in gen_mtc0()
6453 switch (sel) { in gen_mtc0()
6491 switch (sel) { in gen_mtc0()
6494 ctx->base.is_jmp = DISAS_STOP; in gen_mtc0()
6502 switch (sel) { in gen_mtc0()
6512 switch (sel) { in gen_mtc0()
6532 switch (sel) { in gen_mtc0()
6548 register_name = "invalid sel"; in gen_mtc0()
6553 switch (sel) { in gen_mtc0()
6563 switch (sel) { in gen_mtc0()
6575 CP0_CHECK(ctx->kscrexist & (1 << sel)); in gen_mtc0()
6577 offsetof(CPUMIPSState, CP0_KScratch[sel - 2])); in gen_mtc0()
6587 trace_mips_translate_c0("mtc0", register_name, reg, sel); in gen_mtc0()
6595 gen_save_pc(ctx->base.pc_next + 4); in gen_mtc0()
6596 ctx->base.is_jmp = DISAS_EXIT; in gen_mtc0()
6601 qemu_log_mask(LOG_UNIMP, "mtc0 %s (reg %d sel %d)\n", in gen_mtc0()
6602 register_name, reg, sel); in gen_mtc0()
6606 static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel) in gen_dmfc0() argument
6610 if (sel != 0) { in gen_dmfc0()
6616 switch (sel) { in gen_dmfc0()
6637 CP0_CHECK(ctx->vp); in gen_dmfc0()
6646 switch (sel) { in gen_dmfc0()
6648 CP0_CHECK(!(ctx->insn_flags & ISA_MIPS_R6)); in gen_dmfc0()
6695 switch (sel) { in gen_dmfc0()
6741 switch (sel) { in gen_dmfc0()
6747 CP0_CHECK(ctx->vp); in gen_dmfc0()
6756 switch (sel) { in gen_dmfc0()
6767 CP0_CHECK(ctx->ulri); in gen_dmfc0()
6773 CP0_CHECK(ctx->mi); in gen_dmfc0()
6782 switch (sel) { in gen_dmfc0()
6793 CP0_CHECK(ctx->sc); in gen_dmfc0()
6798 CP0_CHECK(ctx->sc); in gen_dmfc0()
6803 CP0_CHECK(ctx->sc); in gen_dmfc0()
6827 switch (sel) { in gen_dmfc0()
6867 switch (sel) { in gen_dmfc0()
6878 switch (sel) { in gen_dmfc0()
6884 CP0_CHECK(ctx->bi); in gen_dmfc0()
6889 CP0_CHECK(ctx->bp); in gen_dmfc0()
6894 CP0_CHECK(ctx->bi); in gen_dmfc0()
6904 switch (sel) { in gen_dmfc0()
6907 translator_io_start(&ctx->base); in gen_dmfc0()
6914 gen_save_pc(ctx->base.pc_next + 4); in gen_dmfc0()
6915 ctx->base.is_jmp = DISAS_EXIT; in gen_dmfc0()
6923 switch (sel) { in gen_dmfc0()
6933 switch (sel) { in gen_dmfc0()
6944 switch (sel) { in gen_dmfc0()
6969 switch (sel) { in gen_dmfc0()
6979 switch (sel) { in gen_dmfc0()
6989 switch (sel) { in gen_dmfc0()
7001 CP0_CHECK(ctx->cmgcr); in gen_dmfc0()
7010 switch (sel) { in gen_dmfc0()
7049 switch (sel) { in gen_dmfc0()
7055 CP0_CHECK(ctx->mrp); in gen_dmfc0()
7060 CP0_CHECK(ctx->mrp); in gen_dmfc0()
7069 switch (sel) { in gen_dmfc0()
7078 CP0_CHECK(ctx->CP0_Config1 & (1 << CP0C1_WR)); in gen_dmfc0()
7079 gen_helper_1e0i(dmfc0_watchlo, arg, sel); in gen_dmfc0()
7087 switch (sel) { in gen_dmfc0()
7096 CP0_CHECK(ctx->CP0_Config1 & (1 << CP0C1_WR)); in gen_dmfc0()
7097 gen_helper_1e0i(dmfc0_watchhi, arg, sel); in gen_dmfc0()
7105 switch (sel) { in gen_dmfc0()
7116 /* Officially reserved, but sel 0 is used for R1x000 framemask */ in gen_dmfc0()
7117 CP0_CHECK(!(ctx->insn_flags & ISA_MIPS_R6)); in gen_dmfc0()
7118 switch (sel) { in gen_dmfc0()
7132 switch (sel) { in gen_dmfc0()
7167 switch (sel) { in gen_dmfc0()
7178 switch (sel) { in gen_dmfc0()
7216 switch (sel) { in gen_dmfc0()
7226 switch (sel) { in gen_dmfc0()
7237 switch (sel) { in gen_dmfc0()
7257 switch (sel) { in gen_dmfc0()
7277 switch (sel) { in gen_dmfc0()
7287 switch (sel) { in gen_dmfc0()
7299 CP0_CHECK(ctx->kscrexist & (1 << sel)); in gen_dmfc0()
7301 offsetof(CPUMIPSState, CP0_KScratch[sel - 2])); in gen_dmfc0()
7311 trace_mips_translate_c0("dmfc0", register_name, reg, sel); in gen_dmfc0()
7315 qemu_log_mask(LOG_UNIMP, "dmfc0 %s (reg %d sel %d)\n", in gen_dmfc0()
7316 register_name, reg, sel); in gen_dmfc0()
7320 static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel) in gen_dmtc0() argument
7325 if (sel != 0) { in gen_dmtc0()
7329 icount = translator_io_start(&ctx->base); in gen_dmtc0()
7333 switch (sel) { in gen_dmtc0()
7354 CP0_CHECK(ctx->vp); in gen_dmtc0()
7363 switch (sel) { in gen_dmtc0()
7410 switch (sel) { in gen_dmtc0()
7455 switch (sel) { in gen_dmtc0()
7461 CP0_CHECK(ctx->vp); in gen_dmtc0()
7470 switch (sel) { in gen_dmtc0()
7481 CP0_CHECK(ctx->ulri); in gen_dmtc0()
7487 CP0_CHECK(ctx->mi); in gen_dmtc0()
7496 switch (sel) { in gen_dmtc0()
7507 CP0_CHECK(ctx->sc); in gen_dmtc0()
7512 CP0_CHECK(ctx->sc); in gen_dmtc0()
7517 CP0_CHECK(ctx->sc); in gen_dmtc0()
7541 switch (sel) { in gen_dmtc0()
7581 switch (sel) { in gen_dmtc0()
7585 ctx->base.is_jmp = DISAS_STOP; in gen_dmtc0()
7593 switch (sel) { in gen_dmtc0()
7615 switch (sel) { in gen_dmtc0()
7624 ctx->base.is_jmp = DISAS_STOP; in gen_dmtc0()
7627 switch (sel) { in gen_dmtc0()
7637 switch (sel) { in gen_dmtc0()
7647 ctx->base.is_jmp = DISAS_STOP; in gen_dmtc0()
7650 switch (sel) { in gen_dmtc0()
7655 gen_save_pc(ctx->base.pc_next + 4); in gen_dmtc0()
7656 ctx->base.is_jmp = DISAS_EXIT; in gen_dmtc0()
7663 ctx->base.is_jmp = DISAS_STOP; in gen_dmtc0()
7670 ctx->base.is_jmp = DISAS_STOP; in gen_dmtc0()
7677 ctx->base.is_jmp = DISAS_STOP; in gen_dmtc0()
7685 switch (sel) { in gen_dmtc0()
7694 gen_save_pc(ctx->base.pc_next + 4); in gen_dmtc0()
7695 ctx->base.is_jmp = DISAS_EXIT; in gen_dmtc0()
7703 switch (sel) { in gen_dmtc0()
7713 switch (sel) { in gen_dmtc0()
7728 switch (sel) { in gen_dmtc0()
7733 ctx->base.is_jmp = DISAS_STOP; in gen_dmtc0()
7743 ctx->base.is_jmp = DISAS_STOP; in gen_dmtc0()
7749 ctx->base.is_jmp = DISAS_STOP; in gen_dmtc0()
7759 ctx->base.is_jmp = DISAS_STOP; in gen_dmtc0()
7768 switch (sel) { in gen_dmtc0()
7774 CP0_CHECK(ctx->mrp); in gen_dmtc0()
7779 CP0_CHECK(ctx->mrp); in gen_dmtc0()
7788 switch (sel) { in gen_dmtc0()
7797 CP0_CHECK(ctx->CP0_Config1 & (1 << CP0C1_WR)); in gen_dmtc0()
7798 gen_helper_0e1i(mtc0_watchlo, arg, sel); in gen_dmtc0()
7806 switch (sel) { in gen_dmtc0()
7815 CP0_CHECK(ctx->CP0_Config1 & (1 << CP0C1_WR)); in gen_dmtc0()
7816 gen_helper_0e1i(mtc0_watchhi, arg, sel); in gen_dmtc0()
7824 switch (sel) { in gen_dmtc0()
7835 /* Officially reserved, but sel 0 is used for R1x000 framemask */ in gen_dmtc0()
7836 CP0_CHECK(!(ctx->insn_flags & ISA_MIPS_R6)); in gen_dmtc0()
7837 switch (sel) { in gen_dmtc0()
7851 switch (sel) { in gen_dmtc0()
7855 gen_save_pc(ctx->base.pc_next + 4); in gen_dmtc0()
7856 ctx->base.is_jmp = DISAS_EXIT; in gen_dmtc0()
7863 ctx->base.is_jmp = DISAS_STOP; in gen_dmtc0()
7870 ctx->base.is_jmp = DISAS_STOP; in gen_dmtc0()
7877 ctx->base.is_jmp = DISAS_STOP; in gen_dmtc0()
7884 ctx->base.is_jmp = DISAS_STOP; in gen_dmtc0()
7891 ctx->base.is_jmp = DISAS_STOP; in gen_dmtc0()
7899 switch (sel) { in gen_dmtc0()
7910 switch (sel) { in gen_dmtc0()
7948 switch (sel) { in gen_dmtc0()
7951 ctx->base.is_jmp = DISAS_STOP; in gen_dmtc0()
7959 switch (sel) { in gen_dmtc0()
7969 switch (sel) { in gen_dmtc0()
7989 switch (sel) { in gen_dmtc0()
8005 register_name = "invalid sel"; in gen_dmtc0()
8010 switch (sel) { in gen_dmtc0()
8020 switch (sel) { in gen_dmtc0()
8032 CP0_CHECK(ctx->kscrexist & (1 << sel)); in gen_dmtc0()
8034 offsetof(CPUMIPSState, CP0_KScratch[sel - 2])); in gen_dmtc0()
8044 trace_mips_translate_c0("dmtc0", register_name, reg, sel); in gen_dmtc0()
8052 gen_save_pc(ctx->base.pc_next + 4); in gen_dmtc0()
8053 ctx->base.is_jmp = DISAS_EXIT; in gen_dmtc0()
8058 qemu_log_mask(LOG_UNIMP, "dmtc0 %s (reg %d sel %d)\n", in gen_dmtc0()
8059 register_name, reg, sel); in gen_dmtc0()
8064 int u, int sel, int h) in gen_mftr() argument
8066 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); in gen_mftr()
8069 if ((env->CP0_VPEConf0 & (1 << CP0VPEC0_MVP)) == 0 && in gen_mftr()
8070 ((env->tcs[other_tc].CP0_TCBind & (0xf << CP0TCBd_CurVPE)) != in gen_mftr()
8071 (env->active_tc.CP0_TCBind & (0xf << CP0TCBd_CurVPE)))) { in gen_mftr()
8072 tcg_gen_movi_tl(t0, -1); in gen_mftr()
8073 } else if ((env->CP0_VPEControl & (0xff << CP0VPECo_TargTC)) > in gen_mftr()
8074 (env->mvp->CP0_MVPConf0 & (0xff << CP0MVPC0_PTC))) { in gen_mftr()
8075 tcg_gen_movi_tl(t0, -1); in gen_mftr()
8079 switch (sel) { in gen_mftr()
8092 switch (sel) { in gen_mftr()
8115 gen_mfc0(ctx, t0, rt, sel); in gen_mftr()
8120 switch (sel) { in gen_mftr()
8125 gen_mfc0(ctx, t0, rt, sel); in gen_mftr()
8130 switch (sel) { in gen_mftr()
8135 gen_mfc0(ctx, t0, rt, sel); in gen_mftr()
8140 switch (sel) { in gen_mftr()
8150 switch (sel) { in gen_mftr()
8160 switch (sel) { in gen_mftr()
8170 switch (sel) { in gen_mftr()
8179 gen_helper_mftc0_configx(t0, tcg_env, tcg_constant_tl(sel)); in gen_mftr()
8187 switch (sel) { in gen_mftr()
8192 gen_mfc0(ctx, t0, rt, sel); in gen_mftr()
8197 gen_mfc0(ctx, t0, rt, sel); in gen_mftr()
8200 switch (sel) { in gen_mftr()
8278 trace_mips_translate_tr("mftr", rt, u, sel, h); in gen_mftr()
8283 LOG_DISAS("mftr (reg %d u %d sel %d h %d)\n", rt, u, sel, h); in gen_mftr()
8288 int u, int sel, int h) in gen_mttr() argument
8290 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); in gen_mttr()
8294 if ((env->CP0_VPEConf0 & (1 << CP0VPEC0_MVP)) == 0 && in gen_mttr()
8295 ((env->tcs[other_tc].CP0_TCBind & (0xf << CP0TCBd_CurVPE)) != in gen_mttr()
8296 (env->active_tc.CP0_TCBind & (0xf << CP0TCBd_CurVPE)))) { in gen_mttr()
8299 } else if ((env->CP0_VPEControl & (0xff << CP0VPECo_TargTC)) > in gen_mttr()
8300 (env->mvp->CP0_MVPConf0 & (0xff << CP0MVPC0_PTC))) { in gen_mttr()
8306 switch (sel) { in gen_mttr()
8319 switch (sel) { in gen_mttr()
8342 gen_mtc0(ctx, t0, rd, sel); in gen_mttr()
8347 switch (sel) { in gen_mttr()
8352 gen_mtc0(ctx, t0, rd, sel); in gen_mttr()
8357 switch (sel) { in gen_mttr()
8362 gen_mtc0(ctx, t0, rd, sel); in gen_mttr()
8367 switch (sel) { in gen_mttr()
8377 switch (sel) { in gen_mttr()
8387 switch (sel) { in gen_mttr()
8392 gen_mtc0(ctx, t0, rd, sel); in gen_mttr()
8397 gen_mtc0(ctx, t0, rd, sel); in gen_mttr()
8400 switch (sel) { in gen_mttr()
8470 ctx->base.is_jmp = DISAS_STOP; in gen_mttr()
8480 trace_mips_translate_tr("mttr", rd, u, sel, h); in gen_mttr()
8484 LOG_DISAS("mttr (reg %d u %d sel %d h %d)\n", rd, u, sel, h); in gen_mttr()
8500 gen_mfc0(ctx, cpu_gpr[rt], rd, ctx->opcode & 0x7); in gen_cp0()
8508 gen_mtc0(ctx, t0, rd, ctx->opcode & 0x7); in gen_cp0()
8519 gen_dmfc0(ctx, cpu_gpr[rt], rd, ctx->opcode & 0x7); in gen_cp0()
8528 gen_dmtc0(ctx, t0, rd, ctx->opcode & 0x7); in gen_cp0()
8539 gen_mfhc0(ctx, cpu_gpr[rt], rd, ctx->opcode & 0x7); in gen_cp0()
8547 gen_mthc0(ctx, t0, rd, ctx->opcode & 0x7); in gen_cp0()
8557 gen_mftr(env, ctx, rt, rd, (ctx->opcode >> 5) & 1, in gen_cp0()
8558 ctx->opcode & 0x7, (ctx->opcode >> 4) & 1); in gen_cp0()
8563 gen_mttr(env, ctx, rd, rt, (ctx->opcode >> 5) & 1, in gen_cp0()
8564 ctx->opcode & 0x7, (ctx->opcode >> 4) & 1); in gen_cp0()
8569 if (!env->tlb->helper_tlbwi) { in gen_cp0()
8576 if (ctx->ie >= 2) { in gen_cp0()
8577 if (!env->tlb->helper_tlbinv) { in gen_cp0()
8585 if (ctx->ie >= 2) { in gen_cp0()
8586 if (!env->tlb->helper_tlbinvf) { in gen_cp0()
8594 if (!env->tlb->helper_tlbwr) { in gen_cp0()
8601 if (!env->tlb->helper_tlbp) { in gen_cp0()
8608 if (!env->tlb->helper_tlbr) { in gen_cp0()
8614 if ((ctx->insn_flags & ISA_MIPS_R6) && in gen_cp0()
8615 (ctx->hflags & MIPS_HFLAG_BMASK)) { in gen_cp0()
8618 int bit_shift = (ctx->hflags & MIPS_HFLAG_M16) ? 16 : 6; in gen_cp0()
8619 if (ctx->opcode & (1 << bit_shift)) { in gen_cp0()
8630 ctx->base.is_jmp = DISAS_EXIT; in gen_cp0()
8636 if ((ctx->insn_flags & ISA_MIPS_R6) && in gen_cp0()
8637 (ctx->hflags & MIPS_HFLAG_BMASK)) { in gen_cp0()
8640 if (!(ctx->hflags & MIPS_HFLAG_DM)) { in gen_cp0()
8645 ctx->base.is_jmp = DISAS_EXIT; in gen_cp0()
8651 if ((ctx->insn_flags & ISA_MIPS_R6) && in gen_cp0()
8652 (ctx->hflags & MIPS_HFLAG_BMASK)) { in gen_cp0()
8656 ctx->base.pc_next += 4; in gen_cp0()
8658 ctx->base.pc_next -= 4; in gen_cp0()
8660 ctx->base.is_jmp = DISAS_NORETURN; in gen_cp0()
8679 if ((ctx->insn_flags & ISA_MIPS_R6) && (ctx->hflags & MIPS_HFLAG_BMASK)) { in gen_compute_branch1()
8688 btarget = ctx->base.pc_next + 4 + offset; in gen_compute_branch1()
8713 ctx->hflags |= MIPS_HFLAG_BL; in gen_compute_branch1()
8763 ctx->hflags |= MIPS_HFLAG_BC; in gen_compute_branch1()
8770 ctx->btarget = btarget; in gen_compute_branch1()
8771 ctx->hflags |= MIPS_HFLAG_BDS32; in gen_compute_branch1()
8782 if (ctx->hflags & MIPS_HFLAG_BMASK) { in gen_compute_branch1_r6()
8785 VADDR_PRIx "\n", ctx->base.pc_next); in gen_compute_branch1_r6()
8794 btarget = addr_add(ctx, ctx->base.pc_next + 4, offset); in gen_compute_branch1_r6()
8799 ctx->hflags |= MIPS_HFLAG_BC; in gen_compute_branch1_r6()
8803 ctx->hflags |= MIPS_HFLAG_BC; in gen_compute_branch1_r6()
8813 ctx->btarget = btarget; in gen_compute_branch1_r6()
8817 ctx->hflags |= MIPS_HFLAG_BDS16; in gen_compute_branch1_r6()
8820 ctx->hflags |= MIPS_HFLAG_BDS32; in gen_compute_branch1_r6()
9071 ctx->base.is_jmp = DISAS_STOP; in gen_cp1()
9271 uint32_t func = ctx->opcode & 0x3f; in gen_farith()
9331 if (ctx->abs2008) { in gen_farith()
9352 if (ctx->abs2008) { in gen_farith()
9367 if (ctx->nan2008) { in gen_farith()
9382 if (ctx->nan2008) { in gen_farith()
9397 if (ctx->nan2008) { in gen_farith()
9412 if (ctx->nan2008) { in gen_farith()
9425 if (ctx->nan2008) { in gen_farith()
9438 if (ctx->nan2008) { in gen_farith()
9451 if (ctx->nan2008) { in gen_farith()
9464 if (ctx->nan2008) { in gen_farith()
9581 if (ctx->insn_flags & ISA_MIPS_R6) { in gen_farith()
9605 if (ctx->insn_flags & ISA_MIPS_R6) { in gen_farith()
9627 if (ctx->insn_flags & ISA_MIPS_R6) { in gen_farith()
9648 if (ctx->insn_flags & ISA_MIPS_R6) { in gen_farith()
9686 if (ctx->nan2008) { in gen_farith()
9701 if (ctx->nan2008) { in gen_farith()
9739 if (ctx->opcode & (1 << 6)) { in gen_farith()
9740 gen_cmpabs_s(ctx, func - 48, ft, fs, cc); in gen_farith()
9742 gen_cmp_s(ctx, func - 48, ft, fs, cc); in gen_farith()
9809 if (ctx->abs2008) { in gen_farith()
9832 if (ctx->abs2008) { in gen_farith()
9846 if (ctx->nan2008) { in gen_farith()
9860 if (ctx->nan2008) { in gen_farith()
9874 if (ctx->nan2008) { in gen_farith()
9888 if (ctx->nan2008) { in gen_farith()
9903 if (ctx->nan2008) { in gen_farith()
9918 if (ctx->nan2008) { in gen_farith()
9933 if (ctx->nan2008) { in gen_farith()
9948 if (ctx->nan2008) { in gen_farith()
10067 if (ctx->insn_flags & ISA_MIPS_R6) { in gen_farith()
10090 if (ctx->insn_flags & ISA_MIPS_R6) { in gen_farith()
10111 if (ctx->insn_flags & ISA_MIPS_R6) { in gen_farith()
10132 if (ctx->insn_flags & ISA_MIPS_R6) { in gen_farith()
10171 if (ctx->opcode & (1 << 6)) { in gen_farith()
10172 gen_cmpabs_d(ctx, func - 48, ft, fs, cc); in gen_farith()
10174 gen_cmp_d(ctx, func - 48, ft, fs, cc); in gen_farith()
10195 if (ctx->nan2008) { in gen_farith()
10209 if (ctx->nan2008) { in gen_farith()
10529 if (ctx->opcode & (1 << 6)) { in gen_farith()
10530 gen_cmpabs_ps(ctx, func - 48, ft, fs, cc); in gen_farith()
10532 gen_cmp_ps(ctx, func - 48, ft, fs, cc); in gen_farith()
10565 tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, mo_endian(ctx) | MO_SL); in gen_flt3_ldst()
10575 tcg_gen_qemu_ld_i64(fp0, t0, ctx->mem_idx, mo_endian(ctx) | MO_UQ); in gen_flt3_ldst()
10585 tcg_gen_qemu_ld_i64(fp0, t0, ctx->mem_idx, mo_endian(ctx) | MO_UQ); in gen_flt3_ldst()
10594 tcg_gen_qemu_st_i32(fp0, t0, ctx->mem_idx, mo_endian(ctx) | MO_UL); in gen_flt3_ldst()
10603 tcg_gen_qemu_st_i64(fp0, t0, ctx->mem_idx, mo_endian(ctx) | MO_UQ); in gen_flt3_ldst()
10612 tcg_gen_qemu_st_i64(fp0, t0, ctx->mem_idx, mo_endian(ctx) | MO_UQ); in gen_flt3_ldst()
10835 void gen_rdhwr(DisasContext *ctx, int rt, int rd, int sel) in gen_rdhwr() argument
10858 translator_io_start(&ctx->base); in gen_rdhwr()
10866 gen_save_pc(ctx->base.pc_next + 4); in gen_rdhwr()
10867 ctx->base.is_jmp = DISAS_EXIT; in gen_rdhwr()
10875 if (sel != 0) { in gen_rdhwr()
10897 if ((ctx->hflags & MIPS_HFLAG_CP0) || in gen_rdhwr()
10898 (ctx->hflags & MIPS_HFLAG_HWRENA_ULR)) { in gen_rdhwr()
10916 ctx->hflags &= ~MIPS_HFLAG_BMASK; in clear_branch_hflags()
10917 if (ctx->base.is_jmp == DISAS_NEXT) { in clear_branch_hflags()
10921 * It is not safe to save ctx->hflags as hflags may be changed in clear_branch_hflags()
10930 if (ctx->hflags & MIPS_HFLAG_BMASK) { in gen_branch()
10931 int proc_hflags = ctx->hflags & MIPS_HFLAG_BMASK; in gen_branch()
10934 ctx->base.is_jmp = DISAS_NORETURN; in gen_branch()
10937 gen_goto_tb(ctx, 0, ctx->base.pc_next + insn_bytes); in gen_branch()
10944 gen_goto_tb(ctx, 0, ctx->btarget); in gen_branch()
10948 gen_goto_tb(ctx, 0, ctx->btarget); in gen_branch()
10956 gen_goto_tb(ctx, 1, ctx->base.pc_next + insn_bytes); in gen_branch()
10958 gen_goto_tb(ctx, 0, ctx->btarget); in gen_branch()
10963 if (ctx->insn_flags & (ASE_MIPS16 | ASE_MICROMIPS)) { in gen_branch()
10993 int m16_lowbit = (ctx->hflags & MIPS_HFLAG_M16) != 0; in gen_compute_compact_branch()
10995 if (ctx->hflags & MIPS_HFLAG_BMASK) { in gen_compute_compact_branch()
10998 VADDR_PRIx "\n", ctx->base.pc_next); in gen_compute_compact_branch()
11012 ctx->btarget = addr_add(ctx, ctx->base.pc_next + 4, offset); in gen_compute_compact_branch()
11015 tcg_gen_movi_tl(cpu_gpr[31], ctx->base.pc_next + 4 + m16_lowbit); in gen_compute_compact_branch()
11023 ctx->btarget = addr_add(ctx, ctx->base.pc_next + 4, offset); in gen_compute_compact_branch()
11030 tcg_gen_movi_tl(cpu_gpr[31], ctx->base.pc_next + 4 + m16_lowbit); in gen_compute_compact_branch()
11035 ctx->btarget = addr_add(ctx, ctx->base.pc_next + 4, offset); in gen_compute_compact_branch()
11039 ctx->btarget = addr_add(ctx, ctx->base.pc_next + 4, offset); in gen_compute_compact_branch()
11047 ctx->btarget = addr_add(ctx, ctx->base.pc_next + 4, offset); in gen_compute_compact_branch()
11066 tcg_gen_movi_tl(cpu_gpr[31], ctx->base.pc_next + 4 + m16_lowbit); in gen_compute_compact_branch()
11069 ctx->hflags |= MIPS_HFLAG_BR; in gen_compute_compact_branch()
11072 tcg_gen_movi_tl(cpu_gpr[31], ctx->base.pc_next + 4 + m16_lowbit); in gen_compute_compact_branch()
11075 ctx->hflags |= MIPS_HFLAG_B; in gen_compute_compact_branch()
11203 gen_goto_tb(ctx, 1, ctx->btarget); in gen_compute_compact_branch()
11206 ctx->hflags |= MIPS_HFLAG_FBNSLOT; in gen_compute_compact_branch()
11215 if (extended && (ctx->hflags & MIPS_HFLAG_BMASK)) { in gen_addiupc()
11241 bool is_user = (ctx->hflags & MIPS_HFLAG_KSU) == MIPS_HFLAG_UM; in is_uhi()
11259 tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, mo_endian(ctx) | MO_SL); in gen_ldxs()
11299 * Values for microMIPS fmt field. Variable-width, depending on which
11331 if (!(ctx->insn_flags & INSN_OCTEON)) { in gen_mips_lx()
11346 tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_UB); in gen_mips_lx()
11350 tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, mo_endian(ctx) | MO_SW); in gen_mips_lx()
11354 tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, mo_endian(ctx) | MO_SL); in gen_mips_lx()
11359 tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, mo_endian(ctx) | MO_UQ); in gen_mips_lx()
11831 op2 = MASK_SHLL_QB(ctx->opcode); in gen_mipsdsp_shift()
11930 op2 = MASK_SHLL_OB(ctx->opcode); in gen_mipsdsp_shift()
12375 imm = (ctx->opcode >> 16) & 0xFF; in gen_mipsdsp_bitinsn()
12396 imm = (ctx->opcode >> 16) & 0x03FF; in gen_mipsdsp_bitinsn()
12420 imm = (ctx->opcode >> 16) & 0xFF; in gen_mipsdsp_bitinsn()
12432 imm = (ctx->opcode >> 16) & 0x03FF; in gen_mipsdsp_bitinsn()
12444 imm = (ctx->opcode >> 16) & 0x03FF; in gen_mipsdsp_bitinsn()
12683 switch (MASK_APPEND(ctx->opcode)) { in gen_mipsdsp_append()
12686 tcg_gen_deposit_tl(cpu_gpr[rt], t0, cpu_gpr[rt], sa, 32 - sa); in gen_mipsdsp_append()
12694 tcg_gen_shli_tl(t0, t0, 32 - sa); in gen_mipsdsp_append()
12704 tcg_gen_shri_tl(t0, t0, 8 * (4 - sa)); in gen_mipsdsp_append()
12717 switch (MASK_DAPPEND(ctx->opcode)) { in gen_mipsdsp_append()
12720 tcg_gen_deposit_tl(cpu_gpr[rt], t0, cpu_gpr[rt], sa, 64 - sa); in gen_mipsdsp_append()
12725 tcg_gen_shli_tl(t0, t0, 64 - (0x20 | sa)); in gen_mipsdsp_append()
12731 tcg_gen_shli_tl(t0, t0, 64 - sa); in gen_mipsdsp_append()
12739 tcg_gen_shri_tl(t0, t0, 8 * (8 - sa)); in gen_mipsdsp_append()
12832 imm = (ctx->opcode >> 20) & 0x3F; in gen_mipsdsp_accinsn()
12846 imm = (ctx->opcode >> 11) & 0x3FF; in gen_mipsdsp_accinsn()
12851 imm = (ctx->opcode >> 16) & 0x03FF; in gen_mipsdsp_accinsn()
12867 int shift = (ctx->opcode >> 19) & 0x7F; in gen_mipsdsp_accinsn()
12868 int ac = (ctx->opcode >> 11) & 0x03; in gen_mipsdsp_accinsn()
12876 int ac = (ctx->opcode >> 11) & 0x03; in gen_mipsdsp_accinsn()
12976 rs = (ctx->opcode >> 21) & 0x1f; in decode_opc_special_r6()
12977 rt = (ctx->opcode >> 16) & 0x1f; in decode_opc_special_r6()
12978 rd = (ctx->opcode >> 11) & 0x1f; in decode_opc_special_r6()
12979 sa = (ctx->opcode >> 6) & 0x1f; in decode_opc_special_r6()
12981 op1 = MASK_SPECIAL(ctx->opcode); in decode_opc_special_r6()
12987 op2 = MASK_R6_MULDIV(ctx->opcode); in decode_opc_special_r6()
13022 if (is_uhi(ctx, extract32(ctx->opcode, 6, 20))) { in decode_opc_special_r6()
13023 ctx->base.is_jmp = DISAS_SEMIHOST; in decode_opc_special_r6()
13025 if (ctx->hflags & MIPS_HFLAG_SBRI) { in decode_opc_special_r6()
13051 op2 = MASK_R6_MULDIV(ctx->opcode); in decode_opc_special_r6()
13080 int rs = extract32(ctx->opcode, 21, 5); in decode_opc_special_tx79()
13081 int rt = extract32(ctx->opcode, 16, 5); in decode_opc_special_tx79()
13082 int rd = extract32(ctx->opcode, 11, 5); in decode_opc_special_tx79()
13083 uint32_t op1 = MASK_SPECIAL(ctx->opcode); in decode_opc_special_tx79()
13130 rs = (ctx->opcode >> 21) & 0x1f; in decode_opc_special_legacy()
13131 rt = (ctx->opcode >> 16) & 0x1f; in decode_opc_special_legacy()
13132 rd = (ctx->opcode >> 11) & 0x1f; in decode_opc_special_legacy()
13134 op1 = MASK_SPECIAL(ctx->opcode); in decode_opc_special_legacy()
13152 if (env->CP0_Config1 & (1 << CP0C1_FP)) { in decode_opc_special_legacy()
13154 gen_movci(ctx, rd, rs, (ctx->opcode >> 18) & 0x7, in decode_opc_special_legacy()
13155 (ctx->opcode >> 16) & 1); in decode_opc_special_legacy()
13203 rs = (ctx->opcode >> 21) & 0x1f; in decode_opc_special()
13204 rt = (ctx->opcode >> 16) & 0x1f; in decode_opc_special()
13205 rd = (ctx->opcode >> 11) & 0x1f; in decode_opc_special()
13206 sa = (ctx->opcode >> 6) & 0x1f; in decode_opc_special()
13208 op1 = MASK_SPECIAL(ctx->opcode); in decode_opc_special()
13213 if ((ctx->insn_flags & ISA_MIPS_R6) && in decode_opc_special()
13214 (ctx->hflags & MIPS_HFLAG_BMASK)) { in decode_opc_special()
13224 switch ((ctx->opcode >> 21) & 0x1f) { in decode_opc_special()
13226 /* rotr is decoded as srl on non-R2 CPUs */ in decode_opc_special()
13227 if (ctx->insn_flags & ISA_MIPS_R2) { in decode_opc_special()
13250 switch ((ctx->opcode >> 6) & 0x1f) { in decode_opc_special()
13252 /* rotrv is decoded as srlv on non-R2 CPUs */ in decode_opc_special()
13253 if (ctx->insn_flags & ISA_MIPS_R2) { in decode_opc_special()
13285 gen_trap(ctx, op1, rs, rt, -1, extract32(ctx->opcode, 6, 10)); in decode_opc_special()
13300 generate_exception_break(ctx, extract32(ctx->opcode, 6, 20)); in decode_opc_special()
13304 gen_sync(extract32(ctx->opcode, 6, 5)); in decode_opc_special()
13318 switch ((ctx->opcode >> 21) & 0x1f) { in decode_opc_special()
13320 /* drotr is decoded as dsrl on non-R2 CPUs */ in decode_opc_special()
13321 if (ctx->insn_flags & ISA_MIPS_R2) { in decode_opc_special()
13336 switch ((ctx->opcode >> 21) & 0x1f) { in decode_opc_special()
13338 /* drotr32 is decoded as dsrl32 on non-R2 CPUs */ in decode_opc_special()
13339 if (ctx->insn_flags & ISA_MIPS_R2) { in decode_opc_special()
13368 switch ((ctx->opcode >> 6) & 0x1f) { in decode_opc_special()
13370 /* drotrv is decoded as dsrlv on non-R2 CPUs */ in decode_opc_special()
13371 if (ctx->insn_flags & ISA_MIPS_R2) { in decode_opc_special()
13387 if (ctx->insn_flags & ISA_MIPS_R6) { in decode_opc_special()
13389 } else if (ctx->insn_flags & INSN_R5900) { in decode_opc_special()
13403 rs = (ctx->opcode >> 21) & 0x1f; in decode_opc_special2_legacy()
13404 rt = (ctx->opcode >> 16) & 0x1f; in decode_opc_special2_legacy()
13405 rd = (ctx->opcode >> 11) & 0x1f; in decode_opc_special2_legacy()
13407 op1 = MASK_SPECIAL2(ctx->opcode); in decode_opc_special2_legacy()
13425 if (is_uhi(ctx, extract32(ctx->opcode, 6, 20))) { in decode_opc_special2_legacy()
13426 ctx->base.is_jmp = DISAS_SEMIHOST; in decode_opc_special2_legacy()
13457 rs = (ctx->opcode >> 21) & 0x1f; in decode_opc_special3_r6()
13458 rt = (ctx->opcode >> 16) & 0x1f; in decode_opc_special3_r6()
13459 rd = (ctx->opcode >> 11) & 0x1f; in decode_opc_special3_r6()
13460 sa = (ctx->opcode >> 6) & 0x1f; in decode_opc_special3_r6()
13461 imm = (int16_t)ctx->opcode >> 7; in decode_opc_special3_r6()
13463 op1 = MASK_SPECIAL3(ctx->opcode); in decode_opc_special3_r6()
13467 /* hint codes 24-31 are reserved and signal RI */ in decode_opc_special3_r6()
13474 if (ctx->hflags & MIPS_HFLAG_ITC_CACHE) { in decode_opc_special3_r6()
13490 op2 = MASK_BSHFL(ctx->opcode); in decode_opc_special3_r6()
13506 if (unlikely(ctx->gi <= 1)) { in decode_opc_special3_r6()
13510 switch ((ctx->opcode >> 6) & 3) { in decode_opc_special3_r6()
13515 gen_helper_0e1i(ginvt, cpu_gpr[rs], extract32(ctx->opcode, 8, 2)); in decode_opc_special3_r6()
13537 op2 = MASK_DBSHFL(ctx->opcode); in decode_opc_special3_r6()
13569 rs = (ctx->opcode >> 21) & 0x1f; in decode_opc_special3_legacy()
13570 rt = (ctx->opcode >> 16) & 0x1f; in decode_opc_special3_legacy()
13571 rd = (ctx->opcode >> 11) & 0x1f; in decode_opc_special3_legacy()
13573 op1 = MASK_SPECIAL3(ctx->opcode); in decode_opc_special3_legacy()
13580 if ((ctx->insn_flags & ASE_DSP_R2) && (op1 == OPC_MUL_PH_DSP)) { in decode_opc_special3_legacy()
13581 op2 = MASK_ADDUH_QB(ctx->opcode); in decode_opc_special3_legacy()
13613 op2 = MASK_LX(ctx->opcode); in decode_opc_special3_legacy()
13630 op2 = MASK_ABSQ_S_PH(ctx->opcode); in decode_opc_special3_legacy()
13661 op2 = MASK_ADDU_QB(ctx->opcode); in decode_opc_special3_legacy()
13699 op2 = MASK_CMPU_EQ_QB(ctx->opcode); in decode_opc_special3_legacy()
13741 op2 = MASK_DPA_W_PH(ctx->opcode); in decode_opc_special3_legacy()
13774 op2 = MASK_INSV(ctx->opcode); in decode_opc_special3_legacy()
13804 op2 = MASK_EXTR_W(ctx->opcode); in decode_opc_special3_legacy()
13837 op2 = MASK_ABSQ_S_QH(ctx->opcode); in decode_opc_special3_legacy()
13873 op2 = MASK_ADDU_OB(ctx->opcode); in decode_opc_special3_legacy()
13912 op2 = MASK_CMPU_EQ_OB(ctx->opcode); in decode_opc_special3_legacy()
13960 op2 = MASK_DEXTR_W(ctx->opcode); in decode_opc_special3_legacy()
13994 op2 = MASK_DPAQ_W_QH(ctx->opcode); in decode_opc_special3_legacy()
14033 op2 = MASK_INSV(ctx->opcode); in decode_opc_special3_legacy()
14076 uint32_t opc = MASK_MMI(ctx->opcode); in decode_mmi()
14077 int rs = extract32(ctx->opcode, 21, 5); in decode_mmi()
14078 int rt = extract32(ctx->opcode, 16, 5); in decode_mmi()
14079 int rd = extract32(ctx->opcode, 11, 5); in decode_mmi()
14107 * The TX79-specific instruction Store Quadword
14109 * +--------+-------+-------+------------------------+
14111 * +--------+-------+-------+------------------------+
14116 * +--------+-------+-------+-------+-------+--------+
14118 * +--------+-------+-------+-------+-------+--------+
14129 int base = extract32(ctx->opcode, 21, 5); in decode_mmi_sq()
14130 int rt = extract32(ctx->opcode, 16, 5); in decode_mmi_sq()
14131 int offset = extract32(ctx->opcode, 0, 16); in decode_mmi_sq()
14134 uint32_t op1 = MASK_SPECIAL3(ctx->opcode); in decode_mmi_sq()
14135 uint32_t op2 = extract32(ctx->opcode, 6, 5); in decode_mmi_sq()
14138 int rd = extract32(ctx->opcode, 11, 5); in decode_mmi_sq()
14156 rs = (ctx->opcode >> 21) & 0x1f; in decode_opc_special3()
14157 rt = (ctx->opcode >> 16) & 0x1f; in decode_opc_special3()
14158 rd = (ctx->opcode >> 11) & 0x1f; in decode_opc_special3()
14159 sa = (ctx->opcode >> 6) & 0x1f; in decode_opc_special3()
14160 imm = sextract32(ctx->opcode, 7, 9); in decode_opc_special3()
14162 op1 = MASK_SPECIAL3(ctx->opcode); in decode_opc_special3()
14169 if (ctx->eva) { in decode_opc_special3()
14197 if (ctx->hflags & MIPS_HFLAG_ITC_CACHE) { in decode_opc_special3()
14215 op2 = MASK_BSHFL(ctx->opcode); in decode_opc_special3()
14243 op2 = MASK_DBSHFL(ctx->opcode); in decode_opc_special3()
14260 op2 = MASK_DBSHFL(ctx->opcode); in decode_opc_special3()
14267 gen_rdhwr(ctx, rt, rd, extract32(ctx->opcode, 6, 3)); in decode_opc_special3()
14291 if (ctx->insn_flags & ISA_MIPS_R6) { in decode_opc_special3()
14306 op = MASK_OP_MAJOR(ctx->opcode); in decode_opc_legacy()
14307 rs = (ctx->opcode >> 21) & 0x1f; in decode_opc_legacy()
14308 rt = (ctx->opcode >> 16) & 0x1f; in decode_opc_legacy()
14309 rd = (ctx->opcode >> 11) & 0x1f; in decode_opc_legacy()
14310 sa = (ctx->opcode >> 6) & 0x1f; in decode_opc_legacy()
14311 imm = (int16_t)ctx->opcode; in decode_opc_legacy()
14318 if ((ctx->insn_flags & INSN_R5900) && (ctx->insn_flags & ASE_MMI)) { in decode_opc_legacy()
14323 if (TARGET_LONG_BITS == 32 && (ctx->insn_flags & ASE_MXU)) { in decode_opc_legacy()
14324 if (decode_ase_mxu(ctx, ctx->opcode)) { in decode_opc_legacy()
14332 if (ctx->insn_flags & INSN_R5900) { in decode_opc_legacy()
14342 op1 = MASK_REGIMM(ctx->opcode); in decode_opc_legacy()
14353 gen_compute_branch(ctx, op1, 4, rs, -1, imm << 2, 4); in decode_opc_legacy()
14357 if (ctx->insn_flags & ISA_MIPS_R6) { in decode_opc_legacy()
14360 gen_compute_branch(ctx, op1, 4, 0, -1, imm << 2, 4); in decode_opc_legacy()
14365 gen_compute_branch(ctx, op1, 4, rs, -1, imm << 2, 4); in decode_opc_legacy()
14376 gen_trap(ctx, op1, rs, -1, imm, 0); in decode_opc_legacy()
14388 ctx->base.is_jmp = DISAS_STOP; in decode_opc_legacy()
14395 gen_compute_branch(ctx, op1, 4, -1, -2, (int32_t)imm << 2, 4); in decode_opc_legacy()
14421 op1 = MASK_CP0(ctx->opcode); in decode_opc_legacy()
14454 gen_cp0(env, ctx, MASK_C0(ctx->opcode), rt, rd); in decode_opc_legacy()
14463 op2 = MASK_MFMC0(ctx->opcode); in decode_opc_legacy()
14487 if (ctx->vp) { in decode_opc_legacy()
14494 if (ctx->vp) { in decode_opc_legacy()
14508 ctx->base.is_jmp = DISAS_STOP; in decode_opc_legacy()
14519 gen_save_pc(ctx->base.pc_next + 4); in decode_opc_legacy()
14520 ctx->base.is_jmp = DISAS_EXIT; in decode_opc_legacy()
14545 if (ctx->insn_flags & ISA_MIPS_R6) { in decode_opc_legacy()
14569 offset = (int32_t)(ctx->opcode & 0x3FFFFFF) << 2; in decode_opc_legacy()
14574 if (ctx->insn_flags & ISA_MIPS_R6) { in decode_opc_legacy()
14587 if (ctx->insn_flags & ISA_MIPS_R6) { in decode_opc_legacy()
14630 if (ctx->insn_flags & INSN_R5900) { in decode_opc_legacy()
14653 if (ctx->insn_flags & INSN_R5900) { in decode_opc_legacy()
14661 if (ctx->hflags & MIPS_HFLAG_ITC_CACHE) { in decode_opc_legacy()
14680 op1 = MASK_CP1(ctx->opcode); in decode_opc_legacy()
14706 if (ctx->insn_flags & ISA_MIPS_R6) { in decode_opc_legacy()
14708 gen_compute_branch1_r6(ctx, MASK_CP1(ctx->opcode), in decode_opc_legacy()
14716 gen_compute_branch1(ctx, MASK_BC1(ctx->opcode), in decode_opc_legacy()
14723 gen_compute_branch1_r6(ctx, MASK_CP1(ctx->opcode), in decode_opc_legacy()
14737 gen_compute_branch1(ctx, MASK_BC1(ctx->opcode), in decode_opc_legacy()
14746 gen_farith(ctx, ctx->opcode & FOP(0x3f, 0x1f), rt, rd, sa, in decode_opc_legacy()
14752 int r6_op = ctx->opcode & FOP(0x3f, 0x1f); in decode_opc_legacy()
14754 if (ctx->insn_flags & ISA_MIPS_R6) { in decode_opc_legacy()
14778 gen_r6_cmp_s(ctx, ctx->opcode & 0x1f, rt, rd, sa); in decode_opc_legacy()
14802 gen_r6_cmp_d(ctx, ctx->opcode & 0x1f, rt, rd, sa); in decode_opc_legacy()
14805 gen_farith(ctx, ctx->opcode & FOP(0x3f, 0x1f), in decode_opc_legacy()
14811 gen_farith(ctx, ctx->opcode & FOP(0x3f, 0x1f), rt, rd, sa, in decode_opc_legacy()
14823 /* Compact branches [R6] and COP2 [non-R6] */ in decode_opc_legacy()
14826 if (ctx->insn_flags & ISA_MIPS_R6) { in decode_opc_legacy()
14829 sextract32(ctx->opcode << 2, 0, 28)); in decode_opc_legacy()
14830 } else if (ctx->insn_flags & ASE_LEXT) { in decode_opc_legacy()
14840 if (ctx->insn_flags & ISA_MIPS_R6) { in decode_opc_legacy()
14844 sextract32(ctx->opcode << 2, 0, 23)); in decode_opc_legacy()
14849 } else if (ctx->insn_flags & ASE_LEXT) { in decode_opc_legacy()
14864 if (ctx->CP0_Config1 & (1 << CP0C1_FP)) { in decode_opc_legacy()
14866 op1 = MASK_CP3(ctx->opcode); in decode_opc_legacy()
14914 if (ctx->insn_flags & INSN_R5900) { in decode_opc_legacy()
14935 if (ctx->insn_flags & INSN_R5900) { in decode_opc_legacy()
14942 if (ctx->insn_flags & ISA_MIPS_R6) { in decode_opc_legacy()
14959 if (ctx->insn_flags & ISA_MIPS_R6) { in decode_opc_legacy()
14968 if (ctx->insn_flags & ISA_MIPS_R6) { in decode_opc_legacy()
14986 offset = (int32_t)(ctx->opcode & 0x3FFFFFF) << 2; in decode_opc_legacy()
14995 gen_pcrel(ctx, ctx->opcode, ctx->base.pc_next, rs); in decode_opc_legacy()
15007 if (ctx->base.pc_next & 0x3) { in decode_opc()
15008 env->CP0_BadVAddr = ctx->base.pc_next; in decode_opc()
15014 if ((ctx->hflags & MIPS_HFLAG_BMASK_BASE) == MIPS_HFLAG_BL) { in decode_opc()
15018 tcg_gen_movi_i32(hflags, ctx->hflags & ~MIPS_HFLAG_BMASK); in decode_opc()
15019 gen_goto_tb(ctx, 1, ctx->base.pc_next + 4); in decode_opc()
15023 /* Transition to the auto-generated decoder. */ in decode_opc()
15026 if (cpu_supports_isa(env, INSN_R5900) && decode_ext_txx9(ctx, ctx->opcode)) { in decode_opc()
15029 if (cpu_supports_isa(env, INSN_VR54XX) && decode_ext_vr54xx(ctx, ctx->opcode)) { in decode_opc()
15032 if (TARGET_LONG_BITS == 64 && decode_ext_loongson(ctx, ctx->opcode)) { in decode_opc()
15036 if (ase_lcsr_available(env) && decode_ase_lcsr(ctx, ctx->opcode)) { in decode_opc()
15039 if (cpu_supports_isa(env, INSN_OCTEON) && decode_ext_octeon(ctx, ctx->opcode)) { in decode_opc()
15045 if (ase_msa_available(env) && decode_ase_msa(ctx, ctx->opcode)) { in decode_opc()
15050 if (cpu_supports_isa(env, ISA_MIPS_R6) && decode_isa_rel6(ctx, ctx->opcode)) { in decode_opc()
15066 ctx->page_start = ctx->base.pc_first & TARGET_PAGE_MASK; in mips_tr_init_disas_context()
15067 ctx->saved_pc = -1; in mips_tr_init_disas_context()
15068 ctx->insn_flags = env->insn_flags; in mips_tr_init_disas_context()
15069 ctx->CP0_Config0 = env->CP0_Config0; in mips_tr_init_disas_context()
15070 ctx->CP0_Config1 = env->CP0_Config1; in mips_tr_init_disas_context()
15071 ctx->CP0_Config2 = env->CP0_Config2; in mips_tr_init_disas_context()
15072 ctx->CP0_Config3 = env->CP0_Config3; in mips_tr_init_disas_context()
15073 ctx->CP0_Config5 = env->CP0_Config5; in mips_tr_init_disas_context()
15074 ctx->btarget = 0; in mips_tr_init_disas_context()
15075 ctx->kscrexist = (env->CP0_Config4 >> CP0C4_KScrExist) & 0xff; in mips_tr_init_disas_context()
15076 ctx->rxi = (env->CP0_Config3 >> CP0C3_RXI) & 1; in mips_tr_init_disas_context()
15077 ctx->ie = (env->CP0_Config4 >> CP0C4_IE) & 3; in mips_tr_init_disas_context()
15078 ctx->bi = (env->CP0_Config3 >> CP0C3_BI) & 1; in mips_tr_init_disas_context()
15079 ctx->bp = (env->CP0_Config3 >> CP0C3_BP) & 1; in mips_tr_init_disas_context()
15080 ctx->PAMask = env->PAMask; in mips_tr_init_disas_context()
15081 ctx->mvh = (env->CP0_Config5 >> CP0C5_MVH) & 1; in mips_tr_init_disas_context()
15082 ctx->eva = (env->CP0_Config5 >> CP0C5_EVA) & 1; in mips_tr_init_disas_context()
15083 ctx->sc = (env->CP0_Config3 >> CP0C3_SC) & 1; in mips_tr_init_disas_context()
15084 ctx->CP0_LLAddr_shift = env->CP0_LLAddr_shift; in mips_tr_init_disas_context()
15085 ctx->cmgcr = (env->CP0_Config3 >> CP0C3_CMGCR) & 1; in mips_tr_init_disas_context()
15087 ctx->hflags = (uint32_t)ctx->base.tb->flags; /* FIXME: maybe use 64 bits? */ in mips_tr_init_disas_context()
15088 ctx->ulri = (env->CP0_Config3 >> CP0C3_ULRI) & 1; in mips_tr_init_disas_context()
15089 ctx->ps = ((env->active_fpu.fcr0 >> FCR0_PS) & 1) || in mips_tr_init_disas_context()
15090 (env->insn_flags & (INSN_LOONGSON2E | INSN_LOONGSON2F)); in mips_tr_init_disas_context()
15091 ctx->vp = (env->CP0_Config5 >> CP0C5_VP) & 1; in mips_tr_init_disas_context()
15092 ctx->mrp = (env->CP0_Config5 >> CP0C5_MRP) & 1; in mips_tr_init_disas_context()
15093 ctx->nan2008 = (env->active_fpu.fcr31 >> FCR31_NAN2008) & 1; in mips_tr_init_disas_context()
15094 ctx->abs2008 = (env->active_fpu.fcr31 >> FCR31_ABS2008) & 1; in mips_tr_init_disas_context()
15095 ctx->mi = (env->CP0_Config5 >> CP0C5_MI) & 1; in mips_tr_init_disas_context()
15096 ctx->gi = (env->CP0_Config5 >> CP0C5_GI) & 3; in mips_tr_init_disas_context()
15099 ctx->mem_idx = MIPS_HFLAG_UM; in mips_tr_init_disas_context()
15101 ctx->mem_idx = hflags_mmu_index(ctx->hflags); in mips_tr_init_disas_context()
15103 ctx->default_tcg_memop_mask = (!(ctx->insn_flags & ISA_NANOMIPS32) && in mips_tr_init_disas_context()
15104 (ctx->insn_flags & (ISA_MIPS_R6 | in mips_tr_init_disas_context()
15113 if ((tb_cflags(ctx->base.tb) & CF_SINGLE_STEP) && in mips_tr_init_disas_context()
15114 (ctx->hflags & MIPS_HFLAG_BMASK)) { in mips_tr_init_disas_context()
15115 ctx->base.max_insns = 2; in mips_tr_init_disas_context()
15118 LOG_DISAS("\ntb %p idx %d hflags %04x\n", ctx->base.tb, ctx->mem_idx, in mips_tr_init_disas_context()
15119 ctx->hflags); in mips_tr_init_disas_context()
15130 tcg_gen_insn_start(ctx->base.pc_next, ctx->hflags & MIPS_HFLAG_BMASK, in mips_tr_insn_start()
15131 ctx->btarget); in mips_tr_insn_start()
15141 is_slot = ctx->hflags & MIPS_HFLAG_BMASK; in mips_tr_translate_insn()
15142 if (ctx->insn_flags & ISA_NANOMIPS32) { in mips_tr_translate_insn()
15143 ctx->opcode = translator_lduw(env, &ctx->base, ctx->base.pc_next); in mips_tr_translate_insn()
15145 } else if (!(ctx->hflags & MIPS_HFLAG_M16)) { in mips_tr_translate_insn()
15146 ctx->opcode = translator_ldl(env, &ctx->base, ctx->base.pc_next); in mips_tr_translate_insn()
15149 } else if (ctx->insn_flags & ASE_MICROMIPS) { in mips_tr_translate_insn()
15150 ctx->opcode = translator_lduw(env, &ctx->base, ctx->base.pc_next); in mips_tr_translate_insn()
15152 } else if (ctx->insn_flags & ASE_MIPS16) { in mips_tr_translate_insn()
15153 ctx->opcode = translator_lduw(env, &ctx->base, ctx->base.pc_next); in mips_tr_translate_insn()
15157 g_assert(ctx->base.is_jmp == DISAS_NORETURN); in mips_tr_translate_insn()
15161 if (ctx->hflags & MIPS_HFLAG_BMASK) { in mips_tr_translate_insn()
15162 if (!(ctx->hflags & (MIPS_HFLAG_BDS16 | MIPS_HFLAG_BDS32 | in mips_tr_translate_insn()
15170 if ((ctx->hflags & MIPS_HFLAG_M16) && in mips_tr_translate_insn()
15171 (ctx->hflags & MIPS_HFLAG_FBNSLOT)) { in mips_tr_translate_insn()
15182 if (ctx->base.is_jmp == DISAS_SEMIHOST) { in mips_tr_translate_insn()
15185 ctx->base.pc_next += insn_bytes; in mips_tr_translate_insn()
15187 if (ctx->base.is_jmp != DISAS_NEXT) { in mips_tr_translate_insn()
15193 * See mips_tr_init_disas_context about single-stepping a branch in mips_tr_translate_insn()
15196 if (ctx->base.pc_next - ctx->page_start >= TARGET_PAGE_SIZE in mips_tr_translate_insn()
15197 && !(tb_cflags(ctx->base.tb) & CF_SINGLE_STEP)) { in mips_tr_translate_insn()
15198 ctx->base.is_jmp = DISAS_TOO_MANY; in mips_tr_translate_insn()
15206 switch (ctx->base.is_jmp) { in mips_tr_tb_stop()
15208 gen_save_pc(ctx->base.pc_next); in mips_tr_tb_stop()
15214 gen_goto_tb(ctx, 0, ctx->base.pc_next); in mips_tr_tb_stop()
15311 env->active_tc.PC = data[0]; in mips_restore_state_to_opc()
15312 env->hflags &= ~MIPS_HFLAG_BMASK; in mips_restore_state_to_opc()
15313 env->hflags |= data[1]; in mips_restore_state_to_opc()
15314 switch (env->hflags & MIPS_HFLAG_BMASK_BASE) { in mips_restore_state_to_opc()
15320 env->btarget = data[2]; in mips_restore_state_to_opc()