Lines Matching full:env
37 CPUMIPSState *env = &c->env; in mips_vpe_is_wfi() local
43 return cpu->halted && mips_vpe_active(env); in mips_vpe_is_wfi()
49 CPUMIPSState *env = &c->env; in mips_vp_is_wfi() local
51 return cpu->halted && mips_vp_active(env); in mips_vp_is_wfi()
80 CPUMIPSState *c = &cpu->env; in mips_tc_wake()
90 CPUMIPSState *c = &cpu->env; in mips_tc_sleep()
100 * @env: CPU from which mapping is performed.
112 static CPUMIPSState *mips_cpu_map_tc(CPUMIPSState *env, int *tc) in mips_cpu_map_tc() argument
120 if (!(env->CP0_VPEConf0 & (1 << CP0VPEC0_MVP))) { in mips_cpu_map_tc()
122 *tc = env->current_tc; in mips_cpu_map_tc()
123 return env; in mips_cpu_map_tc()
126 cs = env_cpu(env); in mips_cpu_map_tc()
131 return env; in mips_cpu_map_tc()
134 return &cpu->env; in mips_cpu_map_tc()
149 * static inline void sync_c0_status(CPUMIPSState *env, CPUMIPSState *cpu,
204 uint32_t cpu_mips_get_random(CPUMIPSState *env) in cpu_mips_get_random() argument
209 uint32_t nb_rand_tlb = env->tlb->nb_tlb - env->CP0_Wired; in cpu_mips_get_random()
212 return env->tlb->nb_tlb - 1; in cpu_mips_get_random()
222 idx = (seed >> 16) % nb_rand_tlb + env->CP0_Wired; in cpu_mips_get_random()
229 target_ulong helper_mfc0_mvpcontrol(CPUMIPSState *env) in helper_mfc0_mvpcontrol() argument
231 return env->mvp->CP0_MVPControl; in helper_mfc0_mvpcontrol()
234 target_ulong helper_mfc0_mvpconf0(CPUMIPSState *env) in helper_mfc0_mvpconf0() argument
236 return env->mvp->CP0_MVPConf0; in helper_mfc0_mvpconf0()
239 target_ulong helper_mfc0_mvpconf1(CPUMIPSState *env) in helper_mfc0_mvpconf1() argument
241 return env->mvp->CP0_MVPConf1; in helper_mfc0_mvpconf1()
244 target_ulong helper_mfc0_random(CPUMIPSState *env) in helper_mfc0_random() argument
246 return (int32_t)cpu_mips_get_random(env); in helper_mfc0_random()
249 target_ulong helper_mfc0_tcstatus(CPUMIPSState *env) in helper_mfc0_tcstatus() argument
251 return env->active_tc.CP0_TCStatus; in helper_mfc0_tcstatus()
254 target_ulong helper_mftc0_tcstatus(CPUMIPSState *env) in helper_mftc0_tcstatus() argument
256 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); in helper_mftc0_tcstatus()
257 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc); in helper_mftc0_tcstatus()
266 target_ulong helper_mfc0_tcbind(CPUMIPSState *env) in helper_mfc0_tcbind() argument
268 return env->active_tc.CP0_TCBind; in helper_mfc0_tcbind()
271 target_ulong helper_mftc0_tcbind(CPUMIPSState *env) in helper_mftc0_tcbind() argument
273 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); in helper_mftc0_tcbind()
274 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc); in helper_mftc0_tcbind()
283 target_ulong helper_mfc0_tcrestart(CPUMIPSState *env) in helper_mfc0_tcrestart() argument
285 return env->active_tc.PC; in helper_mfc0_tcrestart()
288 target_ulong helper_mftc0_tcrestart(CPUMIPSState *env) in helper_mftc0_tcrestart() argument
290 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); in helper_mftc0_tcrestart()
291 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc); in helper_mftc0_tcrestart()
300 target_ulong helper_mfc0_tchalt(CPUMIPSState *env) in helper_mfc0_tchalt() argument
302 return env->active_tc.CP0_TCHalt; in helper_mfc0_tchalt()
305 target_ulong helper_mftc0_tchalt(CPUMIPSState *env) in helper_mftc0_tchalt() argument
307 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); in helper_mftc0_tchalt()
308 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc); in helper_mftc0_tchalt()
317 target_ulong helper_mfc0_tccontext(CPUMIPSState *env) in helper_mfc0_tccontext() argument
319 return env->active_tc.CP0_TCContext; in helper_mfc0_tccontext()
322 target_ulong helper_mftc0_tccontext(CPUMIPSState *env) in helper_mftc0_tccontext() argument
324 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); in helper_mftc0_tccontext()
325 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc); in helper_mftc0_tccontext()
334 target_ulong helper_mfc0_tcschedule(CPUMIPSState *env) in helper_mfc0_tcschedule() argument
336 return env->active_tc.CP0_TCSchedule; in helper_mfc0_tcschedule()
339 target_ulong helper_mftc0_tcschedule(CPUMIPSState *env) in helper_mftc0_tcschedule() argument
341 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); in helper_mftc0_tcschedule()
342 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc); in helper_mftc0_tcschedule()
351 target_ulong helper_mfc0_tcschefback(CPUMIPSState *env) in helper_mfc0_tcschefback() argument
353 return env->active_tc.CP0_TCScheFBack; in helper_mfc0_tcschefback()
356 target_ulong helper_mftc0_tcschefback(CPUMIPSState *env) in helper_mftc0_tcschefback() argument
358 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); in helper_mftc0_tcschefback()
359 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc); in helper_mftc0_tcschefback()
368 target_ulong helper_mfc0_count(CPUMIPSState *env) in helper_mfc0_count() argument
370 return (int32_t)cpu_mips_get_count(env); in helper_mfc0_count()
373 target_ulong helper_mftc0_entryhi(CPUMIPSState *env) in helper_mftc0_entryhi() argument
375 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); in helper_mftc0_entryhi()
376 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc); in helper_mftc0_entryhi()
381 target_ulong helper_mftc0_cause(CPUMIPSState *env) in helper_mftc0_cause() argument
383 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); in helper_mftc0_cause()
384 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc); in helper_mftc0_cause()
389 target_ulong helper_mftc0_status(CPUMIPSState *env) in helper_mftc0_status() argument
391 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); in helper_mftc0_status()
392 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc); in helper_mftc0_status()
397 target_ulong helper_mfc0_lladdr(CPUMIPSState *env) in helper_mfc0_lladdr() argument
399 return (int32_t)(env->CP0_LLAddr >> env->CP0_LLAddr_shift); in helper_mfc0_lladdr()
402 target_ulong helper_mfc0_maar(CPUMIPSState *env) in helper_mfc0_maar() argument
404 return (int32_t) env->CP0_MAAR[env->CP0_MAARI]; in helper_mfc0_maar()
407 target_ulong helper_mfhc0_maar(CPUMIPSState *env) in helper_mfhc0_maar() argument
409 return env->CP0_MAAR[env->CP0_MAARI] >> 32; in helper_mfhc0_maar()
412 target_ulong helper_mfc0_watchlo(CPUMIPSState *env, uint32_t sel) in helper_mfc0_watchlo() argument
414 return (int32_t)env->CP0_WatchLo[sel]; in helper_mfc0_watchlo()
417 target_ulong helper_mfc0_watchhi(CPUMIPSState *env, uint32_t sel) in helper_mfc0_watchhi() argument
419 return (int32_t) env->CP0_WatchHi[sel]; in helper_mfc0_watchhi()
422 target_ulong helper_mfhc0_watchhi(CPUMIPSState *env, uint32_t sel) in helper_mfhc0_watchhi() argument
424 return env->CP0_WatchHi[sel] >> 32; in helper_mfhc0_watchhi()
427 target_ulong helper_mfc0_debug(CPUMIPSState *env) in helper_mfc0_debug() argument
429 target_ulong t0 = env->CP0_Debug; in helper_mfc0_debug()
430 if (env->hflags & MIPS_HFLAG_DM) { in helper_mfc0_debug()
437 target_ulong helper_mftc0_debug(CPUMIPSState *env) in helper_mftc0_debug() argument
439 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); in helper_mftc0_debug()
441 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc); in helper_mftc0_debug()
455 target_ulong helper_dmfc0_tcrestart(CPUMIPSState *env) in helper_dmfc0_tcrestart() argument
457 return env->active_tc.PC; in helper_dmfc0_tcrestart()
460 target_ulong helper_dmfc0_tchalt(CPUMIPSState *env) in helper_dmfc0_tchalt() argument
462 return env->active_tc.CP0_TCHalt; in helper_dmfc0_tchalt()
465 target_ulong helper_dmfc0_tccontext(CPUMIPSState *env) in helper_dmfc0_tccontext() argument
467 return env->active_tc.CP0_TCContext; in helper_dmfc0_tccontext()
470 target_ulong helper_dmfc0_tcschedule(CPUMIPSState *env) in helper_dmfc0_tcschedule() argument
472 return env->active_tc.CP0_TCSchedule; in helper_dmfc0_tcschedule()
475 target_ulong helper_dmfc0_tcschefback(CPUMIPSState *env) in helper_dmfc0_tcschefback() argument
477 return env->active_tc.CP0_TCScheFBack; in helper_dmfc0_tcschefback()
480 target_ulong helper_dmfc0_lladdr(CPUMIPSState *env) in helper_dmfc0_lladdr() argument
482 return env->CP0_LLAddr >> env->CP0_LLAddr_shift; in helper_dmfc0_lladdr()
485 target_ulong helper_dmfc0_maar(CPUMIPSState *env) in helper_dmfc0_maar() argument
487 return env->CP0_MAAR[env->CP0_MAARI]; in helper_dmfc0_maar()
490 target_ulong helper_dmfc0_watchlo(CPUMIPSState *env, uint32_t sel) in helper_dmfc0_watchlo() argument
492 return env->CP0_WatchLo[sel]; in helper_dmfc0_watchlo()
495 target_ulong helper_dmfc0_watchhi(CPUMIPSState *env, uint32_t sel) in helper_dmfc0_watchhi() argument
497 return env->CP0_WatchHi[sel]; in helper_dmfc0_watchhi()
502 void helper_mtc0_index(CPUMIPSState *env, target_ulong arg1) in helper_mtc0_index() argument
504 uint32_t index_p = env->CP0_Index & 0x80000000; in helper_mtc0_index()
506 if (tlb_index < env->tlb->nb_tlb) { in helper_mtc0_index()
507 if (env->insn_flags & ISA_MIPS_R6) { in helper_mtc0_index()
510 env->CP0_Index = index_p | tlb_index; in helper_mtc0_index()
514 void helper_mtc0_mvpcontrol(CPUMIPSState *env, target_ulong arg1) in helper_mtc0_mvpcontrol() argument
519 if (env->CP0_VPEConf0 & (1 << CP0VPEC0_MVP)) { in helper_mtc0_mvpcontrol()
523 if (env->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC)) { in helper_mtc0_mvpcontrol()
526 newval = (env->mvp->CP0_MVPControl & ~mask) | (arg1 & mask); in helper_mtc0_mvpcontrol()
530 env->mvp->CP0_MVPControl = newval; in helper_mtc0_mvpcontrol()
533 void helper_mtc0_vpecontrol(CPUMIPSState *env, target_ulong arg1) in helper_mtc0_vpecontrol() argument
540 newval = (env->CP0_VPEControl & ~mask) | (arg1 & mask); in helper_mtc0_vpecontrol()
549 env->CP0_VPEControl = newval; in helper_mtc0_vpecontrol()
552 void helper_mttc0_vpecontrol(CPUMIPSState *env, target_ulong arg1) in helper_mttc0_vpecontrol() argument
554 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); in helper_mttc0_vpecontrol()
555 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc); in helper_mttc0_vpecontrol()
568 target_ulong helper_mftc0_vpecontrol(CPUMIPSState *env) in helper_mftc0_vpecontrol() argument
570 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); in helper_mftc0_vpecontrol()
571 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc); in helper_mftc0_vpecontrol()
576 target_ulong helper_mftc0_vpeconf0(CPUMIPSState *env) in helper_mftc0_vpeconf0() argument
578 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); in helper_mftc0_vpeconf0()
579 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc); in helper_mftc0_vpeconf0()
584 void helper_mtc0_vpeconf0(CPUMIPSState *env, target_ulong arg1) in helper_mtc0_vpeconf0() argument
589 if (env->CP0_VPEConf0 & (1 << CP0VPEC0_MVP)) { in helper_mtc0_vpeconf0()
590 if (env->CP0_VPEConf0 & (1 << CP0VPEC0_VPA)) { in helper_mtc0_vpeconf0()
595 newval = (env->CP0_VPEConf0 & ~mask) | (arg1 & mask); in helper_mtc0_vpeconf0()
599 env->CP0_VPEConf0 = newval; in helper_mtc0_vpeconf0()
602 void helper_mttc0_vpeconf0(CPUMIPSState *env, target_ulong arg1) in helper_mttc0_vpeconf0() argument
604 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); in helper_mttc0_vpeconf0()
605 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc); in helper_mttc0_vpeconf0()
616 void helper_mtc0_vpeconf1(CPUMIPSState *env, target_ulong arg1) in helper_mtc0_vpeconf1() argument
621 if (env->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC)) in helper_mtc0_vpeconf1()
624 newval = (env->CP0_VPEConf1 & ~mask) | (arg1 & mask); in helper_mtc0_vpeconf1()
631 env->CP0_VPEConf1 = newval; in helper_mtc0_vpeconf1()
634 void helper_mtc0_yqmask(CPUMIPSState *env, target_ulong arg1) in helper_mtc0_yqmask() argument
637 env->CP0_YQMask = 0x00000000; in helper_mtc0_yqmask()
640 void helper_mtc0_vpeopt(CPUMIPSState *env, target_ulong arg1) in helper_mtc0_vpeopt() argument
642 env->CP0_VPEOpt = arg1 & 0x0000ffff; in helper_mtc0_vpeopt()
645 #define MTC0_ENTRYLO_MASK(env) ((env->PAMask >> 6) & 0x3FFFFFFF) argument
647 void helper_mtc0_entrylo0(CPUMIPSState *env, target_ulong arg1) in helper_mtc0_entrylo0() argument
650 target_ulong rxi = arg1 & (env->CP0_PageGrain & (3u << CP0PG_XIE)); in helper_mtc0_entrylo0()
651 env->CP0_EntryLo0 = (arg1 & MTC0_ENTRYLO_MASK(env)) in helper_mtc0_entrylo0()
656 #define DMTC0_ENTRYLO_MASK(env) (env->PAMask >> 6) argument
658 void helper_dmtc0_entrylo0(CPUMIPSState *env, uint64_t arg1) in helper_dmtc0_entrylo0() argument
660 uint64_t rxi = arg1 & ((env->CP0_PageGrain & (3ull << CP0PG_XIE)) << 32); in helper_dmtc0_entrylo0()
661 env->CP0_EntryLo0 = (arg1 & DMTC0_ENTRYLO_MASK(env)) | rxi; in helper_dmtc0_entrylo0()
665 void helper_mtc0_tcstatus(CPUMIPSState *env, target_ulong arg1) in helper_mtc0_tcstatus() argument
667 uint32_t mask = env->CP0_TCStatus_rw_bitmask; in helper_mtc0_tcstatus()
670 newval = (env->active_tc.CP0_TCStatus & ~mask) | (arg1 & mask); in helper_mtc0_tcstatus()
672 env->active_tc.CP0_TCStatus = newval; in helper_mtc0_tcstatus()
673 sync_c0_tcstatus(env, env->current_tc, newval); in helper_mtc0_tcstatus()
676 void helper_mttc0_tcstatus(CPUMIPSState *env, target_ulong arg1) in helper_mttc0_tcstatus() argument
678 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); in helper_mttc0_tcstatus()
679 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc); in helper_mttc0_tcstatus()
689 void helper_mtc0_tcbind(CPUMIPSState *env, target_ulong arg1) in helper_mtc0_tcbind() argument
694 if (env->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC)) { in helper_mtc0_tcbind()
697 newval = (env->active_tc.CP0_TCBind & ~mask) | (arg1 & mask); in helper_mtc0_tcbind()
698 env->active_tc.CP0_TCBind = newval; in helper_mtc0_tcbind()
701 void helper_mttc0_tcbind(CPUMIPSState *env, target_ulong arg1) in helper_mttc0_tcbind() argument
703 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); in helper_mttc0_tcbind()
706 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc); in helper_mttc0_tcbind()
720 void helper_mtc0_tcrestart(CPUMIPSState *env, target_ulong arg1) in helper_mtc0_tcrestart() argument
722 env->active_tc.PC = arg1; in helper_mtc0_tcrestart()
723 env->active_tc.CP0_TCStatus &= ~(1 << CP0TCSt_TDS); in helper_mtc0_tcrestart()
724 env->CP0_LLAddr = 0; in helper_mtc0_tcrestart()
725 env->lladdr = 0; in helper_mtc0_tcrestart()
729 void helper_mttc0_tcrestart(CPUMIPSState *env, target_ulong arg1) in helper_mttc0_tcrestart() argument
731 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); in helper_mttc0_tcrestart()
732 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc); in helper_mttc0_tcrestart()
749 void helper_mtc0_tchalt(CPUMIPSState *env, target_ulong arg1) in helper_mtc0_tchalt() argument
751 MIPSCPU *cpu = env_archcpu(env); in helper_mtc0_tchalt()
753 env->active_tc.CP0_TCHalt = arg1 & 0x1; in helper_mtc0_tchalt()
756 if (env->active_tc.CP0_TCHalt & 1) { in helper_mtc0_tchalt()
757 mips_tc_sleep(cpu, env->current_tc); in helper_mtc0_tchalt()
759 mips_tc_wake(cpu, env->current_tc); in helper_mtc0_tchalt()
763 void helper_mttc0_tchalt(CPUMIPSState *env, target_ulong arg1) in helper_mttc0_tchalt() argument
765 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); in helper_mttc0_tchalt()
766 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc); in helper_mttc0_tchalt()
784 void helper_mtc0_tccontext(CPUMIPSState *env, target_ulong arg1) in helper_mtc0_tccontext() argument
786 env->active_tc.CP0_TCContext = arg1; in helper_mtc0_tccontext()
789 void helper_mttc0_tccontext(CPUMIPSState *env, target_ulong arg1) in helper_mttc0_tccontext() argument
791 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); in helper_mttc0_tccontext()
792 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc); in helper_mttc0_tccontext()
801 void helper_mtc0_tcschedule(CPUMIPSState *env, target_ulong arg1) in helper_mtc0_tcschedule() argument
803 env->active_tc.CP0_TCSchedule = arg1; in helper_mtc0_tcschedule()
806 void helper_mttc0_tcschedule(CPUMIPSState *env, target_ulong arg1) in helper_mttc0_tcschedule() argument
808 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); in helper_mttc0_tcschedule()
809 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc); in helper_mttc0_tcschedule()
818 void helper_mtc0_tcschefback(CPUMIPSState *env, target_ulong arg1) in helper_mtc0_tcschefback() argument
820 env->active_tc.CP0_TCScheFBack = arg1; in helper_mtc0_tcschefback()
823 void helper_mttc0_tcschefback(CPUMIPSState *env, target_ulong arg1) in helper_mttc0_tcschefback() argument
825 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); in helper_mttc0_tcschefback()
826 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc); in helper_mttc0_tcschefback()
835 void helper_mtc0_entrylo1(CPUMIPSState *env, target_ulong arg1) in helper_mtc0_entrylo1() argument
838 target_ulong rxi = arg1 & (env->CP0_PageGrain & (3u << CP0PG_XIE)); in helper_mtc0_entrylo1()
839 env->CP0_EntryLo1 = (arg1 & MTC0_ENTRYLO_MASK(env)) in helper_mtc0_entrylo1()
844 void helper_dmtc0_entrylo1(CPUMIPSState *env, uint64_t arg1) in helper_dmtc0_entrylo1() argument
846 uint64_t rxi = arg1 & ((env->CP0_PageGrain & (3ull << CP0PG_XIE)) << 32); in helper_dmtc0_entrylo1()
847 env->CP0_EntryLo1 = (arg1 & DMTC0_ENTRYLO_MASK(env)) | rxi; in helper_dmtc0_entrylo1()
851 void helper_mtc0_context(CPUMIPSState *env, target_ulong arg1) in helper_mtc0_context() argument
853 env->CP0_Context = (env->CP0_Context & 0x007FFFFF) | (arg1 & ~0x007FFFFF); in helper_mtc0_context()
856 void helper_mtc0_memorymapid(CPUMIPSState *env, target_ulong arg1) in helper_mtc0_memorymapid() argument
859 old = env->CP0_MemoryMapID; in helper_mtc0_memorymapid()
860 env->CP0_MemoryMapID = (int32_t) arg1; in helper_mtc0_memorymapid()
862 if (old != env->CP0_MemoryMapID) { in helper_mtc0_memorymapid()
863 cpu_mips_tlb_flush(env); in helper_mtc0_memorymapid()
867 void update_pagemask(CPUMIPSState *env, target_ulong arg1, int32_t *pagemask) in update_pagemask() argument
884 env->CP0_PageMask = mask << CP0PM_MASK; in update_pagemask()
891 env->CP0_PageMask = mask << CP0PM_MASK; in update_pagemask()
894 void helper_mtc0_pagemask(CPUMIPSState *env, target_ulong arg1) in helper_mtc0_pagemask() argument
896 update_pagemask(env, arg1, &env->CP0_PageMask); in helper_mtc0_pagemask()
899 void helper_mtc0_pagegrain(CPUMIPSState *env, target_ulong arg1) in helper_mtc0_pagegrain() argument
903 env->CP0_PageGrain = (arg1 & env->CP0_PageGrain_rw_bitmask) | in helper_mtc0_pagegrain()
904 (env->CP0_PageGrain & ~env->CP0_PageGrain_rw_bitmask); in helper_mtc0_pagegrain()
905 compute_hflags(env); in helper_mtc0_pagegrain()
906 restore_pamask(env); in helper_mtc0_pagegrain()
909 void helper_mtc0_segctl0(CPUMIPSState *env, target_ulong arg1) in helper_mtc0_segctl0() argument
911 CPUState *cs = env_cpu(env); in helper_mtc0_segctl0()
913 env->CP0_SegCtl0 = arg1 & CP0SC0_MASK; in helper_mtc0_segctl0()
917 void helper_mtc0_segctl1(CPUMIPSState *env, target_ulong arg1) in helper_mtc0_segctl1() argument
919 CPUState *cs = env_cpu(env); in helper_mtc0_segctl1()
921 env->CP0_SegCtl1 = arg1 & CP0SC1_MASK; in helper_mtc0_segctl1()
925 void helper_mtc0_segctl2(CPUMIPSState *env, target_ulong arg1) in helper_mtc0_segctl2() argument
927 CPUState *cs = env_cpu(env); in helper_mtc0_segctl2()
929 env->CP0_SegCtl2 = arg1 & CP0SC2_MASK; in helper_mtc0_segctl2()
933 void helper_mtc0_pwfield(CPUMIPSState *env, target_ulong arg1) in helper_mtc0_pwfield() argument
937 uint32_t old_ptei = (env->CP0_PWField >> CP0PF_PTEI) & 0x3FULL; in helper_mtc0_pwfield()
940 if ((env->insn_flags & ISA_MIPS_R6)) { in helper_mtc0_pwfield()
957 env->CP0_PWField = arg1 & mask; in helper_mtc0_pwfield()
960 ((env->insn_flags & ISA_MIPS_R6) && in helper_mtc0_pwfield()
962 env->CP0_PWField = (env->CP0_PWField & ~0x3FULL) | in helper_mtc0_pwfield()
967 uint32_t old_ptew = (env->CP0_PWField >> CP0PF_PTEW) & 0x3F; in helper_mtc0_pwfield()
970 if ((env->insn_flags & ISA_MIPS_R6)) { in helper_mtc0_pwfield()
984 env->CP0_PWField = arg1 & mask; in helper_mtc0_pwfield()
987 ((env->insn_flags & ISA_MIPS_R6) && in helper_mtc0_pwfield()
989 env->CP0_PWField = (env->CP0_PWField & ~0x3F) | in helper_mtc0_pwfield()
995 void helper_mtc0_pwsize(CPUMIPSState *env, target_ulong arg1) in helper_mtc0_pwsize() argument
998 env->CP0_PWSize = arg1 & 0x3F7FFFFFFFULL; in helper_mtc0_pwsize()
1000 env->CP0_PWSize = arg1 & 0x3FFFFFFF; in helper_mtc0_pwsize()
1004 void helper_mtc0_wired(CPUMIPSState *env, target_ulong arg1) in helper_mtc0_wired() argument
1006 if (env->insn_flags & ISA_MIPS_R6) { in helper_mtc0_wired()
1007 if (arg1 < env->tlb->nb_tlb) { in helper_mtc0_wired()
1008 env->CP0_Wired = arg1; in helper_mtc0_wired()
1011 env->CP0_Wired = arg1 % env->tlb->nb_tlb; in helper_mtc0_wired()
1015 void helper_mtc0_pwctl(CPUMIPSState *env, target_ulong arg1) in helper_mtc0_pwctl() argument
1019 env->CP0_PWCtl = (env->CP0_PWCtl & 0x000000C0) | (arg1 & 0x5C00003F); in helper_mtc0_pwctl()
1021 env->CP0_PWCtl = (arg1 & 0x800000FF); in helper_mtc0_pwctl()
1025 void helper_mtc0_srsconf0(CPUMIPSState *env, target_ulong arg1) in helper_mtc0_srsconf0() argument
1027 env->CP0_SRSConf0 |= arg1 & env->CP0_SRSConf0_rw_bitmask; in helper_mtc0_srsconf0()
1030 void helper_mtc0_srsconf1(CPUMIPSState *env, target_ulong arg1) in helper_mtc0_srsconf1() argument
1032 env->CP0_SRSConf1 |= arg1 & env->CP0_SRSConf1_rw_bitmask; in helper_mtc0_srsconf1()
1035 void helper_mtc0_srsconf2(CPUMIPSState *env, target_ulong arg1) in helper_mtc0_srsconf2() argument
1037 env->CP0_SRSConf2 |= arg1 & env->CP0_SRSConf2_rw_bitmask; in helper_mtc0_srsconf2()
1040 void helper_mtc0_srsconf3(CPUMIPSState *env, target_ulong arg1) in helper_mtc0_srsconf3() argument
1042 env->CP0_SRSConf3 |= arg1 & env->CP0_SRSConf3_rw_bitmask; in helper_mtc0_srsconf3()
1045 void helper_mtc0_srsconf4(CPUMIPSState *env, target_ulong arg1) in helper_mtc0_srsconf4() argument
1047 env->CP0_SRSConf4 |= arg1 & env->CP0_SRSConf4_rw_bitmask; in helper_mtc0_srsconf4()
1050 void helper_mtc0_hwrena(CPUMIPSState *env, target_ulong arg1) in helper_mtc0_hwrena() argument
1054 if ((env->CP0_Config1 & (1 << CP0C1_PC)) && in helper_mtc0_hwrena()
1055 (env->insn_flags & ISA_MIPS_R6)) { in helper_mtc0_hwrena()
1058 if (env->insn_flags & ISA_MIPS_R6) { in helper_mtc0_hwrena()
1061 if (env->CP0_Config3 & (1 << CP0C3_ULRI)) { in helper_mtc0_hwrena()
1065 env->hflags |= MIPS_HFLAG_HWRENA_ULR; in helper_mtc0_hwrena()
1067 env->hflags &= ~MIPS_HFLAG_HWRENA_ULR; in helper_mtc0_hwrena()
1071 env->CP0_HWREna = arg1 & mask; in helper_mtc0_hwrena()
1074 void helper_mtc0_count(CPUMIPSState *env, target_ulong arg1) in helper_mtc0_count() argument
1076 cpu_mips_store_count(env, arg1); in helper_mtc0_count()
1079 void helper_mtc0_entryhi(CPUMIPSState *env, target_ulong arg1) in helper_mtc0_entryhi() argument
1082 mask = (TARGET_PAGE_MASK << 1) | env->CP0_EntryHi_ASID_mask; in helper_mtc0_entryhi()
1083 if (((env->CP0_Config4 >> CP0C4_IE) & 0x3) >= 2) { in helper_mtc0_entryhi()
1089 if (env->insn_flags & ISA_MIPS_R6) { in helper_mtc0_entryhi()
1091 int config0_at = extract32(env->CP0_Config0, 13, 2); in helper_mtc0_entryhi()
1092 bool no_supervisor = (env->CP0_Status_rw_bitmask & 0x8) == 0; in helper_mtc0_entryhi()
1099 mask &= env->SEGMask; in helper_mtc0_entryhi()
1101 old = env->CP0_EntryHi; in helper_mtc0_entryhi()
1103 env->CP0_EntryHi = val; in helper_mtc0_entryhi()
1104 if (ase_mt_available(env)) { in helper_mtc0_entryhi()
1105 sync_c0_entryhi(env, env->current_tc); in helper_mtc0_entryhi()
1108 if ((old & env->CP0_EntryHi_ASID_mask) != in helper_mtc0_entryhi()
1109 (val & env->CP0_EntryHi_ASID_mask)) { in helper_mtc0_entryhi()
1110 tlb_flush(env_cpu(env)); in helper_mtc0_entryhi()
1114 void helper_mttc0_entryhi(CPUMIPSState *env, target_ulong arg1) in helper_mttc0_entryhi() argument
1116 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); in helper_mttc0_entryhi()
1117 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc); in helper_mttc0_entryhi()
1123 void helper_mtc0_compare(CPUMIPSState *env, target_ulong arg1) in helper_mtc0_compare() argument
1125 cpu_mips_store_compare(env, arg1); in helper_mtc0_compare()
1128 void helper_mtc0_status(CPUMIPSState *env, target_ulong arg1) in helper_mtc0_status() argument
1132 old = env->CP0_Status; in helper_mtc0_status()
1133 cpu_mips_store_status(env, arg1); in helper_mtc0_status()
1134 val = env->CP0_Status; in helper_mtc0_status()
1138 old, old & env->CP0_Cause & CP0Ca_IP_mask, in helper_mtc0_status()
1139 val, val & env->CP0_Cause & CP0Ca_IP_mask, in helper_mtc0_status()
1140 env->CP0_Cause); in helper_mtc0_status()
1141 switch (mips_env_mmu_index(env)) { in helper_mtc0_status()
1155 cpu_abort(env_cpu(env), "Invalid MMU mode!\n"); in helper_mtc0_status()
1161 void helper_mttc0_status(CPUMIPSState *env, target_ulong arg1) in helper_mttc0_status() argument
1163 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); in helper_mttc0_status()
1164 uint32_t mask = env->CP0_Status_rw_bitmask & ~0xf1000018; in helper_mttc0_status()
1165 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc); in helper_mttc0_status()
1168 sync_c0_status(env, other, other_tc); in helper_mttc0_status()
1171 void helper_mtc0_intctl(CPUMIPSState *env, target_ulong arg1) in helper_mtc0_intctl() argument
1173 env->CP0_IntCtl = (env->CP0_IntCtl & ~0x000003e0) | (arg1 & 0x000003e0); in helper_mtc0_intctl()
1176 void helper_mtc0_srsctl(CPUMIPSState *env, target_ulong arg1) in helper_mtc0_srsctl() argument
1179 env->CP0_SRSCtl = (env->CP0_SRSCtl & ~mask) | (arg1 & mask); in helper_mtc0_srsctl()
1182 void helper_mtc0_cause(CPUMIPSState *env, target_ulong arg1) in helper_mtc0_cause() argument
1184 cpu_mips_store_cause(env, arg1); in helper_mtc0_cause()
1187 void helper_mttc0_cause(CPUMIPSState *env, target_ulong arg1) in helper_mttc0_cause() argument
1189 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); in helper_mttc0_cause()
1190 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc); in helper_mttc0_cause()
1195 target_ulong helper_mftc0_epc(CPUMIPSState *env) in helper_mftc0_epc() argument
1197 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); in helper_mftc0_epc()
1198 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc); in helper_mftc0_epc()
1203 target_ulong helper_mftc0_ebase(CPUMIPSState *env) in helper_mftc0_ebase() argument
1205 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); in helper_mftc0_ebase()
1206 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc); in helper_mftc0_ebase()
1211 void helper_mtc0_ebase(CPUMIPSState *env, target_ulong arg1) in helper_mtc0_ebase() argument
1213 target_ulong mask = 0x3FFFF000 | env->CP0_EBaseWG_rw_bitmask; in helper_mtc0_ebase()
1214 if (arg1 & env->CP0_EBaseWG_rw_bitmask) { in helper_mtc0_ebase()
1217 env->CP0_EBase = (env->CP0_EBase & ~mask) | (arg1 & mask); in helper_mtc0_ebase()
1220 void helper_mttc0_ebase(CPUMIPSState *env, target_ulong arg1) in helper_mttc0_ebase() argument
1222 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); in helper_mttc0_ebase()
1223 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc); in helper_mttc0_ebase()
1224 target_ulong mask = 0x3FFFF000 | env->CP0_EBaseWG_rw_bitmask; in helper_mttc0_ebase()
1225 if (arg1 & env->CP0_EBaseWG_rw_bitmask) { in helper_mttc0_ebase()
1231 target_ulong helper_mftc0_configx(CPUMIPSState *env, target_ulong idx) in helper_mftc0_configx() argument
1233 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); in helper_mftc0_configx()
1234 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc); in helper_mftc0_configx()
1250 void helper_mtc0_config0(CPUMIPSState *env, target_ulong arg1) in helper_mtc0_config0() argument
1252 env->CP0_Config0 = (env->CP0_Config0 & 0x81FFFFF8) | (arg1 & 0x00000007); in helper_mtc0_config0()
1255 void helper_mtc0_config2(CPUMIPSState *env, target_ulong arg1) in helper_mtc0_config2() argument
1258 env->CP0_Config2 = (env->CP0_Config2 & 0x8FFF0FFF); in helper_mtc0_config2()
1261 void helper_mtc0_config3(CPUMIPSState *env, target_ulong arg1) in helper_mtc0_config3() argument
1263 if (env->insn_flags & ASE_MICROMIPS) { in helper_mtc0_config3()
1264 env->CP0_Config3 = (env->CP0_Config3 & ~(1 << CP0C3_ISA_ON_EXC)) | in helper_mtc0_config3()
1269 void helper_mtc0_config4(CPUMIPSState *env, target_ulong arg1) in helper_mtc0_config4() argument
1271 env->CP0_Config4 = (env->CP0_Config4 & (~env->CP0_Config4_rw_bitmask)) | in helper_mtc0_config4()
1272 (arg1 & env->CP0_Config4_rw_bitmask); in helper_mtc0_config4()
1275 void helper_mtc0_config5(CPUMIPSState *env, target_ulong arg1) in helper_mtc0_config5() argument
1277 env->CP0_Config5 = (env->CP0_Config5 & (~env->CP0_Config5_rw_bitmask)) | in helper_mtc0_config5()
1278 (arg1 & env->CP0_Config5_rw_bitmask); in helper_mtc0_config5()
1279 env->CP0_EntryHi_ASID_mask = (env->CP0_Config5 & (1 << CP0C5_MI)) ? in helper_mtc0_config5()
1280 0x0 : (env->CP0_Config4 & (1 << CP0C4_AE)) ? 0x3ff : 0xff; in helper_mtc0_config5()
1281 compute_hflags(env); in helper_mtc0_config5()
1284 void helper_mtc0_lladdr(CPUMIPSState *env, target_ulong arg1) in helper_mtc0_lladdr() argument
1286 target_long mask = env->CP0_LLAddr_rw_bitmask; in helper_mtc0_lladdr()
1287 arg1 = arg1 << env->CP0_LLAddr_shift; in helper_mtc0_lladdr()
1288 env->CP0_LLAddr = (env->CP0_LLAddr & ~mask) | (arg1 & mask); in helper_mtc0_lladdr()
1291 #define MTC0_MAAR_MASK(env) \ argument
1292 ((0x1ULL << 63) | ((env->PAMask >> 4) & ~0xFFFull) | 0x3)
1294 void helper_mtc0_maar(CPUMIPSState *env, target_ulong arg1) in helper_mtc0_maar() argument
1296 env->CP0_MAAR[env->CP0_MAARI] = arg1 & MTC0_MAAR_MASK(env); in helper_mtc0_maar()
1299 void helper_mthc0_maar(CPUMIPSState *env, target_ulong arg1) in helper_mthc0_maar() argument
1301 env->CP0_MAAR[env->CP0_MAARI] = in helper_mthc0_maar()
1302 (((uint64_t) arg1 << 32) & MTC0_MAAR_MASK(env)) | in helper_mthc0_maar()
1303 (env->CP0_MAAR[env->CP0_MAARI] & 0x00000000ffffffffULL); in helper_mthc0_maar()
1306 void helper_mtc0_maari(CPUMIPSState *env, target_ulong arg1) in helper_mtc0_maari() argument
1314 env->CP0_MAARI = MIPS_MAAR_MAX - 1; in helper_mtc0_maari()
1316 env->CP0_MAARI = index; in helper_mtc0_maari()
1324 void helper_mtc0_watchlo(CPUMIPSState *env, target_ulong arg1, uint32_t sel) in helper_mtc0_watchlo() argument
1330 env->CP0_WatchLo[sel] = (arg1 & ~0x7); in helper_mtc0_watchlo()
1333 void helper_mtc0_watchhi(CPUMIPSState *env, target_ulong arg1, uint32_t sel) in helper_mtc0_watchhi() argument
1335 uint64_t mask = 0x40000FF8 | (env->CP0_EntryHi_ASID_mask << CP0WH_ASID); in helper_mtc0_watchhi()
1336 uint64_t m_bit = env->CP0_WatchHi[sel] & (1 << CP0WH_M); /* read-only */ in helper_mtc0_watchhi()
1337 if ((env->CP0_Config5 >> CP0C5_MI) & 1) { in helper_mtc0_watchhi()
1340 env->CP0_WatchHi[sel] = m_bit | (arg1 & mask); in helper_mtc0_watchhi()
1341 env->CP0_WatchHi[sel] &= ~(env->CP0_WatchHi[sel] & arg1 & 0x7); in helper_mtc0_watchhi()
1344 void helper_mthc0_watchhi(CPUMIPSState *env, target_ulong arg1, uint32_t sel) in helper_mthc0_watchhi() argument
1346 env->CP0_WatchHi[sel] = ((uint64_t) (arg1) << 32) | in helper_mthc0_watchhi()
1347 (env->CP0_WatchHi[sel] & 0x00000000ffffffffULL); in helper_mthc0_watchhi()
1350 void helper_mtc0_xcontext(CPUMIPSState *env, target_ulong arg1) in helper_mtc0_xcontext() argument
1352 target_ulong mask = (1ULL << (env->SEGBITS - 7)) - 1; in helper_mtc0_xcontext()
1353 env->CP0_XContext = (env->CP0_XContext & mask) | (arg1 & ~mask); in helper_mtc0_xcontext()
1356 void helper_mtc0_framemask(CPUMIPSState *env, target_ulong arg1) in helper_mtc0_framemask() argument
1358 env->CP0_Framemask = arg1; /* XXX */ in helper_mtc0_framemask()
1361 void helper_mtc0_debug(CPUMIPSState *env, target_ulong arg1) in helper_mtc0_debug() argument
1363 env->CP0_Debug = (env->CP0_Debug & 0x8C03FC1F) | (arg1 & 0x13300120); in helper_mtc0_debug()
1365 env->hflags |= MIPS_HFLAG_DM; in helper_mtc0_debug()
1367 env->hflags &= ~MIPS_HFLAG_DM; in helper_mtc0_debug()
1371 void helper_mttc0_debug(CPUMIPSState *env, target_ulong arg1) in helper_mttc0_debug() argument
1373 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); in helper_mttc0_debug()
1375 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc); in helper_mttc0_debug()
1388 void helper_mtc0_performance0(CPUMIPSState *env, target_ulong arg1) in helper_mtc0_performance0() argument
1390 env->CP0_Performance0 = arg1 & 0x000007ff; in helper_mtc0_performance0()
1393 void helper_mtc0_errctl(CPUMIPSState *env, target_ulong arg1) in helper_mtc0_errctl() argument
1397 int32_t itc = env->itc_tag ? (arg1 & (1 << CP0EC_ITC)) : 0; in helper_mtc0_errctl()
1399 env->CP0_ErrCtl = wst | spr | itc; in helper_mtc0_errctl()
1402 env->hflags |= MIPS_HFLAG_ITC_CACHE; in helper_mtc0_errctl()
1404 env->hflags &= ~MIPS_HFLAG_ITC_CACHE; in helper_mtc0_errctl()
1408 void helper_mtc0_taglo(CPUMIPSState *env, target_ulong arg1) in helper_mtc0_taglo() argument
1410 if (env->hflags & MIPS_HFLAG_ITC_CACHE) { in helper_mtc0_taglo()
1416 env->CP0_TagLo = arg1; in helper_mtc0_taglo()
1418 env->CP0_TagLo = arg1 & 0xFFFFFCF6; in helper_mtc0_taglo()
1422 void helper_mtc0_datalo(CPUMIPSState *env, target_ulong arg1) in helper_mtc0_datalo() argument
1424 env->CP0_DataLo = arg1; /* XXX */ in helper_mtc0_datalo()
1427 void helper_mtc0_taghi(CPUMIPSState *env, target_ulong arg1) in helper_mtc0_taghi() argument
1429 env->CP0_TagHi = arg1; /* XXX */ in helper_mtc0_taghi()
1432 void helper_mtc0_datahi(CPUMIPSState *env, target_ulong arg1) in helper_mtc0_datahi() argument
1434 env->CP0_DataHi = arg1; /* XXX */ in helper_mtc0_datahi()
1438 target_ulong helper_mftgpr(CPUMIPSState *env, uint32_t sel) in helper_mftgpr() argument
1440 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); in helper_mftgpr()
1441 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc); in helper_mftgpr()
1450 target_ulong helper_mftlo(CPUMIPSState *env, uint32_t sel) in helper_mftlo() argument
1452 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); in helper_mftlo()
1453 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc); in helper_mftlo()
1462 target_ulong helper_mfthi(CPUMIPSState *env, uint32_t sel) in helper_mfthi() argument
1464 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); in helper_mfthi()
1465 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc); in helper_mfthi()
1474 target_ulong helper_mftacx(CPUMIPSState *env, uint32_t sel) in helper_mftacx() argument
1476 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); in helper_mftacx()
1477 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc); in helper_mftacx()
1486 target_ulong helper_mftdsp(CPUMIPSState *env) in helper_mftdsp() argument
1488 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); in helper_mftdsp()
1489 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc); in helper_mftdsp()
1498 void helper_mttgpr(CPUMIPSState *env, target_ulong arg1, uint32_t sel) in helper_mttgpr() argument
1500 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); in helper_mttgpr()
1501 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc); in helper_mttgpr()
1510 void helper_mttlo(CPUMIPSState *env, target_ulong arg1, uint32_t sel) in helper_mttlo() argument
1512 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); in helper_mttlo()
1513 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc); in helper_mttlo()
1522 void helper_mtthi(CPUMIPSState *env, target_ulong arg1, uint32_t sel) in helper_mtthi() argument
1524 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); in helper_mtthi()
1525 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc); in helper_mtthi()
1534 void helper_mttacx(CPUMIPSState *env, target_ulong arg1, uint32_t sel) in helper_mttacx() argument
1536 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); in helper_mttacx()
1537 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc); in helper_mttacx()
1546 void helper_mttdsp(CPUMIPSState *env, target_ulong arg1) in helper_mttdsp() argument
1548 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); in helper_mttdsp()
1549 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc); in helper_mttdsp()
1571 target_ulong helper_dvpe(CPUMIPSState *env) in helper_dvpe() argument
1574 target_ulong prev = env->mvp->CP0_MVPControl; in helper_dvpe()
1579 if (&other_cpu->env != env) { in helper_dvpe()
1580 other_cpu->env.mvp->CP0_MVPControl &= ~(1 << CP0MVPCo_EVP); in helper_dvpe()
1587 target_ulong helper_evpe(CPUMIPSState *env) in helper_evpe() argument
1590 target_ulong prev = env->mvp->CP0_MVPControl; in helper_evpe()
1595 if (&other_cpu->env != env in helper_evpe()
1599 other_cpu->env.mvp->CP0_MVPControl |= (1 << CP0MVPCo_EVP); in helper_evpe()
1607 target_ulong helper_dvp(CPUMIPSState *env) in helper_dvp() argument
1610 target_ulong prev = env->CP0_VPControl; in helper_dvp()
1612 if (!((env->CP0_VPControl >> CP0VPCtl_DIS) & 1)) { in helper_dvp()
1616 if (&other_cpu->env != env) { in helper_dvp()
1620 env->CP0_VPControl |= (1 << CP0VPCtl_DIS); in helper_dvp()
1625 target_ulong helper_evp(CPUMIPSState *env) in helper_evp() argument
1628 target_ulong prev = env->CP0_VPControl; in helper_evp()
1630 if ((env->CP0_VPControl >> CP0VPCtl_DIS) & 1) { in helper_evp()
1633 if ((&other_cpu->env != env) && !mips_vp_is_wfi(other_cpu)) { in helper_evp()
1641 env->CP0_VPControl &= ~(1 << CP0VPCtl_DIS); in helper_evp()