target/mips/cpu-defs.c.inc

4  *  Copyright (c) 2004-2005 Jocelyn Mayer
398         /* This is the TLB-based MMU core.  */
470            FIXME: Support IEEE 754-2008 FP.
472         .name = "mips32r6-generic",
643            WAIT instruction. */
672         .name = "MIPS64R2-generic",
826         .name = "Loongson-2E",
828         /* 64KB I-cache and d-cache. 4 way with 32 bit cache line size.  */
832            Loongson-2E has only Config0.  */
846         .name = "Loongson-2F",
848         /* 64KB I-cache and d-cache. 4 way with 32 bit cache line size.  */
852            Loongson-2F has only Config0.  */
866         .name = "Loongson-3A1000", /* Loongson-3A R1, GS464-based */
868         /* 64KB I-cache and d-cache. 4 way with 32 bit cache line size.  */
896         .name = "Loongson-3A4000", /* Loongson-3A R4, GS464V-based */
898         /* 64KB I-cache and d-cache. 4 way with 32 bit cache line size.  */
1030         env->fpus[i].fcr0 = def->CP1_fcr0;
1032     memcpy(&env->active_fpu, &env->fpus[0], sizeof(env->active_fpu));
1037     env->mvp = g_malloc0(sizeof(CPUMIPSMVPContext));
1045        and shareable TLB entries, MVP has allocatable TCs, 2 VPEs
1046        implemented, 5 TCs implemented. */
1047     env->mvp->CP0_MVPConf0 = (1U << CP0MVPC0_M) | (1 << CP0MVPC0_TLBS) |
1056     env->mvp->CP0_MVPConf0 |= (env->tlb->nb_tlb << CP0MVPC0_PTLBE);
1061     env->mvp->CP0_MVPConf1 = (1U << CP0MVPC1_CIM) | (1 << CP0MVPC1_CIF) |