81 static int typeb_imm(DisasContext *dc, int x)  in typeb_imm()  argument
83     if (dc->tb_flags & IMM_FLAG) {  in typeb_imm()
84         return deposit32(dc->ext_imm, 0, 16, x);  in typeb_imm()
92 static void t_sync_flags(DisasContext *dc)  in t_sync_flags()  argument
95     if ((dc->tb_flags ^ dc->base.tb->flags) & IFLAGS_TB_MASK) {  in t_sync_flags()
96         tcg_gen_movi_i32(cpu_iflags, dc->tb_flags & IFLAGS_TB_MASK);  in t_sync_flags()
100 static void gen_raise_exception(DisasContext *dc, uint32_t index)  in gen_raise_exception()  argument
103     dc->base.is_jmp = DISAS_NORETURN;  in gen_raise_exception()
106 static void gen_raise_exception_sync(DisasContext *dc, uint32_t index)  in gen_raise_exception_sync()  argument
108     t_sync_flags(dc);  in gen_raise_exception_sync()
109     tcg_gen_movi_i32(cpu_pc, dc->base.pc_next);  in gen_raise_exception_sync()
110     gen_raise_exception(dc, index);  in gen_raise_exception_sync()
113 static void gen_raise_hw_excp(DisasContext *dc, uint32_t esr_ec)  in gen_raise_hw_excp()  argument
118     gen_raise_exception_sync(dc, EXCP_HW_EXCP);  in gen_raise_hw_excp()
121 static void gen_goto_tb(DisasContext *dc, int n, target_ulong dest)  in gen_goto_tb()  argument
123     if (translator_use_goto_tb(&dc->base, dest)) {  in gen_goto_tb()
126         tcg_gen_exit_tb(dc->base.tb, n);  in gen_goto_tb()
131     dc->base.is_jmp = DISAS_NORETURN;  in gen_goto_tb()
138 static bool trap_illegal(DisasContext *dc, bool cond)  in trap_illegal()  argument
140     if (cond && (dc->tb_flags & MSR_EE)  in trap_illegal()
141         && dc->cfg->illegal_opcode_exception) {  in trap_illegal()
142         gen_raise_hw_excp(dc, ESR_EC_ILLEGAL_OP);  in trap_illegal()
151 static bool trap_userspace(DisasContext *dc, bool cond)  in trap_userspace()  argument
153     bool cond_user = cond && dc->mem_index == MMU_USER_IDX;  in trap_userspace()
155     if (cond_user && (dc->tb_flags & MSR_EE)) {  in trap_userspace()
156         gen_raise_hw_excp(dc, ESR_EC_PRIVINSN);  in trap_userspace()
165 static bool invalid_delay_slot(DisasContext *dc, const char *insn_type)  in invalid_delay_slot()  argument
167     if (dc->tb_flags & D_FLAG) {  in invalid_delay_slot()
170                       insn_type, (uint32_t)dc->base.pc_next);  in invalid_delay_slot()
176 static TCGv_i32 reg_for_read(DisasContext *dc, int reg)  in reg_for_read()  argument
181     if (!dc->r0_set) {  in reg_for_read()
182         if (dc->r0 == NULL) {  in reg_for_read()
183             dc->r0 = tcg_temp_new_i32();  in reg_for_read()
185         tcg_gen_movi_i32(dc->r0, 0);  in reg_for_read()
186         dc->r0_set = true;  in reg_for_read()
188     return dc->r0;  in reg_for_read()
191 static TCGv_i32 reg_for_write(DisasContext *dc, int reg)  in reg_for_write()  argument
196     if (dc->r0 == NULL) {  in reg_for_write()
197         dc->r0 = tcg_temp_new_i32();  in reg_for_write()
199     return dc->r0;  in reg_for_write()
202 static bool do_typea(DisasContext *dc, arg_typea *arg, bool side_effects,  in do_typea()  argument
211     rd = reg_for_write(dc, arg->rd);  in do_typea()
212     ra = reg_for_read(dc, arg->ra);  in do_typea()
213     rb = reg_for_read(dc, arg->rb);  in do_typea()
218 static bool do_typea0(DisasContext *dc, arg_typea0 *arg, bool side_effects,  in do_typea0()  argument
227     rd = reg_for_write(dc, arg->rd);  in do_typea0()
228     ra = reg_for_read(dc, arg->ra);  in do_typea0()
233 static bool do_typeb_imm(DisasContext *dc, arg_typeb *arg, bool side_effects,  in do_typeb_imm()  argument
242     rd = reg_for_write(dc, arg->rd);  in do_typeb_imm()
243     ra = reg_for_read(dc, arg->ra);  in do_typeb_imm()
248 static bool do_typeb_val(DisasContext *dc, arg_typeb *arg, bool side_effects,  in do_typeb_val()  argument
257     rd = reg_for_write(dc, arg->rd);  in do_typeb_val()
258     ra = reg_for_read(dc, arg->ra);  in do_typeb_val()
266     static bool trans_##NAME(DisasContext *dc, arg_typea *a) \
267     { return do_typea(dc, a, SE, FN); }
270     static bool trans_##NAME(DisasContext *dc, arg_typea *a) \
271     { return dc->cfg->CFG && do_typea(dc, a, SE, FN); }
274     static bool trans_##NAME(DisasContext *dc, arg_typea0 *a) \
275     { return do_typea0(dc, a, SE, FN); }
278     static bool trans_##NAME(DisasContext *dc, arg_typea0 *a) \
279     { return dc->cfg->CFG && do_typea0(dc, a, SE, FN); }
282     static bool trans_##NAME(DisasContext *dc, arg_typeb *a) \
283     { return do_typeb_imm(dc, a, SE, FNI); }
286     static bool trans_##NAME(DisasContext *dc, arg_typeb *a) \
287     { return dc->cfg->CFG && do_typeb_imm(dc, a, SE, FNI); }
290     static bool trans_##NAME(DisasContext *dc, arg_typeb *a) \
291     { return do_typeb_val(dc, a, SE, FN); }
483 static bool trans_imm(DisasContext *dc, arg_imm *arg)  in DO_TYPEA_CFG()
485     if (invalid_delay_slot(dc, "imm")) {  in DO_TYPEA_CFG()
488     dc->ext_imm = arg->imm << 16;  in DO_TYPEA_CFG()
489     tcg_gen_movi_i32(cpu_imm, dc->ext_imm);  in DO_TYPEA_CFG()
490     dc->tb_flags_to_set = IMM_FLAG;  in DO_TYPEA_CFG()
615 static bool trans_wdic(DisasContext *dc, arg_wdic *a)  in DO_TYPEA0()
618     trap_userspace(dc, true);  in DO_TYPEA0()
625 static TCGv compute_ldst_addr_typea(DisasContext *dc, int ra, int rb)  in DO_TYPEA()
642     if ((ra == 1 || rb == 1) && dc->cfg->stackprot) {  in DO_TYPEA()
648 static TCGv compute_ldst_addr_typeb(DisasContext *dc, int ra, int imm)  in compute_ldst_addr_typeb()  argument
661     if (ra == 1 && dc->cfg->stackprot) {  in compute_ldst_addr_typeb()
668 static TCGv compute_ldst_addr_ea(DisasContext *dc, int ra, int rb)  in compute_ldst_addr_ea()  argument
670     int addr_size = dc->cfg->addr_size;  in compute_ldst_addr_ea()
696 static void record_unaligned_ess(DisasContext *dc, int rd,  in record_unaligned_ess()  argument
699     uint32_t iflags = tcg_get_insn_start_param(dc->base.insn_start, 1);  in record_unaligned_ess()
706     tcg_set_insn_start_param(dc->base.insn_start, 1, iflags);  in record_unaligned_ess()
710 static bool do_load(DisasContext *dc, int rd, TCGv addr, MemOp mop,  in do_load()  argument
737         (dc->tb_flags & MSR_EE) &&  in do_load()
738         dc->cfg->unaligned_exceptions) {  in do_load()
739         record_unaligned_ess(dc, rd, size, false);  in do_load()
744     tcg_gen_qemu_ld_i32(reg_for_write(dc, rd), addr, mem_index, mop);  in do_load()
748 static bool trans_lbu(DisasContext *dc, arg_typea *arg)  in trans_lbu()  argument
750     TCGv addr = compute_ldst_addr_typea(dc, arg->ra, arg->rb);  in trans_lbu()
751     return do_load(dc, arg->rd, addr, MO_UB, dc->mem_index, false);  in trans_lbu()
754 static bool trans_lbur(DisasContext *dc, arg_typea *arg)  in trans_lbur()  argument
756     TCGv addr = compute_ldst_addr_typea(dc, arg->ra, arg->rb);  in trans_lbur()
757     return do_load(dc, arg->rd, addr, MO_UB, dc->mem_index, true);  in trans_lbur()
760 static bool trans_lbuea(DisasContext *dc, arg_typea *arg)  in trans_lbuea()  argument
762     if (trap_userspace(dc, true)) {  in trans_lbuea()
768     TCGv addr = compute_ldst_addr_ea(dc, arg->ra, arg->rb);  in trans_lbuea()
769     return do_load(dc, arg->rd, addr, MO_UB, MMU_NOMMU_IDX, false);  in trans_lbuea()
773 static bool trans_lbui(DisasContext *dc, arg_typeb *arg)  in trans_lbui()  argument
775     TCGv addr = compute_ldst_addr_typeb(dc, arg->ra, arg->imm);  in trans_lbui()
776     return do_load(dc, arg->rd, addr, MO_UB, dc->mem_index, false);  in trans_lbui()
779 static bool trans_lhu(DisasContext *dc, arg_typea *arg)  in trans_lhu()  argument
781     TCGv addr = compute_ldst_addr_typea(dc, arg->ra, arg->rb);  in trans_lhu()
782     return do_load(dc, arg->rd, addr, MO_TEUW, dc->mem_index, false);  in trans_lhu()
785 static bool trans_lhur(DisasContext *dc, arg_typea *arg)  in trans_lhur()  argument
787     TCGv addr = compute_ldst_addr_typea(dc, arg->ra, arg->rb);  in trans_lhur()
788     return do_load(dc, arg->rd, addr, MO_TEUW, dc->mem_index, true);  in trans_lhur()
791 static bool trans_lhuea(DisasContext *dc, arg_typea *arg)  in trans_lhuea()  argument
793     if (trap_userspace(dc, true)) {  in trans_lhuea()
799     TCGv addr = compute_ldst_addr_ea(dc, arg->ra, arg->rb);  in trans_lhuea()
800     return do_load(dc, arg->rd, addr, MO_TEUW, MMU_NOMMU_IDX, false);  in trans_lhuea()
804 static bool trans_lhui(DisasContext *dc, arg_typeb *arg)  in trans_lhui()  argument
806     TCGv addr = compute_ldst_addr_typeb(dc, arg->ra, arg->imm);  in trans_lhui()
807     return do_load(dc, arg->rd, addr, MO_TEUW, dc->mem_index, false);  in trans_lhui()
810 static bool trans_lw(DisasContext *dc, arg_typea *arg)  in trans_lw()  argument
812     TCGv addr = compute_ldst_addr_typea(dc, arg->ra, arg->rb);  in trans_lw()
813     return do_load(dc, arg->rd, addr, MO_TEUL, dc->mem_index, false);  in trans_lw()
816 static bool trans_lwr(DisasContext *dc, arg_typea *arg)  in trans_lwr()  argument
818     TCGv addr = compute_ldst_addr_typea(dc, arg->ra, arg->rb);  in trans_lwr()
819     return do_load(dc, arg->rd, addr, MO_TEUL, dc->mem_index, true);  in trans_lwr()
822 static bool trans_lwea(DisasContext *dc, arg_typea *arg)  in trans_lwea()  argument
824     if (trap_userspace(dc, true)) {  in trans_lwea()
830     TCGv addr = compute_ldst_addr_ea(dc, arg->ra, arg->rb);  in trans_lwea()
831     return do_load(dc, arg->rd, addr, MO_TEUL, MMU_NOMMU_IDX, false);  in trans_lwea()
835 static bool trans_lwi(DisasContext *dc, arg_typeb *arg)  in trans_lwi()  argument
837     TCGv addr = compute_ldst_addr_typeb(dc, arg->ra, arg->imm);  in trans_lwi()
838     return do_load(dc, arg->rd, addr, MO_TEUL, dc->mem_index, false);  in trans_lwi()
841 static bool trans_lwx(DisasContext *dc, arg_typea *arg)  in trans_lwx()  argument
843     TCGv addr = compute_ldst_addr_typea(dc, arg->ra, arg->rb);  in trans_lwx()
848     tcg_gen_qemu_ld_i32(cpu_res_val, addr, dc->mem_index, MO_TEUL);  in trans_lwx()
860 static bool do_store(DisasContext *dc, int rd, TCGv addr, MemOp mop,  in do_store()  argument
887         (dc->tb_flags & MSR_EE) &&  in do_store()
888         dc->cfg->unaligned_exceptions) {  in do_store()
889         record_unaligned_ess(dc, rd, size, true);  in do_store()
894     tcg_gen_qemu_st_i32(reg_for_read(dc, rd), addr, mem_index, mop);  in do_store()
898 static bool trans_sb(DisasContext *dc, arg_typea *arg)  in trans_sb()  argument
900     TCGv addr = compute_ldst_addr_typea(dc, arg->ra, arg->rb);  in trans_sb()
901     return do_store(dc, arg->rd, addr, MO_UB, dc->mem_index, false);  in trans_sb()
904 static bool trans_sbr(DisasContext *dc, arg_typea *arg)  in trans_sbr()  argument
906     TCGv addr = compute_ldst_addr_typea(dc, arg->ra, arg->rb);  in trans_sbr()
907     return do_store(dc, arg->rd, addr, MO_UB, dc->mem_index, true);  in trans_sbr()
910 static bool trans_sbea(DisasContext *dc, arg_typea *arg)  in trans_sbea()  argument
912     if (trap_userspace(dc, true)) {  in trans_sbea()
918     TCGv addr = compute_ldst_addr_ea(dc, arg->ra, arg->rb);  in trans_sbea()
919     return do_store(dc, arg->rd, addr, MO_UB, MMU_NOMMU_IDX, false);  in trans_sbea()
923 static bool trans_sbi(DisasContext *dc, arg_typeb *arg)  in trans_sbi()  argument
925     TCGv addr = compute_ldst_addr_typeb(dc, arg->ra, arg->imm);  in trans_sbi()
926     return do_store(dc, arg->rd, addr, MO_UB, dc->mem_index, false);  in trans_sbi()
929 static bool trans_sh(DisasContext *dc, arg_typea *arg)  in trans_sh()  argument
931     TCGv addr = compute_ldst_addr_typea(dc, arg->ra, arg->rb);  in trans_sh()
932     return do_store(dc, arg->rd, addr, MO_TEUW, dc->mem_index, false);  in trans_sh()
935 static bool trans_shr(DisasContext *dc, arg_typea *arg)  in trans_shr()  argument
937     TCGv addr = compute_ldst_addr_typea(dc, arg->ra, arg->rb);  in trans_shr()
938     return do_store(dc, arg->rd, addr, MO_TEUW, dc->mem_index, true);  in trans_shr()
941 static bool trans_shea(DisasContext *dc, arg_typea *arg)  in trans_shea()  argument
943     if (trap_userspace(dc, true)) {  in trans_shea()
949     TCGv addr = compute_ldst_addr_ea(dc, arg->ra, arg->rb);  in trans_shea()
950     return do_store(dc, arg->rd, addr, MO_TEUW, MMU_NOMMU_IDX, false);  in trans_shea()
954 static bool trans_shi(DisasContext *dc, arg_typeb *arg)  in trans_shi()  argument
956     TCGv addr = compute_ldst_addr_typeb(dc, arg->ra, arg->imm);  in trans_shi()
957     return do_store(dc, arg->rd, addr, MO_TEUW, dc->mem_index, false);  in trans_shi()
960 static bool trans_sw(DisasContext *dc, arg_typea *arg)  in trans_sw()  argument
962     TCGv addr = compute_ldst_addr_typea(dc, arg->ra, arg->rb);  in trans_sw()
963     return do_store(dc, arg->rd, addr, MO_TEUL, dc->mem_index, false);  in trans_sw()
966 static bool trans_swr(DisasContext *dc, arg_typea *arg)  in trans_swr()  argument
968     TCGv addr = compute_ldst_addr_typea(dc, arg->ra, arg->rb);  in trans_swr()
969     return do_store(dc, arg->rd, addr, MO_TEUL, dc->mem_index, true);  in trans_swr()
972 static bool trans_swea(DisasContext *dc, arg_typea *arg)  in trans_swea()  argument
974     if (trap_userspace(dc, true)) {  in trans_swea()
980     TCGv addr = compute_ldst_addr_ea(dc, arg->ra, arg->rb);  in trans_swea()
981     return do_store(dc, arg->rd, addr, MO_TEUL, MMU_NOMMU_IDX, false);  in trans_swea()
985 static bool trans_swi(DisasContext *dc, arg_typeb *arg)  in trans_swi()  argument
987     TCGv addr = compute_ldst_addr_typeb(dc, arg->ra, arg->imm);  in trans_swi()
988     return do_store(dc, arg->rd, addr, MO_TEUL, dc->mem_index, false);  in trans_swi()
991 static bool trans_swx(DisasContext *dc, arg_typea *arg)  in trans_swx()  argument
993     TCGv addr = compute_ldst_addr_typea(dc, arg->ra, arg->rb);  in trans_swx()
1016                                reg_for_write(dc, arg->rd),  in trans_swx()
1017                                dc->mem_index, MO_TEUL);  in trans_swx()
1039 static void setup_dslot(DisasContext *dc, bool type_b)  in setup_dslot()  argument
1041     dc->tb_flags_to_set |= D_FLAG;  in setup_dslot()
1042     if (type_b && (dc->tb_flags & IMM_FLAG)) {  in setup_dslot()
1043         dc->tb_flags_to_set |= BIMM_FLAG;  in setup_dslot()
1047 static bool do_branch(DisasContext *dc, int dest_rb, int dest_imm,  in do_branch()  argument
1052     if (invalid_delay_slot(dc, "branch")) {  in do_branch()
1056         setup_dslot(dc, dest_rb < 0);  in do_branch()
1060         tcg_gen_movi_i32(cpu_R[link], dc->base.pc_next);  in do_branch()
1064     add_pc = abs ? 0 : dc->base.pc_next;  in do_branch()
1066         dc->jmp_dest = -1;  in do_branch()
1069         dc->jmp_dest = add_pc + dest_imm;  in do_branch()
1070         tcg_gen_movi_i32(cpu_btarget, dc->jmp_dest);  in do_branch()
1072     dc->jmp_cond = TCG_COND_ALWAYS;  in do_branch()
1077     static bool trans_##NAME(DisasContext *dc, arg_typea_br *arg)          \
1078     { return do_branch(dc, arg->rb, 0, DELAY, ABS, LINK ? arg->rd : 0); }  \
1079     static bool trans_##NAMEI(DisasContext *dc, arg_typeb_br *arg)         \
1080     { return do_branch(dc, -1, arg->imm, DELAY, ABS, LINK ? arg->rd : 0); }
1089 static bool do_bcc(DisasContext *dc, int dest_rb, int dest_imm,  in DO_BR()
1094     if (invalid_delay_slot(dc, "bcc")) {  in DO_BR()
1098         setup_dslot(dc, dest_rb < 0);  in DO_BR()
1101     dc->jmp_cond = cond;  in DO_BR()
1104     tcg_gen_mov_i32(cpu_bvalue, reg_for_read(dc, ra));  in DO_BR()
1108         dc->jmp_dest = -1;  in DO_BR()
1109         tcg_gen_addi_i32(cpu_btarget, cpu_R[dest_rb], dc->base.pc_next);  in DO_BR()
1111         dc->jmp_dest = dc->base.pc_next + dest_imm;  in DO_BR()
1112         tcg_gen_movi_i32(cpu_btarget, dc->jmp_dest);  in DO_BR()
1117     next = tcg_constant_i32(dc->base.pc_next + (delay + 1) * 4);  in DO_BR()
1118     tcg_gen_movcond_i32(dc->jmp_cond, cpu_btarget,  in DO_BR()
1119                         reg_for_read(dc, ra), zero,  in DO_BR()
1126     static bool trans_##NAME(DisasContext *dc, arg_typea_bc *arg)       \
1127     { return do_bcc(dc, arg->rb, 0, COND, arg->ra, false); }            \
1128     static bool trans_##NAME##d(DisasContext *dc, arg_typea_bc *arg)    \
1129     { return do_bcc(dc, arg->rb, 0, COND, arg->ra, true); }             \
1130     static bool trans_##NAME##i(DisasContext *dc, arg_typeb_bc *arg)    \
1131     { return do_bcc(dc, -1, arg->imm, COND, arg->ra, false); }          \
1132     static bool trans_##NAME##id(DisasContext *dc, arg_typeb_bc *arg)   \
1133     { return do_bcc(dc, -1, arg->imm, COND, arg->ra, true); }
1142 static bool trans_brk(DisasContext *dc, arg_typea_br *arg)  in DO_BCC()
1144     if (trap_userspace(dc, true)) {  in DO_BCC()
1147     if (invalid_delay_slot(dc, "brk")) {  in DO_BCC()
1151     tcg_gen_mov_i32(cpu_pc, reg_for_read(dc, arg->rb));  in DO_BCC()
1153         tcg_gen_movi_i32(cpu_R[arg->rd], dc->base.pc_next);  in DO_BCC()
1158     dc->base.is_jmp = DISAS_EXIT;  in DO_BCC()
1162 static bool trans_brki(DisasContext *dc, arg_typeb_br *arg)  in trans_brki()  argument
1166     if (trap_userspace(dc, imm != 0x8 && imm != 0x18)) {  in trans_brki()
1169     if (invalid_delay_slot(dc, "brki")) {  in trans_brki()
1175         tcg_gen_movi_i32(cpu_R[arg->rd], dc->base.pc_next);  in trans_brki()
1182         gen_raise_exception_sync(dc, EXCP_SYSCALL);  in trans_brki()
1185         gen_raise_exception_sync(dc, EXCP_DEBUG);  in trans_brki()
1198         msr_to_set |= (dc->tb_flags & (MSR_UM | MSR_VM)) << 1;  in trans_brki()
1203     dc->base.is_jmp = DISAS_EXIT;  in trans_brki()
1209 static bool trans_mbar(DisasContext *dc, arg_mbar *arg)  in trans_mbar()  argument
1214     if (invalid_delay_slot(dc, "mbar")) {  in trans_mbar()
1225         if (trap_userspace(dc, true)) {  in trans_mbar()
1230         t_sync_flags(dc);  in trans_mbar()
1236         tcg_gen_movi_i32(cpu_pc, dc->base.pc_next + 4);  in trans_mbar()
1238         gen_raise_exception(dc, EXCP_HLT);  in trans_mbar()
1252     dc->base.is_jmp = DISAS_EXIT_NEXT;  in trans_mbar()
1256 static bool do_rts(DisasContext *dc, arg_typeb_bc *arg, int to_set)  in do_rts()  argument
1258     if (trap_userspace(dc, to_set)) {  in do_rts()
1261     if (invalid_delay_slot(dc, "rts")) {  in do_rts()
1265     dc->tb_flags_to_set |= to_set;  in do_rts()
1266     setup_dslot(dc, true);  in do_rts()
1268     dc->jmp_cond = TCG_COND_ALWAYS;  in do_rts()
1269     dc->jmp_dest = -1;  in do_rts()
1270     tcg_gen_addi_i32(cpu_btarget, reg_for_read(dc, arg->ra), arg->imm);  in do_rts()
1275     static bool trans_##NAME(DisasContext *dc, arg_typeb_bc *arg) \
1276     { return do_rts(dc, arg, IFLAG); }
1283 static bool trans_zero(DisasContext *dc, arg_zero *arg)  in DO_RTS()
1286     if (dc->cfg->opcode_0_illegal) {  in DO_RTS()
1287         trap_illegal(dc, true);  in DO_RTS()
1297 static void msr_read(DisasContext *dc, TCGv_i32 d)  in msr_read()  argument
1307 static bool do_msrclrset(DisasContext *dc, arg_type_msr *arg, bool set)  in do_msrclrset()  argument
1311     if (trap_userspace(dc, imm != MSR_C)) {  in do_msrclrset()
1316         msr_read(dc, cpu_R[arg->rd]);  in do_msrclrset()
1339         dc->base.is_jmp = DISAS_EXIT_NEXT;  in do_msrclrset()
1344 static bool trans_msrclr(DisasContext *dc, arg_type_msr *arg)  in trans_msrclr()  argument
1346     return do_msrclrset(dc, arg, false);  in trans_msrclr()
1349 static bool trans_msrset(DisasContext *dc, arg_type_msr *arg)  in trans_msrset()  argument
1351     return do_msrclrset(dc, arg, true);  in trans_msrset()
1354 static bool trans_mts(DisasContext *dc, arg_mts *arg)  in trans_mts()  argument
1356     if (trap_userspace(dc, true)) {  in trans_mts()
1369     TCGv_i32 src = reg_for_read(dc, arg->ra);  in trans_mts()
1408     dc->base.is_jmp = DISAS_EXIT_NEXT;  in trans_mts()
1413 static bool trans_mfs(DisasContext *dc, arg_mfs *arg)  in trans_mfs()  argument
1415     TCGv_i32 dest = reg_for_write(dc, arg->rd);  in trans_mfs()
1444         tcg_gen_movi_i32(dest, dc->base.pc_next);  in trans_mfs()
1447         msr_read(dc, dest);  in trans_mfs()
1503 static void do_rti(DisasContext *dc)  in do_rti()  argument
1514 static void do_rtb(DisasContext *dc)  in do_rtb()  argument
1524 static void do_rte(DisasContext *dc)  in do_rte()  argument
1536 static bool do_get(DisasContext *dc, int rd, int rb, int imm, int ctrl)  in do_get()  argument
1540     if (trap_userspace(dc, true)) {  in do_get()
1552     gen_helper_get(reg_for_write(dc, rd), t_id, t_ctrl);  in do_get()
1556 static bool trans_get(DisasContext *dc, arg_get *arg)  in trans_get()  argument
1558     return do_get(dc, arg->rd, 0, arg->imm, arg->ctrl);  in trans_get()
1561 static bool trans_getd(DisasContext *dc, arg_getd *arg)  in trans_getd()  argument
1563     return do_get(dc, arg->rd, arg->rb, 0, arg->ctrl);  in trans_getd()
1566 static bool do_put(DisasContext *dc, int ra, int rb, int imm, int ctrl)  in do_put()  argument
1570     if (trap_userspace(dc, true)) {  in do_put()
1582     gen_helper_put(t_id, t_ctrl, reg_for_read(dc, ra));  in do_put()
1586 static bool trans_put(DisasContext *dc, arg_put *arg)  in trans_put()  argument
1588     return do_put(dc, arg->ra, 0, arg->imm, arg->ctrl);  in trans_put()
1591 static bool trans_putd(DisasContext *dc, arg_putd *arg)  in trans_putd()  argument
1593     return do_put(dc, arg->ra, arg->rb, 0, arg->ctrl);  in trans_putd()
1598     DisasContext *dc = container_of(dcb, DisasContext, base);  in mb_tr_init_disas_context()  local
1602     dc->cfg = &cpu->cfg;  in mb_tr_init_disas_context()
1603     dc->tb_flags = dc->base.tb->flags;  in mb_tr_init_disas_context()
1604     dc->ext_imm = dc->base.tb->cs_base;  in mb_tr_init_disas_context()
1605     dc->r0 = NULL;  in mb_tr_init_disas_context()
1606     dc->r0_set = false;  in mb_tr_init_disas_context()
1607     dc->mem_index = cpu_mmu_index(cs, false);  in mb_tr_init_disas_context()
1608     dc->jmp_cond = dc->tb_flags & D_FLAG ? TCG_COND_ALWAYS : TCG_COND_NEVER;  in mb_tr_init_disas_context()
1609     dc->jmp_dest = -1;  in mb_tr_init_disas_context()
1611     bound = -(dc->base.pc_first | TARGET_PAGE_MASK) / 4;  in mb_tr_init_disas_context()
1612     dc->base.max_insns = MIN(dc->base.max_insns, bound);  in mb_tr_init_disas_context()
1621     DisasContext *dc = container_of(dcb, DisasContext, base);  in mb_tr_insn_start()  local
1623     tcg_gen_insn_start(dc->base.pc_next, dc->tb_flags & ~MSR_TB_MASK);  in mb_tr_insn_start()
1628     DisasContext *dc = container_of(dcb, DisasContext, base);  in mb_tr_translate_insn()  local
1632     if (dc->base.pc_next & 3) {  in mb_tr_translate_insn()
1634                   (uint32_t)dc->base.pc_next);  in mb_tr_translate_insn()
1637     dc->tb_flags_to_set = 0;  in mb_tr_translate_insn()
1639     ir = translator_ldl(cpu_env(cs), &dc->base, dc->base.pc_next);  in mb_tr_translate_insn()
1640     if (!decode(dc, ir)) {  in mb_tr_translate_insn()
1641         trap_illegal(dc, true);  in mb_tr_translate_insn()
1644     if (dc->r0) {  in mb_tr_translate_insn()
1645         dc->r0 = NULL;  in mb_tr_translate_insn()
1646         dc->r0_set = false;  in mb_tr_translate_insn()
1650     if ((dc->tb_flags & ~dc->tb_flags_to_set) & IMM_FLAG) {  in mb_tr_translate_insn()
1654     dc->tb_flags &= ~(IMM_FLAG | BIMM_FLAG | D_FLAG);  in mb_tr_translate_insn()
1655     dc->tb_flags |= dc->tb_flags_to_set;  in mb_tr_translate_insn()
1656     dc->base.pc_next += 4;  in mb_tr_translate_insn()
1658     if (dc->jmp_cond != TCG_COND_NEVER && !(dc->tb_flags & D_FLAG)) {  in mb_tr_translate_insn()
1662         uint32_t rt_ibe = dc->tb_flags & (DRTI_FLAG | DRTB_FLAG | DRTE_FLAG);  in mb_tr_translate_insn()
1664             dc->tb_flags &= ~(DRTI_FLAG | DRTB_FLAG | DRTE_FLAG);  in mb_tr_translate_insn()
1666                 do_rti(dc);  in mb_tr_translate_insn()
1668                 do_rtb(dc);  in mb_tr_translate_insn()
1670                 do_rte(dc);  in mb_tr_translate_insn()
1675         switch (dc->base.is_jmp) {  in mb_tr_translate_insn()
1688             dc->base.is_jmp = (rt_ibe ? DISAS_EXIT_JUMP : DISAS_JUMP);  in mb_tr_translate_insn()
1695             dc->base.is_jmp = DISAS_EXIT_JUMP;  in mb_tr_translate_insn()
1705     DisasContext *dc = container_of(dcb, DisasContext, base);  in mb_tr_tb_stop()  local
1707     if (dc->base.is_jmp == DISAS_NORETURN) {  in mb_tr_tb_stop()
1712     t_sync_flags(dc);  in mb_tr_tb_stop()
1714     switch (dc->base.is_jmp) {  in mb_tr_tb_stop()
1716         gen_goto_tb(dc, 0, dc->base.pc_next);  in mb_tr_tb_stop()
1722         tcg_gen_movi_i32(cpu_pc, dc->base.pc_next);  in mb_tr_tb_stop()
1730         if (dc->jmp_dest != -1 && !(tb_cflags(dc->base.tb) & CF_NO_GOTO_TB)) {  in mb_tr_tb_stop()
1734             if (dc->jmp_cond != TCG_COND_ALWAYS) {  in mb_tr_tb_stop()
1747                 tcg_gen_brcondi_i32(dc->jmp_cond, tmp, 0, taken);  in mb_tr_tb_stop()
1748                 gen_goto_tb(dc, 1, dc->base.pc_next);  in mb_tr_tb_stop()
1751             gen_goto_tb(dc, 0, dc->jmp_dest);  in mb_tr_tb_stop()
1767         gen_raise_exception(dc, EXCP_DEBUG);  in mb_tr_tb_stop()
1784     DisasContext dc;  in gen_intermediate_code()  local
1785     translator_loop(cpu, tb, max_insns, pc, host_pc, &mb_tr_ops, &dc.base);  in gen_intermediate_code()