39     MicroBlazeMMU *mmu = &env->mmu;  in mmu_flush_idx()  local
43     t = mmu->rams[RAM_TAG][idx];  in mmu_flush_idx()
59     MicroBlazeMMU *mmu = &env->mmu;  in mmu_change_pid()  local
66     for (i = 0; i < ARRAY_SIZE(mmu->rams[RAM_TAG]); i++) {  in mmu_change_pid()
68         t = mmu->rams[RAM_TAG][i];  in mmu_change_pid()
70             if (mmu->tids[i] && ((mmu->regs[MMU_R_PID] & 0xff) == mmu->tids[i]))  in mmu_change_pid()
80     MicroBlazeMMU *mmu = &cpu->env.mmu;  in mmu_translate()  local
87     for (i = 0; i < ARRAY_SIZE(mmu->rams[RAM_TAG]); i++) {  in mmu_translate()
91         t = mmu->rams[RAM_TAG][i];  in mmu_translate()
104             if (mmu->tids[i]  in mmu_translate()
105                 && ((mmu->regs[MMU_R_PID] & 0xff) != mmu->tids[i])) {  in mmu_translate()
110             d = mmu->rams[RAM_DATA][i];  in mmu_translate()
116             t0 = mmu->regs[MMU_R_ZPR] >> (30 - (tlb_zsel * 2));  in mmu_translate()
125             if (cpu->cfg.mmu == 1) {  in mmu_translate()
184     if (cpu->cfg.mmu < 2 || !cpu->cfg.mmu_tlb_access) {  in mmu_read()
203             i = env->mmu.regs[MMU_R_TLBX] & 0xff;  in mmu_read()
204             r = extract64(env->mmu.rams[rn & 1][i], ext * 32, 32);  in mmu_read()
206                 env->mmu.regs[MMU_R_PID] = env->mmu.tids[i];  in mmu_read()
215             r = env->mmu.regs[rn];  in mmu_read()
218             r = env->mmu.regs[rn];  in mmu_read()
239                   rn < 3 ? env->mmu.regs[rn] : env->mmu.regs[MMU_R_TLBX]);  in mmu_write()
241     if (cpu->cfg.mmu < 2 || !cpu->cfg.mmu_tlb_access) {  in mmu_write()
254             i = env->mmu.regs[MMU_R_TLBX] & 0xff;  in mmu_write()
260                 env->mmu.tids[i] = env->mmu.regs[MMU_R_PID] & 0xff;  in mmu_write()
263             tmp64 = env->mmu.rams[rn & 1][i];  in mmu_write()
264             env->mmu.rams[rn & 1][i] = deposit64(tmp64, ext * 32, 32, v);  in mmu_write()
275             if (v != env->mmu.regs[rn]) {  in mmu_write()
278             env->mmu.regs[rn] = v;  in mmu_write()
287             if (v != env->mmu.regs[rn]) {  in mmu_write()
289                 env->mmu.regs[rn] = v;  in mmu_write()
294             env->mmu.regs[rn] = deposit32(env->mmu.regs[rn], 0, 31, v);  in mmu_write()
310                 env->mmu.regs[MMU_R_TLBX] = lu.idx;  in mmu_write()
312                 env->mmu.regs[MMU_R_TLBX] |= R_TBLX_MISS_MASK;  in mmu_write()
322 void mmu_init(MicroBlazeMMU *mmu)  in mmu_init()  argument
325     for (i = 0; i < ARRAY_SIZE(mmu->regs); i++) {  in mmu_init()
326         mmu->regs[i] = 0;  in mmu_init()