Lines Matching +full:ext +full:- +full:regs
5 * Copyright (c) 2009-2012 PetaLogix Qld Pty Ltd.
24 #include "exec/exec-all.h"
25 #include "exec/page-protection.h"
40 MicroBlazeMMU *mmu = &env->mmu; in mmu_flush_idx()
44 t = mmu->rams[RAM_TAG][idx]; in mmu_flush_idx()
60 MicroBlazeMMU *mmu = &env->mmu; in mmu_change_pid()
67 for (i = 0; i < ARRAY_SIZE(mmu->rams[RAM_TAG]); i++) { in mmu_change_pid()
69 t = mmu->rams[RAM_TAG][i]; in mmu_change_pid()
71 if (mmu->tids[i] && ((mmu->regs[MMU_R_PID] & 0xff) == mmu->tids[i])) in mmu_change_pid()
77 /* rw - 0 = read, 1 = write, 2 = fetch. */
81 MicroBlazeMMU *mmu = &cpu->env.mmu; in mmu_translate()
87 lu->err = ERR_MISS; in mmu_translate()
88 for (i = 0; i < ARRAY_SIZE(mmu->rams[RAM_TAG]); i++) { in mmu_translate()
92 t = mmu->rams[RAM_TAG][i]; in mmu_translate()
100 mask = ~((uint64_t)tlb_size - 1); in mmu_translate()
105 if (mmu->tids[i] in mmu_translate()
106 && ((mmu->regs[MMU_R_PID] & 0xff) != mmu->tids[i])) { in mmu_translate()
111 d = mmu->rams[RAM_DATA][i]; in mmu_translate()
117 t0 = mmu->regs[MMU_R_ZPR] >> (30 - (tlb_zsel * 2)); in mmu_translate()
120 if (tlb_zsel > cpu->cfg.mmu_zones) { in mmu_translate()
126 if (cpu->cfg.mmu == 1) { in mmu_translate()
148 lu->err = ERR_PROT; in mmu_translate()
149 lu->prot = PAGE_READ; in mmu_translate()
151 lu->prot |= PAGE_WRITE; in mmu_translate()
155 lu->prot |=PAGE_EXEC; in mmu_translate()
162 lu->vaddr = tlb_tag; in mmu_translate()
163 lu->paddr = tlb_rpn & cpu->cfg.addr_mask; in mmu_translate()
164 lu->size = tlb_size; in mmu_translate()
165 lu->err = ERR_HIT; in mmu_translate()
166 lu->idx = i; in mmu_translate()
178 /* Writes/reads to the MMU's special regs end up here. */
179 uint32_t mmu_read(CPUMBState *env, bool ext, uint32_t rn) in mmu_read() argument
185 if (cpu->cfg.mmu < 2 || !cpu->cfg.mmu_tlb_access) { in mmu_read()
186 qemu_log_mask(LOG_GUEST_ERROR, "MMU access on MMU-less system\n"); in mmu_read()
189 if (ext && rn != MMU_R_TLBLO) { in mmu_read()
198 if (!(cpu->cfg.mmu_tlb_access & 1)) { in mmu_read()
204 i = env->mmu.regs[MMU_R_TLBX] & 0xff; in mmu_read()
205 r = extract64(env->mmu.rams[rn & 1][i], ext * 32, 32); in mmu_read()
207 env->mmu.regs[MMU_R_PID] = env->mmu.tids[i]; in mmu_read()
211 if (!(cpu->cfg.mmu_tlb_access & 1)) { in mmu_read()
216 r = env->mmu.regs[rn]; in mmu_read()
219 r = env->mmu.regs[rn]; in mmu_read()
222 qemu_log_mask(LOG_GUEST_ERROR, "TLBSX is write-only.\n"); in mmu_read()
232 void mmu_write(CPUMBState *env, bool ext, uint32_t rn, uint32_t v) in mmu_write() argument
240 rn < 3 ? env->mmu.regs[rn] : env->mmu.regs[MMU_R_TLBX]); in mmu_write()
242 if (cpu->cfg.mmu < 2 || !cpu->cfg.mmu_tlb_access) { in mmu_write()
243 qemu_log_mask(LOG_GUEST_ERROR, "MMU access on MMU-less system\n"); in mmu_write()
246 if (ext && rn != MMU_R_TLBLO) { in mmu_write()
255 i = env->mmu.regs[MMU_R_TLBX] & 0xff; in mmu_write()
260 i, env->pc); in mmu_write()
261 env->mmu.tids[i] = env->mmu.regs[MMU_R_PID] & 0xff; in mmu_write()
264 tmp64 = env->mmu.rams[rn & 1][i]; in mmu_write()
265 env->mmu.rams[rn & 1][i] = deposit64(tmp64, ext * 32, 32, v); in mmu_write()
268 if (cpu->cfg.mmu_tlb_access <= 1) { in mmu_write()
276 if (v != env->mmu.regs[rn]) { in mmu_write()
279 env->mmu.regs[rn] = v; in mmu_write()
282 if (cpu->cfg.mmu_tlb_access <= 1) { in mmu_write()
288 if (v != env->mmu.regs[rn]) { in mmu_write()
290 env->mmu.regs[rn] = v; in mmu_write()
294 /* Bit 31 is read-only. */ in mmu_write()
295 env->mmu.regs[rn] = deposit32(env->mmu.regs[rn], 0, 31, v); in mmu_write()
302 if (cpu->cfg.mmu_tlb_access <= 1) { in mmu_write()
311 env->mmu.regs[MMU_R_TLBX] = lu.idx; in mmu_write()
313 env->mmu.regs[MMU_R_TLBX] |= R_TBLX_MISS_MASK; in mmu_write()
326 for (i = 0; i < ARRAY_SIZE(mmu->regs); i++) { in mmu_init()
327 mmu->regs[i] = 0; in mmu_init()